Fixed-Point IP Cores (ALTERA_FIXED-POINT_FUNCTIONS) User Guide

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UG-20067 | 2017.03.31

About Fixed-Point IP Cores

The fixed-point IP cores (ALTERA_FIXED-POINT_FUNCTIONS) allow you to implement simple fixed-point functions in your FPGA design. These IP cores are fully parameterizable.

The fixed-point IP cores include functions for:

Parallel add
Multiply
Divide
Square root
Simple counter
Loadable counter
Integer divide

This IP core targets Arria^® 10 devices only.

Feature

Optimized for Altera^® HyperFlex™ FPGA architecture
Configurable frequency and latency targets for add, multiply, divide, and square root functions.

Getting Started

Installing and Licensing IP Cores

The Quartus^® Prime software installation includes the Altera FPGA IP library. This library provides useful IP core functions for your production use without the need for an additional license. Some IP cores in the library require that you purchase a separate license for production use. The OpenCore^® feature allows evaluation of any Altera FPGA IP core in simulation and compilation in the Quartus^® Prime software. Upon satisfaction with functionality and performance, visit the Self Service Licensing Center to obtain a license number for any Altera FPGA product.

The Quartus^® Prime software installs IP cores in the following locations by default:

Figure 1. IP Core Installation Path

Table 1. IP Core Installation Locations
Location	Software	Platform
`<drive>`:\intelFPGA_pro\quartus\ip\altera	Quartus^® Prime Pro Edition	Windows^®
`<drive>`:\intelFPGA\quartus\ip\altera	Quartus^® Prime Standard Edition	Windows
`<home directory>`:/intelFPGA_pro/quartus/ip/altera	Quartus^® Prime Pro Edition	Linux^®
`<home directory>`:/intelFPGA/quartus/ip/altera	Quartus^® Prime Standard Edition	Linux

Design Flow

Use the IP Catalog and parameter editor to define and instantiate complex IP cores. Using the GUI ensures that you set all IP core ports and parameters properly.

If you are an expert user, and choose to configure the IP core directly through parameterized instantiation in your design, refer to the port and parameter details. The details of these ports and parameters are hidden in the parameter editor.

IP Catalog and Parameter Editor

The IP Catalog displays the IP cores available for your project. Use the following features of the IP Catalog to locate and customize an IP core:

Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.
Type in the Search field to locate any full or partial IP core name in IP Catalog.
Right-click an IP core name in IP Catalog to display details about supported devices, to open the IP core's installation folder, and for links to IP documentation.
Click Search for Partner IP to access partner IP information on the web.

The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Quartus^® Prime IP file (.ip) for an IP variation in Quartus^® Prime Pro Edition projects.

The parameter editor generates a top-level Quartus IP file (.qip) for an IP variation in Quartus^® Prime Standard Edition projects. These files represent the IP variation in the project, and store parameterization information.

Figure 2. IP Parameter Editor ( Quartus^® Prime Pro Edition)

Figure 3. IP Parameter Editor ( Quartus^® Prime Standard Edition)

The Parameter Editor

The parameter editor helps you to configure IP core ports, parameters, and output file generation options. The basic parameter editor controls include the following:

Use the Presets window to apply preset parameter values for specific applications (for select cores).
Use the Details window to view port and parameter descriptions, and click links to documentation.
Click Generate > Generate Testbench System to generate a testbench system (for select cores).
Click Generate > Generate Example Design to generate an example design (for select cores).
Click Validate System Integrity to validate a system's generic components against companion files. (Qsys Pro systems only)
Click Sync All System Infos to validate a system's generic components against companion files. (Qsys Pro systems only)

The IP Catalog is also available in Qsys and Qsys Pro (View > IP Catalog). The Qsys IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Quartus^® Prime IP Catalog. Refer to Creating a System with Qsys Pro or Creating a System with Qsys for information on use of IP in Qsys and Qsys Pro, respectively.

Generating IP Cores ( Quartus Prime Pro Edition)

Quickly configure a custom IP variation in the Quartus^® Prime parameter editor.

Double-click any component in the IP Catalog to launch the parameter editor. The parameter editor allows you to define a custom variation of the selected IP core. The parameter editor generates the IP variation synthesis and optional simulation files, and adds the .ip file representing the variation to your project automatically.

IP Parameter Editor ( Quartus^® Prime Pro Edition)

Follow these steps to locate, instantiate, and customize an IP core in the parameter editor:

Create or open a Quartus^® Prime project (.qpf) to contain the instantiated IP variation.
In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. To locate a specific component, type some or all of the component’s name in the IP Catalog search box. The New IP Variation window appears.
Specify a top-level name for your custom IP variation. Do not include spaces in IP variation names or paths. The parameter editor saves the IP variation settings in a file named <your_ip> .ip. Click OK. The parameter editor appears.
Set the parameter values in the parameter editor and view the block diagram for the component. The Parameterization Messages tab at the bottom displays any errors in IP parameters:
- Optionally, select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications.
- Specify parameters defining the IP core functionality, port configurations, and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
Note: Refer to your IP core user guide for information about specific IP core parameters.
Click Generate HDL. The Generation dialog box appears.
Specify output file generation options, and then click Generate. The synthesis and/or simulation files generate according to your specifications.
To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.

Note: Some IP cores generate different HDL implementations according to the IP core parameters. The underlying RTL of these IP cores contains a unique hash code that prevents module name collisions between different variations of the IP core. This unique code remains consistent, given the same IP settings and software version during IP generation. This unique code can change if you edit the IP core's parameters or upgrade the IP core version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script.

IP Core Generation Output ( Quartus Prime Pro Edition)

The Quartus^® Prime software generates the following output file structure for individual IP cores that are not part of a Qsys Pro system.

Figure 4. Individual IP Core Generation Output ( Quartus^® Prime Pro Edition)

Table 2. Files Generated for IP Cores
File Name	Description
<`your_ip`>.ip	Top-level IP variation file that contains the parameterization of an IP core in your project. If the IP variation is part of a Qsys Pro system, the parameter editor also generates a .qsys file.
<`your_ip`>.cmp	The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you use in VHDL design files.
<`your_ip`>_generation.rpt	IP or Qsys Pro generation log file. Displays a summary of the messages during IP generation.
<`your_ip`>.qgsimc (Qsys Pro systems only)	Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Qsys Pro system and IP core. This comparison determines if Qsys Pro can skip regeneration of the HDL.
<`your_ip`>.qgsynth (Qsys Pro systems only)	Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Qsys Pro system and IP core. This comparison determines if Qsys Pro can skip regeneration of the HDL.
<`your_ip`>.qip	Contains all information to integrate and compile the IP component.
<`your_ip`>.csv	Contains information about the upgrade status of the IP component.
`<your_ip>`.bsf	A symbol representation of the IP variation for use in Block Diagram Files (.bdf).
<`your_ip`>.spd	Required input file for `ip-make-simscript` to generate simulation scripts for supported simulators. The .spd file contains a list of files you generate for simulation, along with information about memories that you initialize.
<`your_ip`>.ppf	The Pin Planner File (.ppf) stores the port and node assignments for IP components you create for use with the Pin Planner.
<`your_ip`>_bb.v	Use the Verilog blackbox (_bb.v) file as an empty module declaration for use as a blackbox.
<`your_ip`>_inst.v or _inst.vhd	HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation.
<`your_ip`>.regmap	If the IP contains register information, the Quartus^® Prime software generates the .regmap file. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console.
<`your_ip`>.svd	Allows HPS System Debug tools to view the register maps of peripherals that connect to HPS within a Qsys Pro system. During synthesis, the Quartus^® Prime software stores the .svd files for slave interface visible to the System Console masters in the .sof file in the debug session. System Console reads this section, which Qsys Pro queries for register map information. For system slaves, Qsys Pro accesses the registers by name.
<`your_ip`>.v <`your_ip`>.vhd	HDL files that instantiate each submodule or child IP core for synthesis or simulation.
mentor/	Contains a script msim_setup.tcl to set up and run a simulation.
aldec/	Contains a Riviera*-PRO script rivierapro_setup.tcl to setup and run a simulation.
/synopsys/vcs /synopsys/vcsmx	Contains a shell script vcs_setup.sh to set up and run a VCS* simulation. Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a VCS MX* simulation.
/cadence	Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.
/submodules	Contains HDL files for the IP core submodule.
<`IP submodule`>/	For each generated IP submodule directory, Qsys Pro generates /synth and /sim sub-directories.

Upgrading IP Cores

Any IP variations that you generate from a previous version or different edition of the Quartus^® Prime software, may require upgrade before compilation in the current software edition or version.

The Project Navigator displays a banner indicating the IP upgrade status. Click Launch IP Upgrade Tool or Project > Upgrade IP Components to upgrade outdated IP cores.

IP Upgrade Alert in Project Navigator

Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required, optional, or unsupported for an IP variation in the project. Upgrade IP variations that require upgrade before compilation in the current version of the Quartus^® Prime software.

Note: Upgrading IP cores may append a unique identifier to the original IP core entity name(s), without similarly modifying the IP instance name. There is no requirement to update these entity references in any supporting Quartus^® Prime file, such as the Quartus^® Prime Settings File (.qsf), Synopsys* Design Constraints File (.sdc), or Signal Tap File (.stp), if these files contain instance names. The Quartus^® Prime software reads only the instance name and ignores the entity name in paths that specify both names. Use only instance names in assignments.

IP Core Upgrade Status
IP Core Status	Description
IP Upgraded	Indicates that your IP variation uses the latest version of the IP core.
IP Upgrade Optional	Indicates that upgrade is optional for this IP variation in the current version of the Quartus^® Prime software. Optionally, upgrade this IP variation to take advantage of the latest development of this IP core. Retain previous IP core characteristics by declining to upgrade. Refer to the Description for details about IP core version differences. If you do not upgrade the IP, the IP variation synthesis and simulation files remain unchanged, and you cannot modify parameters until upgrading.
IP Upgrade Required	Indicates that you must upgrade the IP variation before compiling in the current version of the Quartus^® Prime software. Refer to the Description for details about IP core version differences.
IP Upgrade Unsupported	Indicates that Quartus^® Prime software does not support upgrade of the IP variation due to incompatibility in the current software version. The Quartus^® Prime software prompts you to replace the unsupported IP core with equivalent IP core from the IP Catalog. Refer to the Description for details about IP core version differences and links to Release Notes.
IP End of Life	Indicates that Altera designates the IP core as end-of-life status. You may or may not be able to edit the IP core in the parameter editor. Support for this IP core discontinues in future releases of the Quartus^® Prime software.
IP Upgrade Mismatch Warning	Provides warning of non-critical IP core differences in migrating IP to another device family.

Follow these steps to upgrade IP cores:

In the latest version of the Quartus^® Prime software, open the Quartus^® Prime project containing an outdated IP core variation. The Upgrade IP Components dialog box automatically displays the status of IP cores in your project, along with instructions for upgrading each core. To access this dialog box manually, click Project > Upgrade IP Components.
To upgrade one or more IP cores that support automatic upgrade, ensure that you turn on the Auto Upgrade option for the IP core(s), and click Perform Automatic Upgrade. The Status and Version columns update when upgrade is complete. Example designs provided with any Altera FPGA IP core regenerate automatically whenever you upgrade an IP core.
To manually upgrade an individual IP core, select the IP core and click Upgrade in Editor (or simply double-click the IP core name). The parameter editor opens, allowing you to adjust parameters and regenerate the latest version of the IP core.

Figure 5. Upgrading IP Cores

Note: IP cores older than Quartus^® Prime software version 12.0 do not support upgrade. Altera verifies that the current version of the Quartus^® Prime software compiles the previous two versions of each IP core. The Altera FPGA IP Core Release Notes reports any verification exceptions for Altera IP cores. Altera does not verify compilation for IP cores older than the previous two releases.

Migrating IP Cores to a Different Device

Migrate an IP variation when you want to target a different (often newer) device. Most Altera FPGA IP cores support automatic migration. Some IP cores require manual IP regeneration for migration. A few IP cores do not support device migration, requiring you to replace them in the project. The Upgrade IP Components dialog box identifies the migration support level for each IP core in the design.

To display the IP cores that require migration, click Project > Upgrade IP Components. The Description field provides migration instructions and version differences.
To migrate one or more IP cores that support automatic upgrade, ensure that the Auto Upgrade option is turned on for the IP core(s), and click Perform Automatic Upgrade. The Status and Version columns update when upgrade is complete.
To migrate an IP core that does not support automatic upgrade, double-click the IP core name, and click OK. The parameter editor appears. If the parameter editor specifies a Currently selected device family, turn off Match project/default, and then select the new target device family.
Click Generate HDL, and confirm the Synthesis and Simulation file options. Verilog HDL is the default output file format. If you specify VHDL as the output format, select VHDL to retain the original output format.
Click Finish to complete migration of the IP core. Click OK if the software prompts you to overwrite IP core files. The Device Family column displays the new target device name when migration is complete.
To ensure correctness, review the latest parameters in the parameter editor or generated HDL.

Figure 6. IP Core Device Migration

Note: IP migration may change ports, parameters, or functionality of the IP variation. These changes may require you to modify your design or to re-parameterize your IP variant. During migration, the IP variation's HDL generates into a library that is different from the original output location of the IP core. Update any assignments that reference outdated locations. If a symbol in a supporting Block Design File schematic represents your upgraded IP core, replace the symbol with the newly generated <my_ip> .bsf. Migration of some IP cores requires installed support for the original and migration device families.

Fixed-Point IP Cores Parameters and Signals

Each IP core allows you to specify width, which is the total number of bits that make up the fixed-point number. Specifying a sign uses one of the bits.

Table 3. Performance Tab Parameters. Each IP core allows you to view resource usage in the IP Parameter Editor GUI. The parallel add, multiply, divide, integer divide and square root IP cores allow you adjust your implementation based on your chosen frequency or latency target. The parallel add, multiply, divide, and qquare root IP cores allow you to designate some of the bits to represent a fixed-point fraction.
Parameter	Description
Goal	Select Frequency, Latency, or Combined performance target
Target	Enter the frequency in MHz at which you expect this function to run. The IP core determines the amount of pipelining from this frequency and the target device family.
Check Performance	Click Check Performance to view the resource usage.

Parallel Add

This IP core calculates the sum of the inputs.

Table 4. Parallel Add Parameters
Parameter	Description
Input data widths
Input name	Autogenerated name of this input to the generated IP core.
Width	The width of this fixed-point data interface.
Fraction	The number of fraction bits in this fixed-point data interface.
Sign	The signedness of this fixed-point data interface.
+	Click + to add more inputs; click - to remove inputs.
Output data widths
Automatic output type	Always turn on automatic output type to allow the IP core to determine the output format based on the input and operation.
Width
Fraction
Sign
Options
Disable adder word growth	The addition and or subtraction logic in the IP core normally allows for word growth. To disable word growth turn on this option.
Generate an enable port	Turn on if you want the function to have an enable signal.

Table 5. Parallel Add Signals
Signal	Direction	Description
clk	Input	Clock.
reset	Input	Reset.
a0	Input	Input a0.
a1	Input	Input a1.
result	Output	The parallel add result.

Multiply

This IP core multiplies the two inputs.

Table 6. Multiply Parameters
Parameter	Description
Complex Data	You can configure a multiplier to operate on complex valued inputs and optionally use the Karatsuba method for multiplication of complex numbers. Complex valued inputs and outputs are concatenated real and imaginary values of data format you specify. The real part occupies the lower bits of the input or output bus. Complex multiplication requires four multiplications and two additions.
Karatsuba complex multiplicaiton	The Karatsuba option reduces the number of multipliers to three, increases the number of adders to five.
Input data widths
Width	The width of this fixed-point data interface
Fraction	The number of fraction bits in this fixed-point data interface
Sign	The signedness of this fixed-point data interface
Output data widths
Automatic output type	Always turn on automatic output type to allow the IP core to determine the output format based on the input and operation.
Width
Fraction
Sign
Options
Generate an enable port	Turn on if you want the function to have an enable signal.

If the IP core cannot represent the product of the inputs in the output format you chose, the result is undefined.

Table 7. Multiply Signals
Signal	Direction	Description
clk	Input	Clock.
reset	Input	Reset.
a	Input	Input a.
b	Input	Input b.
result	Output	The multiply result.

Divide

This IP core produces the result of the first input, numerator, divided by the second input, denominator. The Divide IP core has a fixed-point output. You can control the number of significant bits in the output by adjusting the output data format. If you reduce the number of bits in the output, the divider uses fewer resources.

The LSB in the divider's output is faithfully rounded. Use the Integer Divide IP core to obtain true equivalence to a truncating CPU integer divider. The faithfully rounded result has an accuracy of one unit in the last place, where one unit in the last place is the weight of the LSB. For example, if the output format has zero fraction bits, the weight of the LSB is 2^0=1. If the result is 3.2, the IP core can either return 3 or 4, where both results are equally valid.

Table 8. Divide Parameters
Parameter	Description
Input data widths
Width	The width of this fixed-point data interface
Fraction	The number of fraction bits in this fixed-point data interface. Divide IP core only.
Sign	The signedness of this fixed-point data interface
Output data widths
Automatic output type	Turn on to allow the IP core to determine the output format based on the input and operation.
Width	The width of this fixed-point data interface.
Fraction	The number of fraction bits in this fixed-point data interface. Divide IP core only.
Options
Generate an enable port	Turn on if you want the function to have an enable signal.

Table 9. Divide Signals
Signal	Direction	Description
clk	Input	Clock.
reset	Input	Reset.
numerator	Input	Numerator.
denominator	Input	Denominator.
result	Output	The division result.

Square Root

The output is faithfully rounded. The faithfully rounded result has an accuracy of one unit in the last place, where one unit in the last place is the weight of the LSB. For example, if the output format has zero fraction bits, the weight of the LSB is 2^0=1. If the result is 3.2, the IP core can either return 3 or 4, where both results are equally valid.

Table 10. Square Root Parameters
Parameter	Description
Input data widths
Width	The width of this fixed-point data interface
Fraction	The number of fraction bits in this fixed-point data interface
Sign	The signedness of this fixed-point data interface
Output data widths
Automatic output type	Turn on to allow the IP core to determine the output format based on the input and operation.
Width	The width of this fixed-point data interface.
Fraction	The number of fraction bits in this fixed-point data interface.
Sign	The signedness of this fixed-point data interface.
Options
Generate an enable port	Turn on if you want the function to have an enable signal.

Table 11. Square Root Signals
Signal	Direction	Description
clk	Input	Clock.
reset	Input	Reset.
radical	Input
result	Output	The square root result.

Integer Divide

The Integer Divide IP core offers true equivalence to a truncating CPU integer divider.

Table 12. Integer Divide Parameters
Parameter	Description
Input data widths
Width	The width of this fixed-point data interface
Sign	The signedness of this fixed-point data interface
Output data widths
Automatic output type	Turn on to allow the IP core to determine the output format based on the input and operation.
Width	The width of this fixed-point data interface.
Options
Generate an enable port	Turn on if you want the function to have an enable signal.

Table 13. Integer Divide Signals
Signal	Direction	Description
clk	Input	Clock.
reset	Input	Reset.
numerator	Input	Numerator.
denominator	Input	Denominator.
result	Output	The division result.

Simple Counter

This IP core maintains a counter and produces the counter value each cycle.The value of the counter increments by the positive step value every cycle for which the enable input is high.

The counter limit is its rollover value. The IP core sizes a counter to accommodate a value one less than the limit you specify. For example, a limit of 65,536 specifies a 16-bit counter. If the start value is 0 and the step value is 1, the counter rolls over from 65,535 to 0.

The limit must be equal to start plus an integer multiple of step.

Table 14. Simple Counter Parameters
Parameter	Description
Start value	The counter initialises to this value on reset and when incrementing a step reaches the Limit. The Start value must be greater than zero.
Step	The increment that the IP core applies on each cycle when the counter's enable input is high. The simple counter's step must be positive. Step must be greater than zero.
Limit	The counter counts up to one step away from this value. If adding the step value to the counter reaches the limit, the counter returns to Start value. Limit must be greater than or equal to Start.

Table 15. Simple Counter Signals
Signal	Direction	Description
clk	Input	Clock.
rst	Input	Reset.
en	Input	Enable.
value	Output

Loadable Counter

This IP core maintains a counter and produces the counter value each cycle.The value of the counter increments by the step value every cycle for which the enable input is high.

The limit must be equal to start plus an integer multiple of step.

Table 16. Loadable Counter Parameters
Parameter	Description
Start value	The counter initializes to this value on reset and when incrementing a step reaches the Limit.
Step	The increment that the IP core applies on each cycle when the counter's enable input is high..
Limit	The counter counts up or down to one step away from this value. If adding the step value to the counter reaches the limit, the counter returns to Start value.
Output data widths
Width	The width of this fixed-point data interface. The width of the counter and its Start, Step, and Limit inputs.
Sign	The signedness of this fixed-point data interface.

Table 17. Loadable Counter Signals
Signal	Direction	Description
clk	Input	Clock.
rst	Input	Reset.
en	Input	Enable.
sload	Input	When sload is high, the IP core replaces the counter's internal start, step, and limit values by values from the corresponding input signals.
step	Input
start	Input
limit	Input
value	Output