The Intel^® Stratix^® 10 TX Transceiver Signal Integrity Development Kit is a complete design environment that includes both hardware and software you need to develop Intel^® Stratix^® 10 TX FPGA designs.

When handling the board, it is important to observe static discharge precautions.

The Intel^® Quartus^® Prime design software is a multiplatform design environment that easily adapts to your specific needs in all phases of FPGA, CPLD, and SoC designs. The Intel^® Quartus^® Prime software delivers the highest performance and productivity for Intel FPGAs, CPLDs, and SoCs.

The new Intel^® Quartus^® Prime design software includes everything needed to design for Intel FPGAs, SoCs and CPLDs from design entry and synthesis to optimization, verification and simulation.

The Intel^® Quartus^® Prime Design Suite software is available in three editions based on specific design requirements: Pro, Standard, and Lite Edition.

The Intel^® Quartus^® Prime Pro Edition is optimized to support the advanced features in Intel's next generation FPGAs and SoCs.

The Intel^® Stratix^® 10 TX FPGA is only supported on Intel^® Quartus^® Prime Pro Edition. There is no paid license fee required for Intel^® Stratix^® 10 support in Intel^® Quartus^® Prime Pro Edition.

Included in the Intel^® Quartus^® Prime Pro Edition are the Intel^® Quartus^® Prime software, Nios^® II EDS and the MegaCore IP Library.

To install Intel^® 's development tools, download the Intel^® Quartus^® Prime Pro Edition software from the Intel Quartus Prime Pro Edition page from Intel^® 's website.

The Intel^® Stratix^® 10 TX Transceiver Signal Integrity Development Kit includes embedded Intel^® FPGA Download Cable II circuits for FPGA and MAX^® V programming. However, for the host computer and board to communicate, you must install the Intel^® FPGA Download Cable II driver on the host computer.

Installation instructions for the Intel^® FPGA Download Cable II driver for your operating system are available on the Intel website.

On the Intel website, navigate to the Cable and Adapter Drivers Information link to locate the table entry for your configuration and click the link to access the instructions.

The MAX^® V CPLD device on the board contains a parallel flash loader II (PFL II) megafunction. If AvST configuration mode is selected, after a POWER-ON or RESET (reconfiguration) event, the MAX^® V CPLD configures the Intel^® Stratix^® 10 FPGA in AvST mode with either factory design or user design depending on the setting of FACTORY_LOAD.

This development kit includes a MAX^® V CPLD design which contains the PFL II megafunction. The design resides in the <package dir>\examples\max5 directory. When configuration is complete, LED D21 (CONF_DONE) illumintes signaling that the Intel^® Stratix^® 10 TX FPGA device is configured successfully. If the configuration fails, the LED D19 (ERROR) illuminates.

The development board features the Intel^® Stratix^® 10 TX FPGA (1ST280EY2F55E1VG).

The Intel^® Stratix^® 10 TX transceiver signal integrity development kit consists of a MAX^® V CPLD (5M2210Z-F256), 256-pin FineLine BGA package. MAX^® V CPLD devices provide programmable solutions for applications such as FPGA reconfiguration from flash memory, I2C chain to manage power consumption, core temperature, fan speed, clock frequency. MAX^® V devices feature on-chip flash storage, internal oscillator and memory functionality. With up to 50% lower total power versus other CPLDs and requiring as few as one power supply, MAX^® V CPLDs can help you meet your low power design requirements.

This section describes the FPGA, flash memory and MAX V CPLD System Controller device programming methods supported by the Intel^® Stratix^® 10 TX tranceiver signal integrity development kit.

Three configuration methods are mostly used on the Intel^® Stratix^® 10 TX transceiver signal integrity development kit.

Embedded Intel^® FPGA Download Cable II is the default method for configuring the FPGA at any time using the Intel Quartus Prime Programmer in JTAG mode with the supplied USB cable.

MAX V configures the FPGA device via AvST mode using stored images from CFI flash devices either at power-up or pressing the MAX_RESETn/PGM_CONFIG push button.

JTAG external header for debugging. Intel recommends that you use lower JTAG clock frequency value such as 16 MHz.

Embedded Intel^® FPGA Download Cable II is the default method for configuring the Intel^® Stratix^® 10 TX FPGA using the Intel^® Quartus^® Prime Programmer in the JTAG mode with the supplied USB cable.

The embedded Intel^® FPGA Download Cable II for USB-based configuration of the Intel^® Stratix^® 10 TX FPGA device is implemented using a Type-B USB connector, a CY7C68013A USB2 PHY device, and an Intel^® MAX^® 10 10M04SCU169 FPGA. This will allow configuration of the Intel^® Stratix^® 10 TX FPGA device using a USB cable directly connected to a computer running Intel^® Quartus^® Prime software without requiring the external Intel^® FPGA Download Cable dongle.

This design will convert USB data to interface with the Intel^® Stratix^® 10 TX FPGA's dedicated JTAG port. Four LEDs are provided to indicate embedded Intel^® FPGA Download Cable II activity. The embedded Intel^® FPGA Download Cable II is automatically disabled when an external Intel^® FPGA Download Cable dongle is connected to the JTAG header.

The PGMSEL dipswitch (S5) is provided to select between POF files (FACTORY and USER) stored on the Flash.

The Parallel Flash Loader II (PFL II) Megafunction is used to implement the AvSTx16 configuration in the MAX^® V CPLD. The PFL II Megafunction reads data from the flash and converts it to AvST format. This data is written into the Intel^® Stratix^® 10 TX FPGA device through dedicated AvST CLK and FPGA Config Data [15:0] pins at corresponding clock rate, such as 25 MHz, 50 MHz and 100 MHz.

Implementation will be done using an MAX^® V 5M2210ZF256FBGA CPLD acting as the AvST download controller and two 1G Flash devices.

If AvST configuration mode is selected, after a POWER-ON or RESET (reconfiguration) event, the MAX^® V device shall configure the Intel^® Stratix^® 10 TX FPGA in the AvST x16 mode with either the FACTORY POF or an USER DEFINED POF depnding on the FACTORY_LOAD setting.

The MSEL[2:0] pins indicate which configuration scheme is chosen. The manufacturing default condition is [001] for Fast AS x4 scheme.

The JTAG chain allows programming of both the Intel^® Stratix^® 10 TX FPGA and MAX V CPLD devices using an external Intel^® FPGA Download Cable dongle or the on-board Intel^® FPGA Download Cable II via the USB Interface Connector. During board bring-up, and as a back-up in case the on-board Intel^® FPGA Download Cable II has a problem, the external Intel^® FPGA Download Cable can be used to program both the Intel^® Stratix^® 10 and MAX^® V CPLD via the Intel^® FPGA Download Cable 2x5 pin 0.1" programming header (J8)

Another 2x5 pin 0.1" vertical non-shrouded header (J9) is provided on the board for programming the Intel^® MAX^® 10 FPGA for configuring the on-board Intel^® FPGA Download Cable II circuitry. Once the on-board Intel^® FPGA Download Cable II is configured and operational, the on-board Intel^® FPGA Download Cable II can be used for subsequent programming of the Intel^® Stratix^® 10 TX FPGA and MAX^® V CPLD.

Pin 2 of the J8 Header is used to disable the embedded Intel^® FPGA Download Cable II by connecting it to the embedded Intel^® FPGA Download Cable II's low active disable pin with a pull-up resistor. Since Pin 2 from the mating Intel^® FPGA Download Cable dongle is GND, when the dongle is connected into the JTAG header, the embedded Intel^® FPGA Download Cable II is disabled to avoid contention with the external Intel^® FPGA Download Cable dongle.

The development board includes board-specific status LEDs and switches for enabling and configuring various features on the board. This section describes these status elements.

JTAG Chain Device Removal Switch

The JTAG chain connects the Intel^® Stratix^® 10 TX FPGA, the MAX V CPLD, FMC in a chain, with the option to selectively bypass each JTAG node by four dip switch setting.

Program Select Pushbutton

If AvST configuration mode is selected, after a POWER-ON or RESET (reconfiguration) event, the MAX^® V configures the Intel^® Stratix^® 10 TX FPGA if configuration mode is AvST mode with either the FACTORY POF or a USERDEFINED POF depending on FACTORY_LOAD setting. The setting of the PGMSEL bit is selected by the PGMSEL pushbutton. Pressing this pushbutton and observing the program LEDs (FACTORY or USER) dictates the program selection. Then, the PGM_CONFIG pushbutton must be pressed to load the program.

MAX^® V Reset Pushbutton

This pushbutton is the development board's Master Reset. This pushbuttton is connected to the MAX^® V CPLD (MAX_RESETn pin) that is used for AvST configuration. When this button is pressed, the MAX^® V CPLD initiates a reloading of the stored image from flash memory using AvST configuration mode. The image that is reloaded depends on the PGMSEL setting.

CPU Reset Pushbutton

This pushbutton is the Nios^® II CPU Reset. This button is connected to a Intel^® Stratix^® 10 TX FPGA global signal input pin and can be used by Nios^® II implementations as a dedicated CPU Reset button. This button is also connected to the MAX^® V CPLD so that the FPGA device can be reset right after its configuration with AvST mode.

User-Defined Pushbuttons

This development kit includes 4 user-defined pushbuttons and 4 system pushbuttons that allow you to interact with the Intel^® Stratix^® 10 TX FPGA. When you press and hold down the pushbutton, the device pin is set to logic 0; when you release the pushbutton, the device pin is set to logic 1. There is no board-specific function for these general user pushbuttons.

The table below lists the pushbuttons, schematic signal names and their corresponding Intel^® Stratix^® 10 TX FPGA device pin numbers.

User-Defined DIP Switch

Board reference SW4 and SW5 are two 4-pin DIP switches. The switches are user-defined and provides additional FPGA input control. When the switch is in the OPEN or OFF position, a logic 1 is selected. When the switch is in the CLOSED or ON position, a logic 0 is selected. There is no board-specific function for these switches.

The table below lists the schematic signal names of each DIP switch and their corresponding Intel^® Stratix^® 10 TX FPGA pin numbers.

User-Defined LEDs

The development board includes 8 user-defined LEDs. Board references D12 through D19 are user LEDs that allow status and debugging signals to be driven to the LEDs from the designs loaded into the Intel^® Stratix^® 10 TX FPGA device. The LEDs illuminate when a logic 0 is driven and turns off when a logic 1 is driven. There is no board-specific function for these LEDs.

The table below lists the user-defined schematic signal names and their corresponding Intel^® Stratix^® 10 TX FPGA device pin numbers.

Dedicated clocking scheme that is implemented on the Intel^® Stratix^® 10 TX transceiver signal integrity development board allows different protocols to run simultaneously by the Intel^® Stratix^® 10 TX FPGA.

The oscillator or PLL provides a differential LVDS trigger output to SMA connectors for scope or other laboratory equipment triggering purposes.

In addition to the two oscillators and PLLs, each transceiver tile have dedicated differential REFCLK input from a pair of SMA connectors to allow use of laboratory equipment clock generators as the transceiver clock source.

The figure below shows the dedicated transceiver clocks that are implemented on the Intel^® Stratix^® 10 TX FPGA development kit.

In addition to transceiver dedicated clocks, five other clock sources are provided to the FPGA Global CLK inputs for general FPGA design as shown in the figure below.

A 24 MHz crystal is dedicated for the embedded Intel^® FPGA Download Cable II circuit. The crystal is used to clock the Cypress CY7C68013A USB2 PHY device.

The Intel^® Stratix^® 10 TX transceiver signal integrity development kit dedicates 90 channels from both the left and right sides of the device. Transceiver channels are allocated as shown in the table below.

The Intel^® Stratix^® 10 TX transceiver signal integrity development kit supports a 10/100/1000 BASE-T Ethernet connection using a Marvell 88E1111 PHY device and the Intel^® Triple-Speed Ethernet Megacore MAC function. The device is an auto-negotiating Ethernet PHY with an SGMII interface to the FPGA.

The Intel^® Stratix^® 10 GX FPGA device can communicate with the LVDS interfaces at up to 1.25 Gbps. The MAC function is provided in the FPGA for typical networking applications. The Marvell 88E1111 PHY uses 2.5 V and 1.2 V power rails and requires a 25-MHz reference clock driven from a dedicated oscillator. It interfaces to an RJ-45 connector with internal magnetics that are used for driving copper lines with Ethernet traffic.

The Intel^® Stratix^® 10 TX Transceiver Signal Integrity Development Kit has two 1-Gbit CFI compatible asynchronous flash device for non-volatile storage of the FPGA configuration data, board information, test application data and user code space.

Two flash devices are implemented to achieve a 16-bit wide data bus at 16 bits each per device. Both MAX V CPLD and Intel^® Stratix^® 10 TX FPGA can access this flash device.

MAX V CPLD accesses are for AvST configuration of the FPGA at power-on and board reset events. It uses the PFL Megafunction.

The Intel^® Stratix^® 10 TX Transceiver Signal Integrity Development Kit has an Intel 1024 Mb EPCQL flash for non-volatile storage of the FPGA configuration data, board information, test application data and user code space. The quad-serial flash provided has a x4 data width, the development board has a x4 data width which can supports an AS x4 configuration scheme.

The table below shows the memory map for this flash memory. This memory provides non-volatile storage for FPGA bit stream, Nios II factory software and other information.

Intel^® Stratix^® 10 TX transceiver signal integrity development kits can be powered by either Intel provided 240 W brick or a standard ATX power supply which provides more than 240 W power. Use Intel provided 24-pin to 6-pin adapter cable to hook up ATX power supply's 24-pin ATX output with Intel^® Stratix^® 10 TX transceiver signal integrity development kit's J46 connector. Do not plug an ATX power supply 6-pin connector into J46 connector directly.

Power supply for this development kit is provided through an external laptop style DC power brick connected to a 6-pin ATX power connector. The input voltage is in the range of 12V +/- 5%. This DC voltage is then stepped down to the various power rails used by the components on the development kit.

Intel^® MAX^® 10 power logic power management solutions are provided in the Intel^® Stratix^® 10 TX Transceiver Signal Integrity Development Kit.

Intel Intel^® MAX^® 10 power management solutions are capabale of measuring the voltage, measuring the current, trimming the voltage and sequencing the order at power on and power off. Voltages can be trimmed upto +/- 10%. Communication to these devices is through I²C interface. Intel development kit's Power GUI is utilized to measure, trim and observe each voltage rail's condition.

With 25 °C ambient temperature and 50 °C printed circuit board (PCB) temperature, you must ensure that your FPGA designs do not consume more than 200 W with the liquid cooling solution.

MAX6581 chip is connected to the Intel^® Stratix^® 10 TX FPGA internal temperature diode to continuously monitor FPGA die temperature. Meanwhile, a dedicated FPGA TSD real-time monitor solution under ~\ip\onchip_sensors\ is added to each transceiver example design to monitor the temperatures of both FPGA core and each transceiver tile.

Based on the data from both MAX6581 and FPGA, MAX V will run fan at its maximum speed whenever any temperature is over 60 °C or immediately power off the board whenever any temperature is over 100 °C. Remember to unplug the power supply when the board is powered off after the temperature crosses 100 °C. Plug the power supply back again to ensure that the board can be normally turned on/off again.

The cooling parts (air duct and fan) for QSFPDD modules are pre-installed, but not powered by default. Plug them into the J60 header if your designs require additional cooling on these interfaces. You can adjust fan speed for both FPGA and optical modules through Power GUI.

Several designs are provided to test the major board features. Each design provides data for one or more tabs in the BTS. The Configure Menu identifies the appropriate design to download to the FPGA for each tab.

After successful FPGA configuration, the appropriate tab appears and allows you to exercise the related board features. Highlights appear in the board picture around the corresponding components.

The BTS shares the JTAG bus with other applications like Nios^® II debugger and the Signal Tap II Embedded Logic Analyzer. As the Intel^® Quartus^® Prime Programmer uses most of the bandwidth of the JTAG bus, other applications using the JTAG bus might time out. Be sure to close the other applications before attempting to reconfigure the FPGA using the Intel^® Quartus^® Prime Programmer.

Before you begin

The BTS relies on the Intel^® Quartus^® Prime software's specific library. Before running the BTS, open the Intel^® Quartus^® Prime software to automatically set the enviromment variable $QUARTUS_ROOTDIR. The BTS uses this environment variable to locate the Intel^® Quartus^® Prime library. The version of Intel^® Quartus^® Prime software set in the $QUARTUS_ROOTDIR environment variable should be newer than version 18.1. For example, the Development Kit Installer version 18.1 requires that the Intel^® Quartus^® Prime software 18.1 or later version to be installed.

Also, to ensure that the FPGA is configured successfully, you should install the latest Intel^® Quartus^® Prime software that can support the silicon on the development kit. For this board, Intel recommends you install Intel^® Quartus^® Prime version 19.1.0 B240.

Please refer to the README.txt file under examples\board_test_system directory.

To run the BTS

Use the Configure Menu to select the design you want to use. Each design example tests different functionality that corresponds to one or more application tabs.

Figure 14. The Configure Menu

To configure the FPGA with a test system design, perform the following steps:

The System Info tab shows information about the board's current configuration. The tab displays system-MAX V control setting, the board's MAC address, and other details stored on the board.

Figure 15. The System Info Tab

The following sections describe the controls on the System Info tab.

Board Information

System-MAX Control

The MAX V register control allows you to view and change the current MAX V register values as described in the table below. Change to the register values with the GUI take effect immediately.

JTAG Chain

The GPIO Tab allows you to interact with all the genral purpose user I/O components on your board. You can read DIP switch settings, turn LEDs on or off and detect push button presses.

Figure 16. The GPIO Tab

The following sections describe the controls on the GPIO tab.

User DIP Switches

The read-only User DIP switches control displays the current positions of the switches in the user DIP switch bank (SW4). Change the switches on the board to see the graphical display change.

User LEDs

The User LEDs control displays the current state of the user LEDs. Toggle the LED buttons to turn the board LEDs on and off.

User Push Buttons

The read-only User Push Button control displays the current status of the push buttons. Press the push button on the board to see the graphical display change.

Qsys Memory Map

Shows the memory map of the GPIO/FLASH Qsys system on yor board.

The EPCQ tab allows you to read and write flash memory on your board.

Figure 17. The EPCQ Tab

The following sections describe the controls on the EPCQ tab.

Read

Write

The Write control writes the flash memory on your board. To update the flash memory contents, change values in the table and click Write. The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents.

Erase

When erasing flash memory contents should read FFFFFFFF, which is limited to a scratch page in the upper 512K block.

Increase

Start an increase data pattern to test flash memory.

Random

Starts a random data pattern to test flash memory.

Flash Memory Map

Displays the flash memory map for the Intel^® Stratix^® 10 TX transceiver signal integrity development board.

This tab allows you to perform loopback tests on the FMC+ port, install FMC+ loopback daughter card and configure the FPGA with FMC+ image.

Figure 18. The FMC Tab

The following sections describe the controls on the FMC+ tab.

Status

Port

Allows you to specify which interface to test. The following port tests are available: XCVR and CMOS

PMA Setting

Data Type

Error Control

Run Control

TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.

Start: This toggle button control initiates and stops the tests.

Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second.

The PAM4 tab allows you to perform loopback tests on the SMAA, SMAB, QSFPDD1x1A and QSFPDD1x1B port. Install QSFPDD loopback module and cable for QSFPDD1x1 and 2.4 mm Rf connectors, configure FPGA with PAM4 image.

Figure 19. The PAM4 Tab

The following sections describe the controls on the PAM4 tab.

Status

Figure 20. SMA Status

Figure 21. QSFPDD1X1 Status

Port

Allows you to specify which interface to test. The following port tests are available: SMAx2, OSFPx8 and QSFPDDx8.

PMA Setting

Figure 22. SMA PMA Setting

Figure 23. QSFPDD1X1 PMA Setting

Data Type

Error Control

Run Control

TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.

Start: This toggle button initiates and stops the tests.

Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second.

The MXP tab allows you to perform loopback tests on the MXP port. Install MXP loopback modules for four MXP interfaces, configure FPGA with MXP image.

Figure 24. The MXP Tab

The following sections describe the controls on the MXP tab.

Status

Port

PMA Setting

Data Type

Error Control

Run Control

TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.

Start: This toggle button initiates and stops the tests.

Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second.

The QSFPDD1x2 tab allows you to perform loopback tests on the QSFPDD1x2 port. Install two QSFPDD loopback modules into QSFPDD1x2 interface, configure the FPGA with QSFPDD1x2 image.

Figure 25. The QSFPDD1x2 Tab

The following sections describe the controls on the QSFPDD1x2 tab.

Status

Figure 26. QSFPDD1X2 Status

Port

Allows you to specify which interface to test. The following port tests are available: QSFPDD1x2

PMA Setting

Figure 27. QSFPDD1X2 PMA Setting

Data Type

Error Control

Run Control

TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.

Start: This toggle button initiates and stops the tests.

Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second.

The QSFPDD2x1 Tab allows you to run transceivers QSFPDD2x1 loopback tests on your board. Install two QSFPDD loopback modules into QSFPDD2x1 interface, configure the FPGA with QSFPDD2x1 image.

Figure 28. The QSFPDD2x1 Tab

The following sections describe the controls on the QSFPDD2x1 tab.

Status

Figure 29. QSFPDD2X1 Status

Port

PMA Setting

Figure 30. QSFPDD2X1 PMA Setting

Data Type

Error Control

Run Control

TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.

Start: This toggle button initiates and stops the tests.

Tx (Mbps) and Rx (Mbps): Show the number of bytes of data analyzed per second.

The Power Monitor measures and reports current power information and communicates with the MAX V device on the board through the JTAG bus. A power monitor cicruit attached to the device allows you to measure the power that the FPGA is consuming and trim voltage level.

To start the application, click the Power Monitor icon in the BTS. You can also run the Power Monitor as a stand-alone application. The PowerMonitor.exe resides in the <package dir>\examples\board_test_system directory.

Figure 31. The Power Monitor

The Clock Controller application sets the Si549 programmable oscillators to any frequency between 0.2 MHz and 800 MHz and sets the Si5341 PLL to any frequencies between 10 MHz and 750 MHz. The oscillator drives a 2-to-6 buffer that drives a copy of the clock to all transceiver blocks of the FPGA.

To start the application, click Clock Controller icon in the BTS. You can also run the Clock Controller as a stand-alone application.

The ClockController.exe resides in the <package dir>\examples\board_test_system directory.

The Clock Control communicates with the MAX V device on the board through the JTAG bus. The Si549 programmable oscillator and PLL are connected to the MAX V device through a 2-wire bus.

Figure 32. The Clock Controller - Si549

Figure 33. The Clock Controller - Si5341

The following sections describe the Clock Control controls.

Divider

F_vco

Target Frequency

The Target Frequency control allows you to specify the frequency of the clock. Legal values are between 0.2 MHz and 800 MHz and select frequencies to 1400 MHz. For example, 421.31259873 is possible within 100 parts per million (ppm). The Target Frequency control works in conjunction with the Set Control.

Set

The Set control sets programmable oscillator or PLL frequency to the value in the Target frequency control. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time.

Default

Sets the frequency for the oscillator associated with the active tab back to its default value. This can also be accomplished by power cycling the board.

The Intel^® Stratix^® 10 TX Transceiver Signal Integrity Development Kit ships with the Simple Socket Server design example stored in the factory portion of the EPCQL flash memory. The design consists of a Nios^® II embedded processor and an Ethernet MAC.

When you power up the board, the Intel^® Stratix^® 10 TX FPGA configures with the Simple Socket Server design example. The design can obtain an IP address from any DHCP server and serve a telnet server to any host computer on the same network. The telnet server allows you to control the LEDs on the board.

The source code for the Simple Socket Server design resides in the <package dir>\examples\simple_socket_server directory. If the Simple Socket Server is corrupted or deleted from the flash memory, you might need to restore the board's original contents, using the BTS application.

Intel^® Stratix^® 10 FPGA silicon assembled on the Intel^® Stratix^® 10 TX Transceiver Signal Integrity Development Kit enables SmartVID feature by default.

You may encounter the following error message when you switch from using the example design to your own design:

Error(19192): File <filename>.sof is incomplete - Power management settings are not set up appropriately on VID part"

To prevent Intel^® Quartus^® Prime from generating an error message due to incomplete SmartVID settings, you must put constraints listed below into the Intel^® Quartus^® Prime project QSF file.

Open your Intel^® Quartus^® Prime project QSF file, copy and paste the constraints listed below in the QSF file.

Before, you compile your project with correct SmartVID settings, ensure that there are no other similar settings with different values.

Constraints

set_global_assignment -name PWRMGT_BUS_SPEED_MODE "400 KHZ"

set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 47

set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 48

set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00

set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00

set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE ON

set_global_assignment -name USE_PWRMGT_SCL SDM_IO14

set_global_assignment -name USE_PWRMGT_SDA SDM_IO11

set_global_assignment -name USE_PWRMGT_ALERT SDM_IO12

set_global_assignment -name USE_CONF_DONE SDM_IO16

set_global_assignment -name USE_INIT_DONE SDM_IO0

set_global_assignment -name USE_CVP_CONFDONE SDM_IO15

set_global_assignment -name USE_SEU_ERROR SDM_IO13

The Intel^® Stratix^® 10 device family offers SmartVID standard power devices in all speed grades. Lower power fixed-voltage devices are also available in all speed grades except for the fastest speed grade. Please refer to Intel Stratix 10 Power Management User Guide for additional information.

ENGINEERING DEVELOPMENT PRODUCT - NOT FOR RESALE OR LEASE

This development kit is intended for laboratory development and engineering use only.

This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required Federal Communications Commission (FCC) equipment authorizations are first obtained.

Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.

Unless the assembled kit is designed to operate under Part 15, Part 18 or Part 95 of the United States Code of Federal Regulations (CFR) Title 47, the operator of the kit must operate under the authority of an FCC licenseholder or must secure an experimental authorization under Part 5 of the United States CFR Title 47.

Safety Assessment and CE mark requirements have been completed, however, other certifications that may be required for installation and operation in your region have not been obtained.

Power Supply Hazardous Voltage

AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply.

Power Connect and Disconnect

The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system. The socket outlet must be installed near the equipment and must be readily accessible.

System Grounding (Earthing)

To avoid shock, you must ensure that the power cord is connected to a properly wired and grounded receptacle. Ensure that any equipment to which this product will be attached is also connected to properly wired and grounded receptacles.

Power Cord Requirements

The connector that plugs into the wall outlet must be a grounding-type male plug designed for use in your region. It must have marks showing certification by an agency in your region. The connector that plugs into the AC receptacle on the power supply must be an IEC 320, sheet C13, female connector. If the power cord supplied with the system does not meet requirements for use in your region, discard the cord and do not use it with adapters.

Lightning/Electrical Storm

Do not connect/disconnect any cables or perform installation/maintenance of this product during an electrical storm.

Risk of Fire

To reduce the risk of fire, keep all flammable materials a safe distance away from the boards and power supply. You must configure the development kit on a flame retardant surface.

Thermal and Mechanical Injury

Certain components such as heat sinks, power regulators, and processors may be hot. Heatsink fans are not guarded. Power supply fan may be accessible through guard. Care should be taken to avoid contact with these components.

Cooling Requirements

Maintain a minimum clearance area of 5 centimeters (2 inches) around the isde, front and back of the board for cooling purposes. Do not block power supply ventilation holes and fan.

Electro-Magnetic Interference (EMI)

This equipment has not been tested for compliance with emission limits of FCC and similar international regulations. Use of this equipment in a residential location is prohibited. This equipment generates, uses and can radiate radio frequency energy which may result in harmful interference to radio communications. If this equipment does cause harmful interfence to radio or television reception, which can be determined by turning the equipment on and off, the user is required to take measures to eliminate this interference.

Telecommunications Port Restrictions

The wireline telecommunications ports (modem, xDSL, T1/E1) on this product must not be connected to the Public Switched Telecommunication Network (PSTN) as it might result in disruption of the network. No formal telecommunication certification to FCC, R&TTE Directive, or other national requirements have been obatined.

Electrostatic Discharge (ESD) Warning

A properly grounded ESD wrist strap must be worn during operation/installation of the boards, connection of cables, or during installation or removal of daughter cards. Failure to use wrist straps can damage components within the system.

Ecology Conformance Marking for WEEE and China RoHS

CE EMI Conformity Caution

This development board is delivered conforming to relevant standards mandated by Directive 2014/30/EU. Because of the nature of programmable logic devices, it is possible for the user to modify the development kit in such a way as to generate electromagnetic interference (EMI) that exceeds the limits established for this equipment. Any EMI caused as a result of modifications to the delivered material is the responsibility of the user of this development kit.