Forward error correction is a powerful method of correcting errors that can occur on a serial link. Although very useful, it can be costly in both area and power when implemented in soft logic. For this reason, E-Tile and H-Tile devices provide hardened FEC blocks to address many important applications, such as:

• 10 Gigabit Ethernet (GbE) (H-Tile)
• 25GbE (E-Tile)
• 100GbE (E-Tile)
• 24.3 Gbps Common Public Radio Interface (CPRI) (E-Tile)
• 128 gigabit fibre channel (GFC) (E-Tile)

Transmitting data introduces many challenges. Among these challenges is the noise in a communication channel, which can result in errors in the transmission of bits. There are many types of noise.

• Hamming code
• Low density parity check codes (LDPC)
• Convolutional codes
• Viterbi
• Various FEC codes

In binary codes, the encoder and decoder operate on a bit basis. The 10GBASE-KR Fire Code FEC is an example of a binary code. In non-binary codes, the encoder and decoder operate on a byte or symbol basis. Symbols may be any number of bits. Galois finite field arithmetic is used and the Reed Solomon code is an example of a non-binary code.

Cyclic block codes are defined by a generator polynomial g(x). Encoding consists of adding a set of parity bits or symbols onto the data to create a code word, also called a codeword or a block. The parity is the remainder of the block from the polynomial division of the data bits by g(x). This is easily implemented using a linear feedback shift register (LFSR). Error detection and correction calculates the syndrome of the received code word. The syndrome is the difference between the locally-generated and received parity. If the syndrome is zero, the code word is correct. If the syndrome is non-zero, then the syndrome can determine the most likely error.

The receiver analyzes the check bit information to locate and correct errors. This correction allows systems to operate at higher bit error rates (BER).

While FEC provides a performance increase, it also introduces increased power consumption, increased latency, and an increased number of gates.

The extra data added to the real data protects the real data from getting corrupted.

• Reed Solomon
• Bose-Chadhuri-Hocquenghem (BCH)
• Concatenated codes

The type you select depends on:

• The overhead your design permits
• Burst handling capability
• Gain versus complexity (number of gates, memory, power, and so on)
• Latency considerations

There are bit error and burst limits to each code. FEC complexity increases non-linearly as you approach the Shannon limit. The Shannon limit, sometimes called Shannon's theorem, establishes that for any given degree of noise contamination of a communication channel, it is possible to communicate discrete data (digital information) nearly error-free up to a computable maximum rate through the channel.

FEC allows detection and correction of X bits or symbols in a block. There are limits to its correcting capability.

This section also includes an Ethernet benchmarking example to help you select the best FEC mode for the 100GbE application in this application note.

The primary considerations when choosing a FEC include:

• Hardware complexity
• Coding gain
• Latency
• Power

The code encodes 2080 bits of payload (or information symbols) and adds 32 bits of overhead (or parity symbols). The code is systematic—meaning that the information symbols are not disturbed in the encoder, and the parity symbols are added separately to the end of each block.

The (2112,2080) code is constructed by shortening the cyclic code (42987, 42955). The shortened cyclic code (2112,2080) is guaranteed to correct an error burst of up to 11 bits per block. It is a systematic code that is well suited for correction of the burst errors typical in a backplane channel resulting from error propagation in the receive equalizer.

At the end of each block there is 32-bit overhead or parity check bits. Transmission is from left to right within each row, and from top to bottom between rows. The payload bits carry the information symbols from the PCS layer.

Total FEC block length = (32 × 65) + 32 = 2112 bits.

Instead, the FEC sublayer compresses the sync bits from the 64B/66B encoded data provided by the PCS to accommodate the addition of 32 parity check bits for every block of 2080 bits.

The BASE-R 64B/66B PCS maps 64 bits of scrambled payload and 2 bits of unscrambled synchronization header into 66-bit encoded blocks. The 2-bit synchronization header allows the PCS synchronization process to establish the 64B/66B block boundaries. The synchronization header is 01 for data blocks and 10 for control blocks. The synchronization header is the only position in the PCS block that always contains a transition, and this feature of the code establishes the 64B/66B block boundaries.

The FEC sublayer compresses the 2 bits of the synchronization header to one transcode bit. The transcode bit carries the state of BASE-R synchronization bits for the associated payload. This is achieved by eliminating the first bit in 64B/66B block, which is also the first synchronization bit, and preserving the second bit. The value of the second bit defines the value of the removed first bit uniquely, because it is always an inversion of the first bit. The transcode bits are further scrambled (as explained in IEEE 802.3ap Clause 74.7.4.2) to ensure DC balance.

The 32 sequential 64B/66B blocks are transcoded in this fashion, and then 32 bits of FEC parity are computed for them. The 32 transcoded words and the 32 FEC parity bits comprise a FEC block. The error detection property of the FEC cyclic code establishes block synchronization at FEC block boundaries at the receiver. If decoding passes successfully, the FEC decoder produces 32 65-bit words, the first decoded bit of each word being the transcode bit. Then, the inversion of the transcode bit constructs the first synchronization bit in the 64B/66B code, and the value of the second synchronization bit is equal to the transcode bit.

The KR FEC blocks in the Enhanced PCS are designed in accordance with the 10GBASE-KR FEC and 40GBASE-KR FEC specification of the IEEE 802.3 specification. The KR FEC implements the FEC as a sublayer between the PCS and PMA sublayers.

The FEC sublayer is optional and you can bypass it. When used, it provides additional margin to allow for variations in manufacturing and environmental conditions. FEC can achieve the following objectives:

• Support a forward error correction mechanism for the 10GBASE-R/KR and 40GBASE-R/KR protocols
• Support full duplex mode of the Ethernet MAC
• Support the PCS, PMA, and Physical Medium Dependent (PMD) sublayers defined for the 10GBASE-R/KR and 40GBASE-R/KR protocols

KR FEC improves the BER performance of the system.

The transcode bit is generated from a combination of 66 bits after the 64B/66B encoder which consists of a 2-bit synchronization header (S0 and S1) and a 64-bit payload (D0, D1,…, D63). To ensure a DC-balanced pattern, the transcode word is generated by performing an XOR function on the second synchronization bit S1 and payload bit D8. The transcode bit becomes the LSB of the 65-bit pattern output of the transcode encoder.

The code is a shortened cyclic code (2112, 2080). For each block of 2080 message bits, the encoder generates another 32 parity checks to form a total of 2112 bits. The generator polynomial is:

g(x) = x³² + x²³ + x²¹ + x¹¹ + x² +1

The KR FEC TX gearbox aligns with the FEC block. Because the encoder output (also the scrambler output) has its unique word size pattern, the gearbox is specially designed to handle that pattern.

If 1 bit or all the m bits of a symbol are corrupt, this accounts for one symbol error. Symbols correlate well into burst errors.

RS-FEC can correct any seven single bit errors.

RS (528, 514) can correct up to seven symbols. If all bits are error bits, for all seven symbols, then the total number of correctable bits is 70.

If 1 bit or all the M bits of a symbol are corrupt, this accounts for one symbol error. Symbols correlate well into burst errors.

RS-FEC can correct any 15 single bit errors.

RS (544, 514) can correct up to 15 symbols. If all bits are error bits, for all 15 symbols, then the total number of correctable bits is 150.

Legend:

• RS528 = RS(528, 514)
• RS544 = RS(544, 514)
• AM = Alignment Markers
• CWM = Codeword Marker
• SnT = Scramble-and-Test

The RS-FEC core supports the following standards:

• 100GbE: IEEE 802.3 Clause 91
• 100GbE with KP-FEC: IEEE 802.3 Clause 91
• 128GFC: Fibre Channel Framing and Signaling - 4 (FC-FCS-4) Clause 5.6
• 25GbE: IEEE 802.3 Clause 108
• 32GFC: Fibre Channel Framing and Signaling - 4 (FC-FCS-4) Clause 5.4

100GbE with KP-FEC uses two physical PAM4 coded lanes, also called, 100 Gigabit Attachment Unit Interface (CAUI-2). It uses the RS(544,514). The two physical lanes are supported by bit-multiplexing the RS-FEC Core’s four PMA lanes pairwise outside of the RS-FEC Core. The remaining defined clients use the RS(528,514) FEC.

In the CPRI standard, the CPRI FEC refers to 32GFC. CPRI is like 32GFC except for the line rate, which is 24 Gbps.

100GBASE-KR4 is a non-binary code (528, 514, 7, 10). 100GBASE-KR4 features:

• 514 data symbols per codeword
• 528 data plus parity symbols per codeword
• Codeword size = 10 * 528 = 5280 bits
• Correcting capability up to seven symbols within a codeword
• 5 to 5.5 dB gain
• NRZ modulation
• 25.78125 Gbps bit rate
• BER of 10^-12 or better (after FEC correction)

100GBASE-KP4 is a non-binary code (544, 514, 15, 10). 100GBASE-KP4 features:

• 514 data symbols per codeword
• 544 data plus parity symbols per codeword
• Codeword size = 10 * 544 = 5440 bits
• Correcting capability up to 15 symbols within a codeword
• 6 to 6.5 dB gain
• PAM4 modulation
• 26.5625 Gbps bit rate
• BER of 10^-12 or better (after FEC correction)

RS(544, 514) requires additional room to accommodate 5440 bits instead of 5280 bits. After transcoding, it must additionally make room for approximately 3% more bits of overhead. The precise overhead is calculated as 1/33; new rate = old rate * 34/33. This result is overspeed for PAM4. For example:

• Payload data rate = 50 Gbps
• Encoding it to 66b encoding: 50*66/64 = 51.5625 Gbps
• Adding FEC expansion: 51.5625*(34/33) = 53.125 Gbps

Intel^® Stratix^® 10TX devices do not support the 100GBASE-KP4 physical medium dependent (PMD).

The IEEE802.3ap specification defines an insertion loss and return loss of 25 dB at 5.15625 GHz. The 1e^-12 BER requirement is a system specification that is met with or without FEC.

The IEEE802.3bj specification specifies 100GBASE-KR4 for 100 Gbps operation using NRZ over four differential pairs where the insertion loss does not exceed 35 dB at 12.9 GHz. 100GBASE-KR4 uses:

• The PCS defined in Clause 82
• The RS-FEC defined in Clause 91
• The PMA defined in Clause 83
• The PMD defined in Clause 93

IEEE802.3bj also specifies 100GBASE-KP4 for 100 Gbps operation using PAM4 over two differential pairs where the insertion loss does not exceed 33 dB at 7 GHz. 100GBASE-KP4 uses:

• The PCS defined in Clause 82
• The RS-FEC defined in Clause 91
• The PMA and PMD defined in Clause 94

The CEI 56G long reach (LR) specification discusses multiple FECs, but the standard is KP4 FEC with PAM4. The 1e^-15 BER requirement is a system specification met with FEC.

It then uses the synchronization headers to obtain lock to the 66-bit blocks in each bit stream and outputs 66-bit blocks.

Alignment marker lock identifies the PCS lane number received on a particular lane of the service interface. After alignment marker lock is achieved on all 20 lanes, all inter-lane skew is removed. The RS-FEC transmit function supports a maximum skew of 49 ns between PCS lanes, and a maximum skew variation of 400 ps.

The RS-FEC transmit function orders the PCS lanes according to the PCS lane number.

If all four incoming blocks are data blocks:

1. Remove the 2-bit headers of all four 66-bit data blocks.
2. Append a header bit of 1 to the four 64-bit data payloads.

If there is at least one control block among the four-incoming blocks:

1. Remove the 2-bit headers of all four incoming 66-bit blocks
2. Append a header bit of 0 to the four payloads of the four blocks.

   RS-FEC deletes the second 4-bit nibble in the block type field (BTF) of the first control block in a transcoded block. RS-FEC retains the first 4-bit nibble in the BTF of the first control block (indicating the type).

3. Add the 4-bit header x1, x2, x3, or x4 following the overall header bit 0, where:
   • x1 = Data block
   • x2, x3, and x4 = Control block

The E-Tile Channel Placement Tool allows you to swiftly plan protocol placements in the product prior to reading comprehensive documentation and implementing designs in the Intel^® Quartus^® Prime software.

The Excel-based E-Tile Channel Placement Tool, supplemented with Instruction, Legend, Revision and Protocols tabs, is self-sustaining, and available for download.

Consider a typical datacenter topology.

The interconnection between the spine switches and the lead switches is a 10G/40G/100G backplane.

25GbE is a proposed standard for Ethernet connectivity in a datacenter application space, and takes advantage of the technology defined for 100GbE as four 25 Gbps lanes running on four fibers or copper pairs.

FEC performance in the Intel^® Stratix^® 10 device was measured using a 25GbE design running RS (528, 514) FEC.

The test configuration included:

• An Intel^® Stratix^® 10 TX signal integrity development kit board using the E-Tile device
• FCI backplane (Megtron 6 material)
• Variable ISI box

The FCI backplane is connected to the E-Tile device on one lane, starting with 28 dB loss (error free even without FEC). Attenuation is increased on only one channel using the variable ISI box. This provides fine control over the insertion loss.

Note the following:

• Post FEC BER is an estimate from uncorrectable code words.
• Received bits at the PRBS are normalized to account for PRBS payload + MAC padding (preamble, start codeword delimiter, and so on).
• Total IL = SI development kit loss + backplane loss + cable loss + variable ISI box loss.
• Total IL is a first order loss calculated by summing all the individual losses.

These hardware results demonstrate that the Intel FEC solution complies with the specification, making it a compelling solution for your Ethernet, CPRI, or Fibre Channel designs.

For more information about forward error correction, refer to the following resources:

• J. Schrum, YouTube video : "Error Detection and Correction 3: Forward Error Correction," 2016. [Online].
• A. Davis, EE Times : "Design How-To Forward Error Correction," 1998. [Online].
• N. R. Wagner, "The Laws of Cryptography: The Hamming Code for Error Correction," [Online].
• Optical Transport Network (OTN) Tutorial. ITU. [Online].