This design example demonstrates how to use a supported Altera device as an I²C battery gauge interface. The end product is a low-cost intelligent device that improves communication between the battery gauge and the host system.

A battery gauge is a device which continuously monitors the state of a battery's capacity and displays it to the user in a simple form. Often in embedded systems, the status of the battery supply is monitored remotely. Communication between the embedded system and battery gauge can be facilitated through an industry standard two-wire I²C bus and an interfacing device. Because of its low overhead, the two-wire communication link minimizes the number of traces required on the PCB to monitor the power source.

A supported Altera device can easily serve as the interfacing device. The I²C interface allows the supported Altera device to access readings from the battery gauge remotely. An I²C serial interface consists of a data line (SDA) and a clock line (SCL). Both the lines are bidirectional and are pulled up to the V_CC of the system. This bus is also a common bus for any other I²C-compliant device in the system.

In this implementation, the battery gauge acts as slave to the supported Altera device and has a software programmable address. At any time, the supported Altera device acting as the master can read the exact state of battery charge through the battery gauge interface. The design uses an inexpensive battery gauge device, such as the Maxim DS2745.

Because the design is made for illustration, it does not implement a complete I²C master. This design, therefore, does not accommodate multimaster capability and is only meant to demonstrate the capability of the supported Altera device to read the DS2745 battery gauge via an I²C interface.

In order to retrieve the status of the battery from the gauge, the master initiates the communication cycle by sending a Start condition on the bus. The Start condition, which consists of pulling the SDA line low while SCL is high, is followed by a 7-bit slave address and a write command (90h). After receiving these signals, the slave sends back an acknowledgment to the master.

After receiving the acknowledgment (battery gauge DS2745), the master sends the memory address (0Ch), which corresponds to the voltage register on the slave. The DS2745 acknowledges this memory address, and then the master generates a Repeat Start (Sr). After the Repeat Start, the supported Altera device (master) sends the device address again, followed by a read, this time (91h). The DS2745 acknowledges it as the same. The battery data is transferred on the SDA line to the master in the next two 8-bit read operations; the MSB is sent first followed by the LSBs. The master sends an acknowledgment after every 8 bits that are received. A Stop (P) condition is generated by the master by leaving the SDA line high when SCL is high after the read is complete. The slave returns Data in two's complement form, which is converted to a bar form for display.

The detailed description of the implementation is based on the MAX II devices. This application can also be implemented in MAX V and MAX 10 devices.

This design example can be implemented with an EPM240 device or any other MAX II device and a I²C battery gauge device such as the Maxim DS2745. This design communicates with the Maxim DS2745 battery gauge through the I²C bus and displays the constantly updated voltage readings without requiring any external stimulus.

The voltage status returned by the DS2745 battery gauge is 11-bit wide and is in 2's complement form. The voltage readings are converted into a viewer-friendly form with eight voltage magnitude levels by the MAX II device. These are subsequently displayed with the help of an LED array with eight LEDs.

The following details the implementation of this design example on the MDN-B2 demo board.

Assign unused pins as input tri-stated in the Quartus^® II software. You must also enable the Auto Open Drain setting on the SCLK and SDA pins. To do this, on the Assignments menu, click Settings and then select Analysis and Synthesis Settings to enable the Auto Open-Drain setting. These settings are followed by a compilation cycle.

This design example has been implemented in Verilog and successful operation has been demonstrated using the MDN-B2 demo board, as described in this document.

Design example adapted for Altera MAX 10 FPGAs by:

Orchid Technologies Engineering and Consulting, Inc.

Maynard, Massachusetts 01754

TEL: 978-461-2000

WEB: www.orchid-tech.com

EMAIL: info@orchid-tech.com