L/H-tile Hard IP for PCI Express IP Core Release Notes
RN-1143 | 2020.12.14
Version Information
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 20.4 |
1. L/H-tile Hard IP for PCI Express IP Core Release Notes
1.1. L/H-tile Hard IP for PCI Express IP Core v20.4
IP versions are the same as the Intel Quartus Prime Design Suite software versions up to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IPs have a new IP versioning scheme.
The IP version (X.Y.Z) number may change from one
Intel®
Quartus® Prime software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
| Intel® Quartus® Prime Version | Description | Impact |
|---|---|---|
| 20.4 | Migrating a design using an L/H-tile Avalon® Streaming, Avalon® Memory-mapped or Avalon® Memory-mapped+ IP from an earlier Intel® Quartus® Prime version to the 20.4 version requires an IP upgrade. | You must regenerate any design using an L/H-tile Avalon® Streaming, Avalon® Memory-mapped or Avalon® Memory-mapped+ IP when moving from an earlier Intel® Quartus® Prime version to the 20.4 version. |
| The names of the L/H-tile IPs for PCI Express have been changed to meet new legal guidelines. | The abbreviations " Avalon® -ST" and " Avalon® -MM" in the names of the L/H-tile IPs for PCI Express have been replaced with " Avalon® Streaming" and " Avalon® Memory-mapped", respectively. | |
| The parameters to enable the Multi-function and Function-Level Reset (FLR) features have been removed from the IP Parameter Editor of the L/H-tile Avalon® Memory-mapped+ IP. | Multi-function and FLR support are not available in this Intel® Quartus® Prime release for the L/H-tile Avalon® Memory-mapped+ IP. |
1.2. L/H-tile Hard IP for PCI Express IP Core v19.3
| Description | Impact |
|---|---|
| Added a note clarifying that the Autonomous Hard IP mode is enabled by default for all Intel® Stratix® 10 IPs for PCI Express* . | This mode enables the PCIe IPs to communicate with the Host before the FPGA configuration and entry into User mode are complete. This mode cannot be disabled in Intel® Stratix® 10 devices. |
| Added a note clarifying that the Control Shadow Interface of the Intel® Stratix® 10 Avalon® -ST IP for PCI Express* is only used to access Virtual Function (VF) registers and not Physical Function (PF) registers. | The Control Shadow Interface provides access to the current settings for some of the VF Control Register fields in the PCI and PCI Express Configuration Spaces located in the SR-IOV Bridge. This interface is only available for H-Tile devices. |
| Removed the signal xcvr_reconfig_readdatavalid from the list of Hard IP Reconfiguration signals of the Intel® Stratix® 10 Avalon® -ST IP for PCI Express* . | Since the xcvr_reconfig_readdata[31:0] bus will be valid on the third cycle after the assertion of xcvr_reconfig_read, the xcvr_reconfig_readdatavalid signal is not needed. |
| Added a description of the behavior of the Intel® Stratix® 10 Avalon® -ST IP for PCI Express* when memory read accesses are made to a disabled Expansion ROM BAR. | If an Expansion ROM BAR is disabled, memory read accesses to that BAR are responded to with 32'h0000_0000 indicating that the BAR does not exist. |
| Raised the device support level for the Intel® Stratix® 10 Avalon® -MM Hard IP+ from Advance to Preliminary. | Preliminary support level indicates that the IP core has been verified with preliminary timing models and also meets all functional requirements. |
1.3. L/H-tile Hard IP for PCI Express IP Core v19.1
| Description | Impact |
|---|---|
| Added a chapter on the programming model for Root Ports to the Intel® Stratix® 10 Avalon® -MM Interface for PCI Express* Solutions User Guide. | Added the programming model for Root Ports to help users enable
Root Ports. The model:
|
| Removed the note stating that Root Port mode is not recommended from the Intel® Stratix® 10 Avalon® -MM and Intel® Stratix® 10 Avalon® -ST for PCI Express* Solutions User Guides. | Root Port mode is fully supported in this release for both Avalon® -MM and Avalon® -ST IPs. |
| Removed the BIOS Enumeration Issue section from the Troubleshooting chapter of all Intel® Stratix® 10 PCI Express* User Guides. | Since Intel® Stratix® 10 devices support the autonomous Hard IP feature, they can be recognized by the OS/BIOS during enumeration without having to be fully programmed. |
| Added the note stating that the bam_response_i[1:0] inputs should be driven to 0 to the Intel® Stratix® 10 Avalon® -MM Hard IP+ for PCI Express* User Guide. | Clarified that these inputs are reserved; hence, they should be driven to 0. |
1.4. L/H-tile Hard IP for PCI Express IP Core v18.1.1
| Description | Impact |
|---|---|
| Added the Link Inspector Avalon-MM Interface to the Avalon® -ST, Avalon® -MM and Avalon® -MM Hard IP+ for PCI Express* IPs. | This interface allows you to access low-level link status information from the PCIe Hard IP, XCVR or PLL blocks via the Link Inspector without using the System Console. |
| Added the completion timeout checking feature to the Avalon® -MM Hard IP+ for PCI Express* IP. | This new option in the GUI (under the Avalon® -MM Settings tab) allows you to receive a completion timeout error indicator on either the rddm_tx_data_o[15] port (if the Read Data Mover issued a Read operation to the host) or the bas_response_o[1:0] ports (if the Bursting Avalon® Slave forwarded a Read operation to the host). |
| Added the feature to trigger MSI interrupts via the rxm_irq_i ports to the Avalon® -MM for PCI Express* IP. | This feature allows the IP core to convert a rising edge on one of the
rxm_irq_i ports to an MSI interrupt and send it to the Root Port.
Note: the rxm_irq_i ports are not available when the IP core is
operating in DMA mode.
|
1.5. L/H-tile Hard IP for PCI Express IP Core v18.0
| Description | Impact |
|---|---|
| Initial release of the Avalon-MM Intel Stratix 10 Hard IP+ for PCI Express. | Added a new IP component to enable Avalon® -MM support for Gen3 x16 mode. This IP core supports up to four functions. The support level is Advance. |
| Added support for 64-bit Avalon-MM application interface width. | In addition to the native 256-bit interface available, support for a 64-bit Avalon® -MM interface (without DMA) is added. |
| VHDL compilation and simulation are not supported in the 18.0 release. | You can only simulate and compile in Verilog in the 18.0 release. |
|
Single Root I/O Virtualization (SR-IOV) support for H-Tile variants. |
Dynamic example design generation, compilation, simulation, and hardware support for SR-IOV have been added for Avalon® -ST mode only. |
| First-level Signal Tap file. | Support to generate a Signal Tap file through a pre-compiled script has been enabled. |
| Software application for the Avalon® -MM IP (with or without DMA). | Linux kernel driver, API, and an example command-line application using the API are available to enable testing of the Avalon® -MM example designs (with or without DMA). The example application can also give rough estimates on the performance of the example design within the system. This application supports all link widths and speeds. |
| Intel® Stratix® 10 timing failures in example designs (Gen3 x16 Avalon® -ST and Gen3 x16 Avalon® -ST with SR-IOV). | Small
hold violations (i.e: < 5 ps slack). Setup violations can be observed on ES devices. |
1.6. L/H-tile Hard IP for PCI Express IP Core v17.1
| Description | Impact | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Initial release. | N/A | ||||||||||||
| VHDL compilation and simulation are not supported in the current release. | You can only simulate in Verilog in the current release. | ||||||||||||
|
The automatically generated simple DMA design example has timing issues. This timing problem does not affect DMA designs that use the internal descriptor controller or DMA designs that use an external DMA controller to drive the internal Read and Write Data Movers. These designs close timing and function correctly in hardware. |
You can simulate the simple DMA design and successfully and generate an SRAM Object file (*.sof). However, if you download the *.sof to hardware, the hardware will fail. | ||||||||||||
|
Single Root I/O Virtualization (SR-IOV) support for H-Tile variants is preliminary in the 17.1 release. |
You can enable SR-IOV using the parameter editor. SR-IOV supports basic simulation and compilation. However, SR-IOV is not fully verified. You may find functional problems in the current release. | ||||||||||||
| The Root Port is preliminary in the 17.1 release. | You can enable the Root Port using the parameter editor. The Root Port supports basic simulation and compilation. However, the Root Port is not fully verified. You may find functional problems in the current release. | ||||||||||||
| The Avalon® Memory-Mapped ( Avalon® -MM) DMA functionality is preliminary in the 17.1 release. | You can use the Avalon® -MM DMA functionality in the current release. Avalon® -MM supports simulation and compilation. However, this functionality has not been fully verified. You may find functional problems. | ||||||||||||
| Upon reboot, the Intel® Stratix® 10 Hard IP for PCI Express* IP Core might be unable to exit BIOS enumeration. | This problem affects L-Tile ES1 and ES2 and H-Tile ES1 devices. It will be fixed in a future release. | ||||||||||||
|
The link acknowledge logic in the Intel® Stratix® 10 H-Tile ES2 devices has a encoding error. This encoding error results in the following incorrect link widths:
|
This problem will be fixed in a future release. |
Related Information