The H-Tile Hard IP for Ethernet Intel^® FPGA IP core provides a simulation testbench and a hardware design example that supports compilation and hardware testing. When you generate the design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.

In addition, you can download the compiled hardware design to the Intel^® Stratix^® 10 MX FPGA Development Kit. Intel^® provides a compilation-only example project that you can use to quickly estimate IP core area and timing.

The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design. The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench. The compilation-only design example is located in <design_example_dir>/compilation_test_design.

Figure 4. Example Design Tab in the H-Tile Hard IP for Ethernet Intel FPGA IP Parameter Editor

Follow these steps to generate the H-Tile Hard IP for Ethernet Intel FPGA IP hardware design example and testbench:

1. If you do not already have an Intel^® Quartus^® Prime Pro Edition project in which to integrate your H-Tile Hard IP for Ethernet Intel FPGA IP core, you must create one.
   1. In the Intel^® Quartus^® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Intel^® Quartus^® Prime project. The wizard prompts you to specify a device.
   2. Specify the device family Intel Stratix 10 and select a device that meets all of these requirements:
      • Transceiver tile is H-tile
      • Transceiver speed grade is –1 or –2
      • Core speed grade is –1 or –2
   3. Click Finish.
2. In the IP Catalog, locate and select H-tile Hard IP for Ethernet Intel FPGA IP. The New IP Variation window appears.
3. Specify a top-level name <your_ip> for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
4. Click OK. The parameter editor appears.
5. On the IP tab, specify the parameters for your IP core variation.
   Important: The design example testbench supports only the default IP parameter settings listed below. Any changes to these settings may cause simulation failure in the testbench.

   IP Parameter Settings	Default Value
   Ready latency	0
   TX maximum frame size	1518
   RX maximum frame size	1518
   Enforce maximum frame size	Disable
   Link fault generation option	Off
   Stop TX traffic when link partner send pause	No
   Bytes to remove from RX frames	Remove CRC bytes
   Forward RX pause requests	Disable
   Use source address insertion	Disable
   TX VLAN detection	Enable
   RX VLAN detection	Enable
   PHY Reference Frequency	644.53125
   Enable AN/LT	Disable
   Enable Native PHY Debug Master endpoint (NPDME)	Disable
   Enable JTAG to Avalon Master Bridge	Disable

6. On the Example Design tab, under Example Design Files, select the Simulation option to generate the testbench and the compilation-only project. Select the Synthesis option to generate the hardware design example.
   Note: You must select at least one of the Simulation and Synthesis options to generate the design example.

   Note: You must select the Simulation option to generate the testbench.
7. On the Example Design tab, under Generated HDL Format, select Verilog HDL or VHDL
   Note: If you select VHDL, you must simulate the testbench with a mixed-language simulator. The device under test in the ex_100G directory is a VHDL model, but the main testbench file is a System Verilog file.
8. Under Target Development Kit select the Stratix 10 MX FPGA Development Kit to generate the hardware design example. Selecting None generates only the simulation and compilation-only design examples.
   Note: The compilation-only and hardware design examples target your project device. For correct hardware design functionality out of the box, you must ensure your project device is the device on your development kit.
9. Under Target Device select 1SM21BHU2F53E1VG or 1SM21BHU2F53E2VGS1.
10. Click the Generate Example Design button. The Select Example Design Directory window appears.
11. If you want to modify the design example directory path or name from the defaults displayed (alt_ehipc2_0_example_design), browse to the new path and type the new design example directory name (<design_example_dir>).

Follow these steps to simulate the testbench:

1. Change to the testbench simulation directory <design_example_dir>/example_testbench.
2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
3. Analyze the results. The successful testbench sends ten or fourteen packets, receives the same number of packets, and displays "Testbench complete."

   Table 3.  Steps to Simulate the Testbench

   Simulator	Instructions
   Mentor Graphics ModelSim*	In the command line, type vsim -do run_vsim.do If you prefer to simulate without bringing up the ModelSim GUI, type vsim -c -do run_vsim.do Note: The ModelSim* - Intel® FPGA Edition simulator does not have the capacity to simulate this IP core. You must use another supported ModelSim simulator such as ModelSim* SE.
   Cadence NCSim	In the command line, type sh run_ncsim.sh
   Synopsys VCS*/VCS MX*	In the command line, type sh run_vcs.sh or sh run_vcsmx.sh Note: run_vcs.sh is only available if you select Verilog as the Generated HDL Format. If you select VHDL as the Generated HDL Format, you must simulate the testbench with a mixed language simulator using run_vcsmx.sh.
   Xcelium*	In the command line, type sh run_xcelium.sh

The successful test run displays output confirming the following behavior:

1. Waiting for the ATX PLLs to lock.
2. Waiting for RX transceiver reset to complete.
3. Waiting for RX alignment.
4. Sending ten (MAC+PCS, OTN, and FlexE) or hundred (PCS Only) packets.
5. Receiving those packets (MAC+PCS, OTN, and FlexE) or receiving and checking those packets (PCS Only).
6. Displaying Testbench complete.

To compile the compilation-only example project, follow these steps:

1. Ensure compilation design example generation is complete.
2. In the Intel^® Quartus^® Prime Pro Edition software, open the Intel^® Quartus^® Prime Pro Edition project <design_example_dir>/compilation_test_design/alt_ehipc2.qpf.
3. On the Processing menu, click Start Compilation.

After successful compilation, reports for timing and for resource utilization are available in your Intel^® Quartus^® Prime Pro Edition session.

To compile the hardware design example and configure it on your Intel^® Stratix^® 10 device, follow these steps:

1. Ensure hardware design example generation is complete.
   Note: The hardware design example in Intel^® Quartus^® Prime version 19.1 supports only MAC+PCS and PCS Only variants.
2. In the Intel^® Quartus^® Prime Pro Edition software, open the Intel^® Quartus^® Prime project <design_example_dir>/hardware_test_design/alt_ehip2.qpf.
3. On the Processing menu, click Start Compilation.
4. After successful compilation, a .sof file is available in your specified directory. Follow these steps to program the hardware design example on the Intel^® Stratix^® 10 device:
   1. On the Tools menu, click Programmer.
   2. In the Programmer, click Hardware Setup.
   3. Select a programming device.
   4. Select the Stratix 10 MX FPGA Development Kit to which your Intel^® Quartus^® Prime Pro Edition session can connect.
   5. Ensure that Mode is set to JTAG.
   6. Select the Intel^® Stratix^® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
   7. In the row with your .sof, check the box for the .sof.
   8. Check the box in the Program/Configure column.
   9. Click Start.

After you compile the H-Tile Hard IP for Ethernet Intel FPGA IP core design example and configure it on your Intel^® Stratix^® 10 device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.

You can test the H-Tile Hard IP for Ethernet Intel FPGA IP hardware design example in either MAC + PCS mode or PCS Only mode.

set  log_file_handle [open loopback_test_results.log w]

source main.tcl
set PCS_pkt_client_base 0xf000 
set frame_type_list { "incr" "constant"  "random"} 

proc hard_reset { }  
{
    open_issp *
    sp_assert_reset
    sp_deassert_reset
    close_issp 
}
proc random_element { list } {
    lindex $list [expr {int (rand()* [llength $list])}]
}

proc random { {min 30 } { max 100 } } \
{
    return [expr {int($min + rand() * $max)}]
}

proc start_pcs_pkt_gen { } \
{
   variable PCS_pkt_client_base
    reg_write $PCS_pkt_client_base 0x0 0x01
}

proc read_pcs_pkt_gen { } \
{
    variable PCS_pkt_client_base
    set res [reg_read $PCS_pkt_client_base 0x2]
    return $res
}

proc pcs_gen_num_frames { { num_frames 200} } \
{
    variable PCS_pkt_client_base
    reg_write $PCS_pkt_client_base 0x6 $num_frames
}

proc get_pcs_gen_num_frames { } \
{
    variable PCS_pkt_client_base
    reg_read $PCS_pkt_client_base 0x6
}

proc pcs_gen_frame_size { { frame_size 200} } \
{
    variable PCS_pkt_client_base
    reg_write $PCS_pkt_client_base 0x7  $frame_size
}

proc get_pcs_gen_frame_size {   } \
{
    variable PCS_pkt_client_base
    reg_read $PCS_pkt_client_base 0x7
}
proc get_pcs_gen_match_count {   } \
{
    variable PCS_pkt_client_base
    reg_write $PCS_pkt_client_base 0x8 
}

proc get_pcs_gen_mismatch_count {   } \
{
    variable PCS_pkt_client_base
    reg_read $PCS_pkt_client_base 0x9
}

proc pcs_gen_set_frame_type { {frame_type "incr"} } \
{
    variable PCS_pkt_client_base
    if {$frame_type == "incr"} {
        reg_write $PCS_pkt_client_base 0xa 0x1 
    } elseif    { $frame_type == "constant" } {
        reg_write $PCS_pkt_client_base 0xa 0x3 
    } elseif    { $frame_type == "random" } {
        reg_write $PCS_pkt_client_base 0xa 0x4 
    } else { 
        puts "ERROR"
        return -1
    }
    return 0
}

proc pcs_only_traffic_test { iterations } {
    variable    log_file_handle
    variable    frame_type_list
    set test_name [lindex [info level [info level]] 0]
    puts "Running ${test_name} test"
    after 100   
    #hard_reset
    chkphy_status
    set phy_locked [phy_locked]              
    puts "Phy locked status is $phy_locked "	
    # global $CLIENT_BASE
    set PCS_pkt_client_base 0xf000 
    for {set i 0} {$i < $iterations} {incr i} {
        #randomize some stuff. Like number and size of Frames
        set res [random 30 16384]
        puts "Setting Number of frames to $res\n"
        pcs_gen_num_frames $res
        set res [random 30 16384]
        puts "Setting Size of frames to $res\n"
        pcs_gen_frame_size $res
        set res [random_element $frame_type_list]
        puts "Setting Type of frames to $res\n"
        pcs_gen_set_frame_type $res
        puts "PCS TRAFFIC = ${i}" 
       start_pcs_pkt_gen
        after 1000
        set res [read_pcs_pkt_gen]
        if { $res == 0x53} {
            puts  "${test_name}:pass"
        } else {
            puts  "${test_name}:fail, Got $res instead of 0x53"
            puts $log_file_handle "${test_name}:fail, Got $res instead of 0x53"
            return -1
        }
    }
    puts $log_file_handle "${test_name}:pass"
    return 0
}

proc pcs_gen_result { } \
{
    variable PCS_pkt_client_base
    set pass [read_pcs_pkt_gen]
    set max_frames [reg_read $PCS_pkt_client_base 0x6]
    set frame_size [reg_read $PCS_pkt_client_base 0x7]
    set match_count [reg_read $PCS_pkt_client_base 0x8]
    set mismatch_count [reg_read $PCS_pkt_client_base 0x9]
    set frame_type [reg_read $PCS_pkt_client_base 0xa]

    if { $pass == 0x53} {
        puts  "Last test passed!\n"
    } else {
        puts  "Last test failed, Got $pass instead of 0x53"
    }
    puts "Num of frames = $max_frames" 
    puts "Frame size    = $frame_size" 
    puts "Match count    = $match_count" 
    puts "Mismatch count    = $mismatch_count" 
    if {$frame_type == 0x1} {
        puts "Frame Type = incr"  
    } elseif    { $frame_type == 0x9 } {
        puts "Frame type = constant_crc"  
    } elseif    { $frame_type == 0x3 } {
        puts "Frame type = constant"  
    } elseif    { $frame_type == 0x4 } {
        puts "Frame type = random"  
    }
}    

To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates a copy of the IP core; the testbench, compilation-only, and hardware design example use this variation as the DUT. If you do not set the parameter values for the DUT to match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.