The DisplayPort Intel® FPGA IP
interface consists of a Main link, an auxiliary channel (AUX CH), and a Hot-Plug Detect (HPD)
Main Link—Main Link is a unidirectional, high-bandwidth channel that
transports video and audio over 1, 2, or 4 lanes at 8.1, 5.4, 2,7, and 1.62 Gigabits per
second (Gbps) per lane. All lanes carry data. The clock is embedded in 8b/10b encoded serial
AUX CH—The AUX CH is 1 Megabits per second (Mbps) half-duplex bidirectional
channel used for link management and device control.
HPD—The DisplayPort Intel® FPGA IP sink
device uses HPD to detect its presence, The HPD signal serves as an interrupt request by the
DisplayPort sink device.
Figure 1. DisplayPort Intel® FPGA IP DisplayPort
Transport ChannelsThis figure shows the DisplayPort Intel® FPGA IP link between a source and a sink device.
1.1.1. Main Link
The DisplayPort Intel® FPGA IP Main
Link is a unidirectional, high-bandwidth channel used to transport video and audio
Figure 2. Main Link Differential Pair with FPGA Transceiver PHYThis figure shows a Main Link differential pair. The DisplayPort Intel® FPGA IP source must have AC-coupling capacitors.
AC-coupling for DisplayPort Intel® FPGA IP sink is
18.104.22.168. Main Link TX
The Main Link TX drives doubly-terminated AC-coupled differential
The FPGA Transceiver PHY TX includes on-chip 100 ohm differential
termination and bias voltage generation. You may add a repeater such as a retimer or a
redriver in between the FPGA and the external DisplayPort connector to compensate for
DisplayPort TX specification for the Main Link allows four
differential peak-to-peak voltage swing levels, and four pre-emphasis (Post Cursor1)
levels. Certain combinations of voltage swing levels and pre-emphasis levels that
result in differential peak-to-peak swing outside the allowable range (1.38 V) are
The reconfiguration management module available in the
Quartus® Prime design example includes a sub-module that
translates the DisplayPort voltage swing and pre-emphasis levels to the FPGA
transceiver setting. Refer to Table 3 for more information.
Use the reconfiguration management file and a sub-module of the
Quartus® Prime design examples that maps the
DisplayPort levels to the transceiver analog parameter setting.
To mitigate system signal losses, you may place a redriver or
retimer between the FPGA and the external DisplayPort connector for a box-to-box
connection. In such designs, place the repeater close to the external DisplayPort
connector and generate the DisplayPort signals at the voltage and pre-emphasis
levels determined during link training, instead of the FPGA.
In this case, you can turn off the Support analog reconfiguration option in the DisplayPort Intel® FPGA IP parameter editor and set the
FPGA voltage swing in the QSF assignments. The selection of the appropriate
signaling level between the FPGA and the repeater depend on the PCB loss and the
equalization of the redriver/retimer input. The typical setting for the transmitter
is 400 mV voltage swing without pre-emphasis.
Bonded TX channels placed in a single transceiver bank results in lower
channel-to-channel skew, allowing more skew budget at the board level. For information about
the maximum channel-to-channel skew, refer to the Device
You have the option to select bonding mode through the Transceiver PHY parameter editor.
Table 2. Bonding Mode Selection Guidelines
Transceiver PHY Bonding Mode
Cyclone® 10 GX
PMA and PCS bonding
Requires bonded TX channels to be placed contiguously
Channel 0 is selected as a bonding master
Uses x6/xN clock network driven by Master Clock Generation
Block (MCGB). MCGB is enabled in the TX PLL (e.g. fPLL) parameter editor.
Note: The digital reset signal (tx_digitalreset) to all TX channels within a bonded group must meet a
maximum skew tolerance of one-half the TX parallel clock cycle (tx_clkout). Refer to the Timing
Constraints for Bonded PCS and PMA Channels section of the respective Transceiver PHY User Guides for more information.
Table 3. Recommended Combinations of Voltage Swing and Pre-Emphasis
LevelsThis table lists the 4 levels of voltage swing level defined in the Video
Electronics Standards Association (VESA) DisplayPort Standard. The combination of
these levels is independent of the devices. Intel FPGA devices
support all 4 levels. The mapping between the DisplayPort levels and the actual PMA values
is provided in the DisplayPort Intel® FPGA IP design examples.
Voltage Swing Level
Table 4. Guidelines on the Usage of the TX Repeater Device
Use the listed Main Link transmitter electrical parameters for reference.
Refer to the VESA DisplayPort Standard for other transmitter
Table 5. TP2 (TX External Connector)
Note: The Lane-to-Lane
Output Skew specification at TP2 in VESA DisplayPort Standard
version 1.2a differs from version 1.4.
Maximum Output Voltage Level
Maximum differential peak-to-peak swing for all output level and
Lane-to-Lane Output Skew
VESA DisplayPort Standard version 1.4 for
all data rates
Lane-to-Lane Output Skew (HBR, RBR)
VESA DisplayPort Standard version 1.2a for
HBR and RBR
Lane-to-Lane Output Skew (HBR2)
4 UI + 500 ps
VESA DisplayPort Standard version 1.2a for
Table 6. TP3_EQ (Compliance Cable Model with Reference Receiver Equalizer)
Maximum TX Total Jitter
For HBR3, TPS4 pattern, at 1E-9
For HBR2, CP2520 pattern, at 1E-9
For HBR2, D10.2 pattern, at 1E-9
TX Differential Peak-to-Peak EYE Voltage at HBR3
For HBR3, TPS4 pattern, at 1E-9
TX Differential Peak-to-Peak EYE Voltage at HBR2
For HBR2, CP2520 pattern, at 1E-9
Note: For more information about TP2 and TP3_EQ compliance measurement points and
reference receiver equalizer, refer to the VESA DisplayPort Standard.
22.214.171.124. Main Link RX
The FPGA Transceiver PHY RX includes on-chip 100 ohm differential
termination and bias voltage generation.
You may add an RX repeater such as a retimer or a redriver in between the
FPGA and the external DisplayPort connector to clean up jitter and compensate for losses.
AC-coupling is optional for Main Link RX.
By default, the
software enables differential 100 ohm OCT and bias voltage generation. Your design
does not require external 50 ohm termination and bias voltage (Vbias_RX).
RX Repeater (Redriver or Retimer)
To clean up jitter and compensate for signal losses, a sink device
uses a redriver or retimer between the external DisplayPort connector and the FPGA
RX. In such systems, the device places the repeater close to the external
DisplayPort connector and regenerates the received DisplayPort signals.
The retimer includes the clock and data recovery (CDR) circuit
that cleans up the jitter.
2 The VESA DisplayPort PHY Compliance Test
Specification (CTS) version 1.4 passed in
Arria® 10 device using Parade Technologies PS8460 Retimer in RX. For other
vendors' device recommendation, please contact your nearest Intel sales representative.
Use the listed Main Link receiver electrical parameters for reference.
Refer to the VESA DisplayPort Standard for other receiver electrical
Table 9. TP3_EQ
Minimum Receiver EYE Width at HBR3
For HBR3, TPS4 pattern
RX Differential Peak-to-Peak EYE Voltage at HBR3
Minimum Receiver EYE Width at HBR2
For HBR2, CP2520 pattern
RX Differential Peak-to-Peak EYE Voltage at HBR2
Note: For more information about TP3_EQ compliance measurement point and reference
receiver equalizer, refer to the VESA DisplayPort Standard.
1.1.2. AUX Channel
The DisplayPort AUX channel is a half-duplex, bidirectional channel
running at 1 Mbps rate.
Figure 3. AUX Channel Differential PairThe AUX channel is a differential pair doubly-terminated with 50 ohm
resistors and AC-coupled at both source and sink devices.
The 100-KΩ and 1-MΩ pull-up and pull-down resistors are placed between the
connectors and AC-coupling capacitors. These resistors help detect any DisplayPort upstream
devices, including a powered DisplayPort upstream device by a sink device.
Table 10. AUX Channel Electrical SpecificationThe table shows the parameters of the DisplayPort AUX channel electrical
AUX Direct Current (DC) Common Mode Voltage
Common mode voltage is equal to Vbias_TX (or Vbias_RX)
AUX Peak-to-Peak Voltage
Differential peak-to-peak voltage swing
AUX AC-Coupling Capacitor
The AUX channel AC-coupling capacitors are placed on both the
DisplayPort upstream and downstream devices.
126.96.36.199. Implementing Bus LVDS I/O Interface
Intel devices offer
on-chip Bus LVDS
that you can use to implement the DisplayPort AUX channel.
The BLVDS I/O is a bidirectional differential I/O interface and requires
special pin assignment consideration. Depending on the FPGA bank VCCIO voltage and I/O
standard used, the BLVDS I/O may require a series resistor, Rs. The
series resistor ensures the AUX channel differential voltage swing is below the maximum
peak-to-peak voltage swing specification.
Figure 4. AUX Channel Using
InterfaceThe figure shows the FPGA BLVDS I/O with series resistors for the
DisplayPort Source (or Sink) AUX channel implementation.
Table 11. BLVDS I/O SupportThe table lists the FPGA BLVDS I/O supported features and I/O
Note: Vbias_TX (or
Vbias_RX) = VCCIO/2, VCCIO is the FPGA I/O supply voltage.
4DFFIO_TX pins do not support true
LVDS differential inputs.
188.8.131.52. Implementing Bidirectional LVDS
you can implement half-duplex, bidirectional LVDS using
Figure 5. External LVDS Line Driver/ReceiverThe figure shows an example of an external LVDS driver/receiver, TI
SN65MLVD200A used in Bitec HSMC DisplayPort daughter card.
The interface to the device is straightforward. For example, TI SN65MLVD200A
requires three LVTTL general purpose I/O pins (aux_oe,
aux_out, aux_in). If the FPGA bank I/Os are not tolerant
with LVTTL, a level shifter is required, as shown in the figure above.
There may be crosstalk from the single-ended LVTTL signals to the Main-Link
high speed signals if the traces are routed close to each other. During board signal integrity
(SI) design, pay special attention to routing.
Note: The DisplayPort Intel® FPGA IP design examples are developed based on the Bitec
DisplayPort daughter card using TI SN65MLVD200A.
184.108.40.206. Detection of DisplayPort Upstream Source Device
The DisplayPort sink device senses the AUX+ and AUX- signal logic
level to detect the upstream source.
resistors form a voltage divider that allows the sink device to detect the presence of the
upstream source device.
Between the AC-coupling capacitor and the DisplayPort connector:
The source device weakly pulls down the AUX+ line to GND and weakly pulls
up the AUX- line to DP_PWR (typically 3.3 V) with nominal 100K ohm resistors.
The sink device weakly pulls up the AUX+ line to 3.3 V and weakly pulls
down the AUX- line to GND with nominal 1M ohm resistors.
The AUX+ and AUX- lines connect to the FPGA through 10K ohm resistors (e.g.
RX_SENSE_P and RX_SENSE_N
signals in the Bitec DisplayPort daughter card). The DisplayPort Intel® FPGA IP sink senses the logic level of the AUX+ and AUX- lines
using the rx_cable_detect and rx_pwr_detect inputs and triggers the HPD signal when the powered upstream source
device is detected.
The sense signals require level translation if they are connected to an FPGA
I/O that is not 3.3V tolerant, for example,
Arria® 10 device
bank with VCCIO = 1.8 V.
1.1.3. DisplayPort Hot Plug Detect (HPD)
The DisplayPort sink device drives the HPD signal using 3.3V TTL
signal level. The upstream DisplayPort source device monitors the HPD signal.
To prevent the HPD signal from floating when not connected, tie to GND with a
>100K ohm resistor in both the DisplayPort Intel® FPGA IP
source and sink devices.
Note: The voltage level of the HPD pin uses 3.3 V
TTL. FPGA I/Os that are not tolerant with 3.3V TTL require a level shifter.
1.1.4. DisplayPort Power
For Box-to-Box DisplayPort connection, the DisplayPort source and sink
devices provide a power pin and a return current pin on the connector.
This power is provided by the DisplayPort source and sink to power up attached
devices such as a Branch device or an Active Cable Assembly.
As per the VESA DisplayPort Standard, the maximum current drawn
by an attached device is 0.5 A at 3.3V setting.
1.1.5. Bitec DisplayPort Daughter Card Revisions
The schematic diagrams of the Bitec HSMC and FMC DisplayPort daughter
cards show the connectivity for Intel FPGA