The PMBus® SmartVID Controller reference designs
show you how to interface the SmartVID Controller IP core with the Power Management Bus or
PMBus control system.
The reference designs demonstrate the following modes: PMBus Master, PMBus Slave, and PMBus
The PMBus is an open standard protocol that provides a way to communicate with
power conversion and other devices. In this reference design, the PMBus system is in
accordance to the PMBus Specification revision 1.2.
Figure 1. PMBus SmartVID Controller Reference Design. The figure shows a high-level block diagram of the reference
The PMBus SmartVID Controller reference design consists of both conduit and Avalon
Memory-Mapped (Avalon-MM) interfaces.
The SmartVID Controller IP core and the PMBus controller connect through a
conduit signal interface.
The PMBus controller and the Nios II processor communicate using the
When multiple devices start to communicate at the same time, the device writing the most
zeros to the bus or the slowest device wins the arbitration. The other devices immediately
discontinue any operation on the bus.
When there is an ongoing bus communication, all devices must detect the
communication and not interrupt it. The devices must wait for a stop condition to appear
before starting communication to the bus.
In this mode, all masters must be multi masters in a multi-master system. Single-master
systems may not understand the arbitration and busy detection mechanisms causing
The reference design supports the command language stated in the
PMBus Specification revision 1.2.