Altera® MAX® II, MAX V, and MAX 10 FPGA devices serve as a bridge between a host that has serial peripheral interface (SPI)
to communicate with devices connected through an I2C bus.
The I2C is a serial, two-wire, low-bandwidth, industry standard protocol
used in embedded systems to communicate with various low-speed
peripheral devices. The SPI is a widely used, fast,
four-wire, full duplex, serial communication interface.
systems today have SPI interfaces, making it difficult to connect them
with peripheral devices in an I2C fashion. You can make the connection by modifying the system, but this is economically inefficient. The best solution is
to use Altera devices as a bridge to connect the two interfaces.
You can use the MAX II, MAX V, or MAX 10 FPGA devices to implement the bridge. Altera devices provide greater flexibility,
consume less power, and can be
economically integrated into the embedded system. The MAX II, MAX V, or MAX 10 FPGA device acts
as an SPI slave to the host (SPI master) and acts as a master to the I2C bus.
The provided designs enable an SPI-equipped host to control data flow to
other devices such as Analog-to-Digital (AD) converter, LED controller, audio processor
to read temperature sensors, hardware monitors, and diagnostic sensors
that are on an I2C interface.
Figure 1. Implementing an SPI to I2C Interface Using a MAX II CPLD. The figure below shows a block diagram of a design example that uses a MAX II device.
The bridge interfaces with the SPI host as an SPI slave using four wires, SS and SCLK signals for control, and MISO and MOSI signals for data. The side interfacing with the I2C bus has two wires, and SCLK and SDA signals.
The SPI bus has only one master, which is connected to many slaves.
Altera device acts as one of the slaves to the SPI master device.
Figure 2. Timing Diagram for SPI.
Table 1. SPI Interface Pins. The table below describes the SPI pins.
Input (active low)
The SPI sends:
command register (8 bits)
data in (8 bits)
The SPI receives:
status register (8 bits)
data out (8 bits)
The SPI word length is fixed at 16 bits.
In every SPI word, the command register dictates
the functions on the I2C bus, and the data in holds the data to be sent by
the I2C bus. Similarly, the last bit of the status register is the acknowledge
bit and the data out is the data received over the I2C line in the previous
At the end of every SPI bus:
The slave select line goes high; indicating a
The master executes an I2C bus as per the value of command register at that time.
After a fixed delay, depending on the frequency of
the I2C SCL, another SPI word can be sent. The minimum delay between
two SPI words is the I2C SCL clock frequency.
Altera device acts as a master to the I2C bus.
Because the designs are meant to provide an interface between an SPI master and an I2C device, multi-master support is not provided on the I2C bus.
Table 2. I2C Interface Pins. The table below describes the I2C interface pin.
I2C serial clock
I2C data bus
The I2C functions are carried out based on the command register value
received from the SPI side.
Table 3. I2C Commands. The table below describes the significance of the value stored in the
Data In Register
Function on the I2C Line
Slave address + R/W
Data to be written
Write a byte
Read a byte
Null, wait state
The data read in a particular I2C transaction is stored in the data out
register and is read by the SPI master in its next SPI transaction. The last
command word, 00000000 (b), is required for the SPI master to read the
value of status and data out registers without doing anything on the I2C
Figure 3. I2C Command Format
Implementing the Design
You can implement the design by using the source code and allocating the appropriate signal and control lines to the general
purpose I/O (GPIO) lines of the Altera devices. You require an SPI master and an I2C slave as additional resources to demonstrate this implementation.
The MAX II design uses an EPM240 device. You can also implement this application in MAX V and MAX 10 devices.
Note: The MAX II design has been implemented in Verilog and successful operation
has been demonstrated using the MDN-B2 demo board. The source code, testbench, and the complete Quartus II
project are available in the provided design example files.
Document Revision History
Added MAX V and MAX 10 devices.
Removed outdated information from the implementation section.