AN 807: Configuring the Intel Arria 10 GX FPGA Development Kit for the Intel FPGA SDK for OpenCL
Configuring the Intel Arria 10 GX FPGA Development Kit for the Intel FPGA SDK for OpenCL
You must complete the instructions in this document before you can use your Intel® Arria® 10 GX FPGA Development Kit with the Intel® FPGA SDK for OpenCL™ . The instructions require you to be familiar with Intel® Quartus® Prime software and hardware assembly to avoid damaging the Intel® Arria® 10 GX FPGA Development Kit PCIe card.
The instructions in this document are best carried out by or with the assistance of an Intel® Programmable Systems Group Field Application Engineer.
Configuring and Installing the Intel Arria 10 GX FPGA Development Kit board
To use the Intel® Arria® 10 GX FPGA Development Kit with the Intel® FPGA SDK for OpenCL™ , you must install the DDR4 memory module, configure certain DIP switches on the board, and add the board to your host system.
-
Install the DDR4 memory module as follows:
-
Locate the heat sink on the
Intel®
Arria® 10 GX FPGA Development Kit board:
-
Remove the heat sink from the board by squeezing and
pushing out the two pins from the back of the board.
-
Locate the HiLo connector that was previously hidden by
the heat sink
-
Plug the DDR4 memory module into the HiLo
connector.
The DD4 memory module provided with the Intel® Arria® 10 GX FPGA Development Kit looks like the following image:
After you have plugged in the DDR4 memory module, your Intel® Arria® 10 GX FPGA Development Kit card should look like the following image:
- Reinstall the heat sink on the board. Make sure that the two fans are visible.
-
Locate the heat sink on the
Intel®
Arria® 10 GX FPGA Development Kit board:
-
Configure the following DIP switches: SW3, SW4, SW5, and
SW6:
-
Locate the SW3 DIP switch on the front of the
board:
-
Ensure that the SW3 DIP switch is configured as
follows:
-
Locate the SW4, SW5, and SW6 DIP switches on the back
of the board:
-
Ensure that the SW4, SW5, and SW6 DIP switches are
configured as follows:
-
Locate the SW3 DIP switch on the front of the
board:
-
Add the
Intel®
Arria® 10 GX FPGA
Development Kit card to your host system:
-
Plug the card into a PCIe Gen3 x8 slot on your host
system.
-
Connect the 6-pin power cable to the card.
-
Connect the card to your host USB subsystem using the
micro USB cable.
-
Plug the card into a PCIe Gen3 x8 slot on your host
system.
Initializing the Intel Arria 10 GX FPGA Development Kit for use with OpenCL
Before you can use the Intel® Arria® 10 GX FPGA Development Kit with OpenCL* , you must initialize the board with an OpenCL* image. Without this image, the board host operating system does not recognize the PCIe card and the Intel® FPGA SDK for OpenCL™ Offline Compiler cannot find the device.
- Intel® FPGA Download Cable driver: Download the Intel® FPGA Download Cable driver from the Intel® FPGA Cable and Adapter Drivers Information page at the following URL:
- Intel® FPGA SDK for OpenCL™ : Download the Intel® FPGA SDK for OpenCL™ at the following URL:
To initialize the Intel® Arria® 10 GX FPGA Development Kit for use with OpenCL* :
-
Lower the JTAG clock speed to 6 MHz using the following
command:
jtagconfig --setparam 1 JtagClock 6M
If you receive " No JTAG hardware available " error message, refer to The jtagconfig command fails when initializing the Intel Arria 10 GX FPGA Development Kit for use with OpenCL for solution.
You can confirm the clock speed with the following command:
jtagconfig --getparam 1 JtagClock
-
Uncompress the following file to a temporary location:
INTELFPGAOCLSDKROOT/board/a10_ref/bringup/a10_ref_initialization.tgz
Where INTELFPGAOCLSDKROOT in the installation path for the Intel® FPGA SDK for OpenCL™ .Ensure that you have the following files in your temporary location. You need these files to complete the steps that follow.
- max5_150.pof
- top.sof
- boardtest.aocx
-
Update the MAX V CPLD system controller with the max5_150.pof file as follows:
-
Ensure that cable number 1 is the cable connected to
the
Intel®
Arria® 10 GX FPGA Development Kit with
the following command:
quartus_pgm -l
The command output should resemble the following example output:
Info: Command: quartus_pgm -l 1) USB-BlasterII [2-1.3] Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
-
Run the jtagconfig
command as follows to ensure that your
Intel® FPGA Download Cable driver is ready:
bash-4.1$ jtagconfig 1) USB-BlasterII [2-1.1] 02E060DD 10AT115N(2E2|3E2|4E2)/.. 020A40DD 5M2210Z/EPM2210
-
Run the following command to update the MAX V CPLD
system controller:
quartus_pgm -c 1 -m JTAG -o "p;max5_150.pof@2"
-
Ensure that cable number 1 is the cable connected to
the
Intel®
Arria® 10 GX FPGA Development Kit with
the following command:
-
Program the FPGA on your
Intel®
Arria® 10
GX FPGA Development Kit with the top.sof
file by running the following command:
quartus_pgm -c 1 -m JTAG -o "p;top.sof"
If you see an unexpected reboot of your system, refer to Unexpected reboot during programming the FPGA for solution.
-
Perform a soft reboot (sometimes called a warm reboot) of your
host system. On Linux systems, use the /sbin/reboot command to perform a soft reboot.
After you program the FPGA and perform a soft reboot, the host system should recognize the Intel® Arria® 10 GX FPGA Development Kit PCIe card. Your system must recognize the card before you load the Intel® FPGA SDK for OpenCL™ driver.
Installing the OpenCL Runtime Driver
After your Intel® Arria® 10 GX FPGA Development Kit board is initialized for use with the Intel® FPGA SDK for OpenCL™ Offline Compiler, install the OpenCL* runtime driver, and run a diagnostic.
To install the OpenCL* runtime driver and run a diagnostic test:
- Ensure that the AOCL_BOARD_PACKAGE_ROOT environment variable points to where you have the a10_ref board support package (BSP).
-
On Linux host systems, set the LD_LIBRARY_PATH environment variable as follows:
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$INTELFPGAOCLSDKROOT/host/linux64/lib:$AOCL_BOARD_PACKAGE_ROOT/linux64/lib
-
Install the
OpenCL*
runtime
driver by running the following command with root or administrator
privileges:
aocl install
The command should produce output like the following example output:
aocl install: Running install from /tools/aclboardpkg/altera_a10pciedk/16.0/linux64/libexec Using kernel source files from /lib/modules/2.6.32-358.el6.x86_64/build Building driver for BSP with name a10_ref make: Entering directory `/usr/src/kernels/2.6.32-358.el6.x86_64' CC [M] /tmp/opencl_driver_x6GjWS/aclpci_queue.o CC [M] /tmp/opencl_driver_x6GjWS/aclpci.o CC [M] /tmp/opencl_driver_x6GjWS/aclpci_fileio.o CC [M] /tmp/opencl_driver_x6GjWS/aclpci_dma.o CC [M] /tmp/opencl_driver_x6GjWS/aclpci_pr.o CC [M] /tmp/opencl_driver_x6GjWS/aclpci_cmd.o LD [M] /tmp/opencl_driver_x6GjWS/aclpci_a10_ref_drv.o Building modules, stage 2. MODPOST 1 modules CC /tmp/opencl_driver_x6GjWS/aclpci_a10_ref_drv.mod.o LD [M] /tmp/opencl_driver_x6GjWS/aclpci_a10_ref_drv.ko.unsigned NO SIGN [M] /tmp/opencl_driver_x6GjWS/aclpci_a10_ref_drv.ko make: Leaving directory `/usr/src/kernels/2.6.32-358.el6.x86_64'
CAUTION:The aocl install command may fail in Ubuntu* 16.04, kernel 4.14 or newer version because of a problem with the installed PCIe* drivers. Refer to The aocl install command fails due to a problem with PCIe drivers for solution.
Programming the Flash Memory on the Intel Arria 10 GX FPGA Development Kit
-
Program the flash memory on the board as follows:
-
Set the AOCL_BOARD_PACKAGE_ROOT environment variable to point
the folder that contains your
Intel®
Arria® 10
reference BSP folder:
INTELFPGAOCLSDKROOT/board/a10_ref
Where INTELFPGAOCLSDKROOT in the installation path for the Intel® FPGA SDK for OpenCL™ . -
Run the following command to program the flash memory.
This command does not use PCIe. It requires only JTAG.
aocl flash acl0 boardtest.aocx
-
Set the AOCL_BOARD_PACKAGE_ROOT environment variable to point
the folder that contains your
Intel®
Arria® 10
reference BSP folder:
- Perform a hard reboot (sometimes called a cold reboot) of your host system. That is, power your host system down, then turn the host system power back on.
-
Confirm that the initialization completed successfully by
running the following command:
aocl diagnose
The command should produce output like the following example output:aocl diagnose: Running diagnose from /tools/aclboardpkg/altera_a10pciedk/16.0/linux64/libexec ------------------------- acl0 ------------------------- Vendor: Intel Corporation Phys Dev Name Status Information acla10_ref0 Passed Arria 10 Reference Platform PCIe dev_id = 2494, bus:slot.func = 04:00.00, Gen3 x8 FPGA temperature = 38.8 degrees C. DIAGNOSTIC_PASSED
At this point, you can see the Intel® Arria® 10 GX FPGA Development Kit board as a PCIe device on your system.
On Linux host systems, the /sbin/lspci | grep Altera command should return output similar to the following example output:-baseh-4.1$ lspci | grep Altera 03:00.0 Class 1200: Altera Corporation Device 2494 (rev 01)
On Windows host systems, the Windows device manager should show the device under Accelerators, similar to the following example:
Troubleshooting
If you encounter errors when you configure the Intel® Arria® 10 GX FPGA Development Kit for the Intel® FPGA SDK for OpenCL™ , review the sections that follow for possible solutions.
The Quartus Programmer might display errors when your run aocl flash or aocl program
Info: Command: quartus_pgm -c 1 flash.cdf Info (213045): Using programming cable "USB-BlasterII [2-1.1]" Info (209060): Started Programmer operation at Wed Mar 22 13:56:27 2017 Error (209025): Can't recognize silicon ID for device 2 Error (209025): Can't recognize silicon ID for device 2 Error (209012): Operation failed Info (209061): Ended Programmer operation at Wed Mar 22 13:56:28 2017
This error indicates that the MAX V CPLD system controller is not programmed with the correct image.
Solution
Use the Quartus Programmer to update the MAX V configuration with the max5_150.pof file for Intel® Arria® 10 GX FPGA Development Kit boards. If the error persists, program the FPGA with the top.sof file and program the flash memory with the aocl flash command again.
Quartus Programmer fails while programming either the FPGA or flash memory
- Error (209014): CONF_DONE pin failed to go high in device 1
- Error (209012): Operation failed
Solution
jtagconfig --setparam 1 JtagClock 6M
jtagconfig --getparam 1 JtagClock
For Microsoft* Windows users, Intel FPGA Download Cable driver might not be installed on your host
On Windows host systems, the Intel® FPGA Download Cable (formerly USB-Blaster) needs a driver installed for the cable to function properly.
Solution
Download the Intel® FPGA Download Cable driver from the Intel® FPGA Cable and Adapter Drivers Information page at the following URL:
After you install the drivers, you should see the cable listed in Windows device manager as follows:
PCIe read/write speed is slower than expected
If you find that your PCIe read/write speed is slower than you expect, then your board might not be plugged into the correct PCIe slot.
Solution
Verify that your Intel® Arria® 10 GX FPGA Development Kit is plugged into the PCIe Gen3x8 slot on your host system. See " Configuring and Installing the Intel Arria 10 GX FPGA Development Kit board " to see what the correct PCIe slot looks like.
Memory module is not plugged in or a loose connection on the board
aocl diagnose: Running diagnose from aocl diagnose: failed 32 times. First error below: Vendor: Intel Corporation MMD INFO: [acla10_ref0] uniphy(s) did not calibrate. Expected 0 but read 2 MMD INFO: If there are more failures than Uniphy controllers connected, MMD INFO: ensure the uniphy_status core is correctly parameterized.
Solution
Confirm that you have connected the memory board, the power cable, and USB cable correctly as shown in " Configuring and Installing the Intel Arria 10 GX FPGA Development Kit board ". If you have confirmed your connections and continue to get this error, the memory board might not be seated correctly in the HiLo connector.
The jtagconfig command fails when initializing the Intel Arria 10 GX FPGA Development Kit for use with OpenCL
You might receive No JTAG hardware available error message when you run the jtagconfig command to lower the JTAG clock speed.
Solution
- Restart the jtag daemon using the following
commands:
$ sudo killall -9 jtagd $ sudo jtagd
- Confirm that the jtagconfig command works correctly. For
example:
$jtagconfig 1) USB-BlasterII [3-11] 02E660DD 10AX115H1(.|E2|ES)/10AX115H2/.. 020A40DD 5M(1270ZF324|2210Z)/EPM2210
Unexpected reboot during programming the FPGA
You might experience an unexpected reboot during programming the FPGA on your Intel® Arria® 10 GX FPGA Development Kit leading to the FPGA not getting programmed and you are unable to proceed.
Solution
Program the non-volatile flash device manually using the following steps:
- Run the following commands to generate the flash.cof and flash.cdf
files:
$ cd /hld $ source init_opencl.sh $ cd board/a10_ref/bringup $ aocl flash acl0
Note: The aocl flash acl0 command above might report failed but it still generates the required flash.cof and flash.cdf files. - Verify that the flash.cof and flash.cdf are now in the bringup directory.
- Run the following commands to generate the flash.pof file and program
the flash
device:
$ jtagconfig --setparam 1 JtagClock 6M $ aocl binedit boardtest.aocx get .acl.fpga.bin fpga.bin $ aocl binedit fpga.bin get .acl.sof fpga_temp.sof $ quartus_cpf --convert flash.cof $ quartus_pgm -c 1 flash.cdf
- Reboot the computer.
- Verify that the flash device was programmed correctly using the following steps:
- Run the following commands to install the
driver:
$ cd /hld $ source init_opencl.sh $ aocl install /hld/board/a10_ref/
- Reboot the computer.
- Run the following commands to run the
diagnostic:
$ cd /hld $ source init_opencl.sh $ aocl diagnose acl0
One of the following might happen:
- If the aocl diagnose command passes, then the flash device was programmed correctly and you can proceed.
- If the aocl diagnose
command fails, use the lspci command to verify
that the card was recognized. Search for Intel® FPGA boards.
- If the lspci command displays that the board is recognized but the aocl diagnose command fails, then rerun the aocl install command.
- If the lspci command does not show that the board is recognized, double-check all switches and jumpers on the board and double-check that the memory module is seated correctly.
- Run the following commands to install the
driver:
The aocl install command fails due to a problem with PCIe* drivers
The aocl install command might fail in Ubuntu* 16.04, kernel 4.14 or newer version because of a problem with the installed PCIe* drivers.
The following error message might appear after running the aocl install command:
Makefile:976: "Cannot use CONFIG_STACK_VALIDATION=y, please install libelf-dev, libelf-devel or elfutils-libelf-devel"
Solution
To fix this issue, perform the following steps:
- Prevent the altera-cvp driver from being used in future by creating a text file /etc/modprobe.d/blacklist-altera-cvp.conf with a line blacklist altera_cvp.
- Rerun the aocl install command and verify that the error message does not appear.
Document Revision History of Configuring the Intel Arria 10 GX FPGA Development Kit for the Intel FPGA SDK for OpenCL
Document Version | Changes |
---|---|
2020.02.14 | Added troubleshooting information for the
following issues:
|
Date | Version | Changes |
---|---|---|
May 2018 | 2018.05.04 |
|
November 2017 | 2017.11.16 |
|
May 2017 | - | Initial release. |