AN822: Intel Configuration Device Migration Guideline
Intel Configuration Device Migration Guideline
Migration Considerations
You must consider the following items to determine the compatibility and the next step of action for a successful device migration.
IP Cores
If you are using Intel® IP cores, you may need to regenerate and recompile your design. In certain conditions, the programming files can be reused without recompilation. Refer to IP Core Compatibility for more information about IP core compatibility.
Pins, Package and Capacity
Migration can only be done to an EPCQA device that has sufficient capacity for the programming file and have the same pin count package.
Pin 3 (nRESET) on the EPCQ64A and EPCQ128A devices act as a reset pin. This pin has an internal pull-up and if you do not use the reset function, connect the nRESET pin to either VCC or leave it unconnected. Refer to Pin Information for more information about the pin-outs and descriptions.
Operation Commands
The dummy clock requirement of the fast read (0Bh) and extended quad input fast read (EBh) commands:
- EPCQ—the dummy clock is configurable with the non-volatile configuration register (NVCR). When the EPCQ is used with a Cyclone® V, Arria® V or Stratix® V device, the dummy clock is configured to be 4, 10 or 12, depending on the byte-addressing mode and ASx1 or ASx4 configuration. However, in EPCQA devices, the dummy clock is fixed at 8 and 6 for fast read and extended quad input fast read respectively. Therefore you must regenerate the programming files, such as .pof, .jic, and .rpd.
- EPCS—the dummy clock is fixed at 8 for fast read, therefore you do not have to regenerate the programming files if all other conditions are met. Refer to IP Core and Programming File Migration Guideline for more information about the conditions.
Status Register
Status Register contains the Top/Bottom (TB) bit (bit 5), Block Protect (BP) bits (bit 4, bit 3, bit 2) for sector protection bits. EPCS devices do not have TP bit and some EPCQ device densities have BP3 (bit 6), while bit 6 is reserved in EPCQA devices. Due to this differences, you may need to recompile the programming file if your design uses the sector protect feature. Refer to Status Register for more information about status registers and sector protect bits.
Sector Size
All of the EPCS and EPCQ devices have the sector size of 512kb except for EPCS128 which has 2Mb. This impacts the sector erase operation. If the design is erasing the flash during user mode, you must update your design to comply the sector size when migrating from EPCS128 to EPCQ128A. After updating your design, regenerate a new programming file for the EPCQA device.
Software Migration Guidelines
IP Core Compatibility
IP Core | Compatibility | Condition |
---|---|---|
ASMI Parallel | Yes/No |
|
Serial Flash Controller | Yes/No | |
Serial Flash Loader (SFL) | Yes/No |
|
Remote Update | Yes |
IP Core | Compatibility | Condition |
---|---|---|
ASMI Parallel | Yes/No |
|
ASMI Parallel II | No | — |
Serial Flash Controller | No | — |
Serial Flash Controller II | No | — |
Generic QSPI Controller | No | — |
Generic QSPI Controller II | No | — |
Serial Flash Loader | Yes/No |
|
Remote Update | Yes | — |
Programming File Compatibility
Programming File | Programming File Compatibility | Condition | |
---|---|---|---|
Programmer Object File (.pof) | Yes/No |
|
|
JTAG Indirect Configuration File (.jic) | |||
Raw Programming Data (.rpd) | |||
JAM STAPL File (.jam/.jbc) | |||
Serial Vector Format (.svf) | No | — |
IP Core and Programming File Migration Guideline
Refer to the following diagram to determine the subsequent tasks and guidelines for migration:
- IP core and programming file are incompatible—regenerate IP core and programming file shown in IP Core Regeneration Guideline.
- Programming file is incompatible—regenerate programming file shown in Programming File Regeneration Guideline.
- IP core and programming file are compatible—no additional task required and you can reuse the existing programming file.
IP Core Regeneration Guideline
To regenerate the IP core and programming file with the correct settings, perform the following steps:
- Regenerate the desired IP cores.
- If you use the sector protect feature:
- For EPCQ4A, EPCQ16A, and EPCQ32A—ensure the status register bit [6:5] is set to 0.
- For EPCQ64A—ensure the status register bit [6] is set to 0.
- For EPCS128 to EPCQ128A migration—sector erase must comply to the
sector size of EPCQ128A.
Note: Sector size for EPCS128 and EPCQ128A are 2Mb and 512kb respectively.
- If you use the sector protect feature:
- Recompile the configuration bitstream to obtain the .sof file.
Programming File Regeneration Guideline
To regenerate the programming file with the correct settings, perform the following steps:
- Convert the .sof file to the desired
programming file in the
Intel®
Quartus® Prime
Convert Programing File tool and ensure that you:
- Select the correct EPCQA device you are migrating to.
- Enable the Disable EPCS/EPCQ ID check option. This option is available in the Advanced Option settings of the Convert Programming File tool in Intel® Quartus® Prime software.
- For migration from EPCS devices—Select AS x1 configuration mode.
- Program the programming file into EPCQA device using Intel® Quartus® Prime Programmer.
Software Support for EPCQA Devices
Intel® Quartus® Prime | IP Cores | Programmer and Programming File Generation |
---|---|---|
Intel® Quartus® Prime Pro Edition 17.1 | No | Yes |
Intel® Quartus® Prime Standard Edition 17.1 | Yes | Yes |
Specification Comparison
Operating Conditions
The following tables show the general comparison of the EPCS, EPCQ and EPCQA operating conditions. For more detailed and up-to-date information, refer to the respective device datasheet.
Parameter | Condition | Symbol | Min | Max | Unit | ||||
---|---|---|---|---|---|---|---|---|---|
EPCS | EPCQ | EPCQA | EPCS | EPCQ | EPCQA | ||||
Supply voltage | The maximum VCC rise time is 100 ms. | VCC | 2.7 | 3.6 | V | ||||
Operating temperature | For industrial use | TA | -40 | 85 | °C | ||||
High-level input voltage | — | VIH | 0.6 x VCC | 0.7 x VCC | VCC + 0.4 | V | |||
Low-level input voltage | — | VIL | -0.5 | 0.3 x VCC | V | ||||
High-level output voltage | IOH =-100µA | VOH | VCC - 0.2 | — | V | ||||
Low-level output voltage | IOL =100µA | VOL | — | 0.2 or 0.42 | V |
Timing Specifications
The following tables show the general comparison of the EPCS, EPCQ, and EPCQA operation timing. For more detailed and up-to-date information, refer to the respective device datasheet.
- t DH
- t DSU
- t nCLK2D/tCLQV
- tCLQX 3
Read Operation Timing
Symbol | Parameter | Capacity | Min | Max | Unit | ||
---|---|---|---|---|---|---|---|
EPCS | EPCQA | EPCS | EPCQA | ||||
f RCLK | Read clock frequency | All | — | — | 20 | 50 | MHz |
Fast read clock frequency | All | — | — | 40 | 100 | MHz | |
t CH | DCLK high time | 4 Mb | 11 | 4 or 6 4 | — | — | ns |
All others | 11 | 3.4 or 9 5 | — | — | |||
t CL | DCLK low time | 4Mb | 11 | 4 or 64 | — | — | ns |
All others | 11 | 3.4 or 95 | — | — | |||
t ODIS | Output disable time after read | All | — | — | 8 | 7 | ns |
t nCLK2D / tCLQV 6 | Clock falling edge to DATA | 4Mb | — | — | 8 | 7 | ns |
All others | — | — | 8 | 6 |
Symbol | Parameter | Capacity | Min | Max | Unit | ||
---|---|---|---|---|---|---|---|
EPCQ | EPCQA | EPCQ | EPCQA | ||||
f RCLK | Read clock frequency | All | — | — | 50 | 50 | MHz |
Fast read clock frequency | All | — | — | 100 | 100 | MHz | |
t CH | DCLK high time | All | 4 | 3.4 or 95 | — | — | ns |
t CL | DCLK low time | All | 4 | 3.4 or 95 | — | — | ns |
t ODIS | Output disable time after read | All | — | — | 8 | 7 | ns |
t nCLK2D / tCLQV 6 | Clock falling edge to DATA | All | — | — | 7 | 6 | ns |
Write Operation Timing
Symbol | Operation | Capacity | Min | Typical | Max | Unit | |||
---|---|---|---|---|---|---|---|---|---|
EPCS | EPCQA | EPCS | EPCQA | EPCS | EPCQA | ||||
f WCLK | Write clock frequency | All | — | — | 25 | 100 | MHz | ||
t CH | DCLK high | 4 | 20 | 4 | — | — | ns | ||
All others | 20 | 3.4 | — | — | |||||
t CL | DCLK low | 4 | 20 | 4 | — | — | ns | ||
All others | 20 | 4 | — | — | |||||
t NCSSU | Chip select ( nCS ) setup | All | 10 | 5 | — | — | ns | ||
t NCSH | Chip select ( nCS ) hold | All | 10 | 5 | — | — | ns | ||
t DSU | DATA[] in setup before DCLK rising edge | All | 5 | 2 | — | — | ns | ||
t DH | DATA[] hold time after DCLK rising edge | 4 | 5 | 5 | — | — | ns | ||
All others | 5 | 3 | — | — | |||||
t CSH | Chip select ( nCS ) high | 4 | 100 | 100 | — | — | ns | ||
All others | 100 | 10 / 507 | — | — | |||||
t WB | Write bytes cycle | 1 | — | 1.5 | — | 5 | — | ms | |
4 | — | 1.5 | 0.4 | 5 | 0.8 | ms | |||
16 | — | 1.5 | 0.4 | 5 | 3 | ms | |||
32 | — | — | 0.7 | — | 3 | ms | |||
64 | — | 1.5 | 0.8 | 5 | 3 | ms | |||
128 | — | 2.5 | 0.7 | 7 | 3 | ms | |||
t WS | Write status cycle | All | — | 5 | 10 | 15 | 15 | ms | |
t EB | Erase bulk cycle | 1 | — | 3 | — | 6 | — | s | |
4 | — | 5 | 1 | 10 | 4 | s | |||
16 | — | 17 | 5 | 40 | 25 | s | |||
32 | — | — | 10 | — | 50 | s | |||
64 | — | 68 | 20 | 160 | 100 | s | |||
128 | — | 105 | 40 | 250 | 200 | s | |||
t ES | Erase sector cycle | 4 | — | 2 | 0.15 | 3 | 1 | s | |
All others | — | 2 | 0.15 | 3 | 2 | s |
Symbol | Operation | Capacity | Min | Typical | Max | Unit | |||
---|---|---|---|---|---|---|---|---|---|
EPCQ | EPCQA | EPCQ | EPCQA | EPCQ | EPCQA | ||||
f WCLK | Write clock frequency | All | — | — | 100 | 100 | MHz | ||
t CH | DCLK high | All | 4 | 3.4 | — | — | ns | ||
t CL | DCLK low | All | 4 | 4 | — | — | ns | ||
t NCSSU | Chip select ( nCS ) setup | All | 4 | 5 | — | — | ns | ||
t NCSH | Chip select ( nCS ) hold | All | 4 | 5 | — | — | ns | ||
t DSU | DATA[] in setup before DCLK rising edge | All | 2 | 2 | — | — | ns | ||
t DH | DATA[] hold time after DCLK rising edge | All | 3 | 3 | — | — | ns | ||
t CSH | Chip select ( nCS ) high | All | 50 | 10 / 508 | — | — | ns | ||
t WB | Write bytes cycle | 16 | — | 0.6 | 0.4 | 5 | 3 | ms | |
32 | — | 0.6 | 0.7 | 5 | 3 | ms | |||
64 | — | 0.6 | 0.8 | 5 | 3 | ms | |||
128 | — | 0.6 | 0.7 | 5 | 3 | ms | |||
t WS | Write status cycle | All | — | 1.3 | 10 | 8 | 15 | ms | |
t EB | Erase bulk cycle | 16 | — | 30 | 5 | 60 | 25 | s | |
32 | — | 30 | 10 | 60 | 50 | s | |||
64 | — | 60 | 20 | 250 | 100 | s | |||
128 | — | 170 | 40 | 250 | 200 | s | |||
t ES | Erase sector cycle | All others | — | 0.7 | 0.15 | 3 | 2 | s | |
128 | — | 0.7 | 0.15 | 6 | 2 | s |
Operation Codes
The following tables summarize EPCS, EPCQ, and EPCQA operation codes. For more detailed and up-to-date information, refer to the respective device datasheet.
Operation | Operation Code | ||
---|---|---|---|
EPCS | EPCQ | EPCQA | |
Write status | 01h | ||
Write bytes | 02h | ||
Read bytes | 03h | ||
Write disable | 04h | ||
Read status | 05h | ||
Write enable | 06h | ||
Fast read | 0Bh | ||
Read silicon ID | ABh 9 | — | ABh |
Read device ID | 9Fh 10 | 9Fh | 9Fh |
Erase bulk | C7h | ||
Erase sector | D8h | ||
Erase subsector | — | 20h | 20h |
Extended dual input fast read | — | BBh | BBh |
Extended quad input fast read | — | EBh | EBh |
Extended dual input fast write bytes | — | D2h | — |
Extended quad input fast write bytes | — | 12h | — |
Quad input fast write bytes | — | — | 32h 11 |
Read NVCR | — | B5h | — |
Write NVCR | — | B1h | — |
4BYTEADDREN | — | B7h | — |
4BYTEADDEX | — | E9h | — |
Pin Information
8-pin SOIC Device Pin Information
Pin Number | AS x1 | AS x4 | |||
---|---|---|---|---|---|
EPCS | EPCQ | EPCQA | EPCQ | EPCQA | |
1 | nCS | nCS | |||
2 | DATA | DATA1 | DATA1 | ||
3 | VCC | DATA2 | |||
4 | GND | GND | |||
5 | ASDI | DATA0 | DATA0 | ||
6 | DCLK | DCLK | |||
7 | VCC | DATA3 | |||
8 | VCC | VCC |
16-pin SOIC Device Pin Information
Pin Number | AS x1 | AS x4 | |||
---|---|---|---|---|---|
EPCS | EPCQ | EPCQA | EPCQ | EPCQA | |
1 | VCC | DATA3 | |||
2 | VCC | VCC | |||
3 | Not connected | nRESET 12 | Not connected | nRESET 12 | |
4, 5, 6, 11, 12, 13 and 14 | Not connected | Not connected | |||
7 | nCS | nCS | |||
8 | DATA | DATA1 | DATA1 | ||
9 | VCC | DATA2 | |||
10 | GND | GND | |||
15 | ASDI | DATA0 | DATA0 | ||
16 | DCLK | DCLK |
Package Dimensions
8-Pin SOIC Device Package Dimensions

Symbol | Min (mm) | Typical (mm) | Max (mm) | |||
---|---|---|---|---|---|---|
EPCS/EPCQ | ECPQA | EPCS/EPCQ | ECPQA | EPCS/EPCQ | ECPQA | |
A | 1.35 | 1.35 | — | 1.6 | 1.75 | 1.75 |
A1 | 0.1 | 0.1 | — | 0.15 | 0.25 | 0.25 |
A2 | 1.25 | — | — | — | 1.65 | — |
D | — | 4.8 | 4.90 BSC | 4.85 | — | 5 |
E | — | 5.8 | 6.0 BSC | 6 | — | 6.2 |
E1 | — | 3.8 | 3.90 BSC | 3.9 | — | 4 |
L | 0.4 | 0.4 | 0.71 | 1.27 | 1.27 | |
L1 | — | — | 1.04 REF | — | — | — |
b | 0.31 | 0.33 | — | 0.41 | 0.51 | 0.51 |
c | 0.17 | 0.19 | — | 0.2 | 0.25 | 0.25 |
e | — | — | 1.27 BSC | 1.27 BSC | — | — |
Theta | 0 | 0 | — | — | 8 | 10 |
16-Pin SOIC Device Package Dimensions

Symbol | Min (mm) | Typical (mm) | Max (mm) | |||
---|---|---|---|---|---|---|
EPCS/EPCQ | ECPQA | EPCS/EPCQ | ECPQA | EPCS/EPCQ | ECPQA | |
A | 2.35 | 2.36 | — | 2.49 | 2.65 | 2.64 |
A1 | 0.1 | 0.1 | — | — | 0.3 | 0.3 |
A2 | 2.05 | — | — | 2.31 | 2.55 | — |
D | — | 10.08 | 10.3 BSC | 10.31 | — | 10.49 |
E | — | 10.01 | 10.3 BSC | 10.31 | — | 10.64 |
E1 | — | 7.39 | 7.50 BSC | 7.49 | — | 7.59 |
L | 0.4 | 0.38 | — | 0.81 | 1.27 | 1.27 |
L1 | — | — | 1.40 Ref | — | — | — |
b | 0.31 | 0.33 | — | 0.41 | 0.51 | 0.51 |
c | 0.2 | 0.18 | — | 0.23 | 0.33 | 0.28 |
e | — | — | 1.27 BSC | 1.27 BSC | — | — |
Theta | 0 | — | — | — | 8 | 8 |
Status Register
Bit | Name | Description | R/W | EPCS | EPCQ | EPCQA | ||
---|---|---|---|---|---|---|---|---|
1 | 4/16/64/128 | 16/32 | 64/128 | All | ||||
7 | RSV | Reserved | ||||||
6 | BP313 | Block Protect Bit 3 | R/W | No | No | No | Yes | No |
5 | TB | Top/Bottom Bit | R/W | No | No | Yes | Yes | Yes |
4 | BP2 | Block Protect Bit 2 | R/W | No | Yes | Yes | Yes | Yes |
3 | BP1 | Block Protect Bit 1 | R/W | Yes | Yes | Yes | Yes | Yes |
2 | BP0 | Block Protect Bit 0 | R/W | Yes | Yes | Yes | Yes | Yes |
1 | WEL | Write Enable Latch | R | Yes | Yes | Yes | Yes | Yes |
0 | WIP | Write In Progress | R | Yes | Yes | Yes | Yes | Yes |
Sector Protect
Status Register | EPCS4 | EPCQ4A | |||
---|---|---|---|---|---|
TB | BP2 | BP1 | BP0 | Protected Sectors (8 sectors) | |
x | 0 | 0 | 0 | None | None |
0 | 0 | 0 | 1 | 7 | 7 |
0 | 0 | 1 | 0 | 6-7 | 6-7 |
0 | 0 | 1 | 1 | 4-7 | 4-7 |
1 | 0 | 0 | 1 | N/A | 0 |
1 | 0 | 1 | 0 | N/A | 0-1 |
1 | 0 | 1 | 1 | N/A | 0-3 |
x | 1 | x | x | All | All |
Status Register | EPCS16 | EPCQ16 | EPCQ16A | |||
---|---|---|---|---|---|---|
TB | BP2 | BP1 | BP0 | Protected Sectors (32 sectors) | ||
0 | 0 | 0 | 0 | None | None | None |
0 | 0 | 0 | 1 | 31 | 31 | 31 |
0 | 0 | 1 | 0 | 30-31 | 30-31 | 30-31 |
0 | 0 | 1 | 1 | 28-31 | 28-31 | 28-31 |
0 | 1 | 0 | 0 | 24-31 | 24-31 | 24-31 |
0 | 1 | 0 | 1 | 16-31 | 16-31 | 16-31 |
0 | 1 | 1 | 0 | All | All | All |
0 | 1 | 1 | 1 | All | All | All |
1 | 0 | 0 | 0 | N/A | None | None |
1 | 0 | 0 | 1 | N/A | 0 | 0 |
1 | 0 | 1 | 0 | N/A | 0-1 | 0-1 |
1 | 0 | 1 | 1 | N/A | 0-3 | 0-3 |
1 | 1 | 0 | 0 | N/A | 0-7 | 0-7 |
1 | 1 | 0 | 1 | N/A | 0-15 | 0-15 |
1 | 1 | 1 | 0 | N/A | All | All |
1 | 1 | 1 | 1 | N/A | All | All |
Status Register | EPCQ32 | EPCQ32A | |||
---|---|---|---|---|---|
TB | BP2 | BP1 | BP0 | Protected Sectors (64 sectors) | |
0 | 0 | 0 | 0 | None | None |
0 | 0 | 0 | 1 | 63 | 63 |
0 | 0 | 1 | 0 | 62-63 | 62-63 |
0 | 0 | 1 | 1 | 60-63 | 60-63 |
0 | 1 | 0 | 0 | 56-63 | 56-63 |
0 | 1 | 0 | 1 | 48-63 | 48-63 |
0 | 1 | 1 | 0 | 32-63 | 32-63 |
0 | 1 | 1 | 1 | All | All |
1 | 0 | 0 | 0 | None | None |
1 | 0 | 0 | 1 | 0 | 0 |
1 | 0 | 1 | 0 | 0-1 | 0-1 |
1 | 0 | 1 | 1 | 0-3 | 0-3 |
1 | 1 | 0 | 0 | 0-7 | 0-7 |
1 | 1 | 0 | 1 | 0-15 | 0-15 |
1 | 1 | 1 | 0 | 0-31 | 0-31 |
1 | 1 | 1 | 1 | All | All |
Status Register | EPCS64 | EPCQ64 | EPCQ64A | |||
---|---|---|---|---|---|---|
TB | BP2 | BP1 | BP0 | Protected Sectors (128 sectors) | ||
0 | 0 | 0 | 0 | None | None | None |
0 | 0 | 0 | 1 | 126-127 | 127 | 126-127 |
0 | 0 | 1 | 0 | 124-127 | 126-127 | 124-127 |
0 | 0 | 1 | 1 | 120-127 | 124-127 | 120-127 |
0 | 1 | 0 | 0 | 112-127 | 120-127 | 112-127 |
0 | 1 | 0 | 1 | 96-127 | 112-127 | 96-127 |
0 | 1 | 1 | 0 | 64-127 | 96-127 | 64-127 |
0 | 1 | 1 | 1 | All | 64-127 | All |
1 | 0 | 0 | 0 | N/A | None | None |
1 | 0 | 0 | 1 | N/A | 0 | 0-1 |
1 | 0 | 1 | 0 | N/A | 0-1 | 0-3 |
1 | 0 | 1 | 1 | N/A | 0-3 | 0-7 |
1 | 1 | 0 | 0 | N/A | 0-7 | 0-15 |
1 | 1 | 0 | 1 | N/A | 0-15 | 0-31 |
1 | 1 | 1 | 0 | N/A | 0-31 | 0-63 |
1 | 1 | 1 | 1 | N/A | 0-63 | All |
Status Register | EPCS12814 | EPCQ128 15 | EPCQ128A15 | |||
---|---|---|---|---|---|---|
TB | BP2 | BP1 | BP0 | Protected Sectors (64 sectors) | ||
0 | 0 | 0 | 0 | None | None | None |
0 | 0 | 0 | 1 | 63 | 255 | 252-255 |
0 | 0 | 1 | 0 | 62-63 | 254-255 | 248-255 |
0 | 0 | 1 | 1 | 60-63 | 252-255 | 240-255 |
0 | 1 | 0 | 0 | 56-63 | 248-255 | 224-255 |
0 | 1 | 0 | 1 | 48-63 | 240-255 | 192-255 |
0 | 1 | 1 | 0 | 32-63 | 224-255 | 128-255 |
0 | 1 | 1 | 1 | All | 192-255 | All |
1 | 0 | 0 | 0 | N/A | None | None |
1 | 0 | 0 | 1 | N/A | 0 | 0-3 |
1 | 0 | 1 | 0 | N/A | 0-1 | 0-7 |
1 | 0 | 1 | 1 | N/A | 0-3 | 0-15 |
1 | 1 | 0 | 0 | N/A | 0-7 | 0-31 |
1 | 1 | 0 | 1 | N/A | 0-15 | 0-63 |
1 | 1 | 1 | 0 | N/A | 0-31 | 0-127 |
1 | 1 | 1 | 1 | N/A | 0-63 | All |
Evaluating Data Setup and Hold Timing Slack
In AS configuration scheme, the FPGA will initiate the configuration process after POR. During the configuration process, the FPGA issues flash operation commands such as read device ID, normal read and erase bulk. You must ensure that the FPGA is able to read the data correctly from the configuration devices. This is done by ensuring the setup time, tDSU and hold time, tDH meets the requirements explained in the respective FPGA device datasheets. To evaluate the tDSU and tDH in your system, follow the guideline below.
The data setup timing slack must be equal or larger than the minimum data setup time, tDSU
tDCLK – (tBT_DCLK + tCLQV + tBT_DATA) ≥ tDSU
The hold timing slack must be equal or larger than the minimum data hold time, tDH:
tBT_DCLK + tCLQX + tBT_DATA ≥ tDH
- tDCLK = Period for a DCLK cycle
- tBT_DCLK = Board trace propagation delay for DCLK from FPGA to EPCQA
- tCLQV = Clock low to output valid
- tCLQX = Output hold time
- tBT_DATA = Board trace propagation delay for Data from EPCQA to FPGA
- tDSU = Minimum data setup time required by FPGA
- tDH = Minimum data hold time required by FPGA
Document Revision History
Date | Version | Changes |
---|---|---|
August 2017 | 2017.08.14 |
|
August 2017 | 2017.08.04 | Updated minimum value for Low-level output voltage in EPCS, EPCQ and EPCQA Device Operating Conditions.. |
August 2017 | 2017.08.02 | Initial release. |