The 25GbE IP core provides a
simulation testbench and a hardware design example that supports compilation and hardware
testing. When you generate the design example, the parameter editor automatically creates the
files necessary to simulate, compile, and test the design in hardware. You can download the
compiled hardware design to an Arria 10 GT device.
Note: This design example targets the Arria 10
GT device and requires a 25G retimer. Please contact your Intel FPGA representative to inquire about a platform suitable to run this
hardware example. In some cases a loan of appropriate hardware may be available.
In addition, Intel provides a compilation-only example project that
you can use to quickly estimate IP core area and timing.
Figure 1. Design Example Usage
Design Example Directory Structure
Figure 2. 25GbE Design
Example Directory Structure
The hardware configuration and test files (the hardware design example) are
located in <design_example_dir>/hardware_test_design. The simulation files
(testbench for simulation only) are located in <design_example_dir>/example_testbench.The
compilation-only design example is located in <design_example_dir>/compilation_test_design.
Simulation Design Example Components
Figure 3. 25GbE Simulation Design
Example Block Diagram
The simulation design example top-level test file is basic_avl_tb_top.sv This file instantiates and connects an ATX
PLL. It includes a task, send_packets_25g_avl, to send and
receive 10 packets.
Table 1. 25GbE IP Core Testbench
Testbench and Simulation Files
Top-level testbench file. The testbench instantiates the DUT
and runs Verilog HDL tasks to generate and accept packets.
The ModelSim script to run
The Synopsys VCS script to run the testbench.
The Cadence NCSim script to run the testbench.
Hardware Design Example Components
Figure 4. 25GbE Hardware Design Example
High Level Block Diagram
The 25GbE hardware design example
includes the following components:
Client logic that coordinates the programming of the IP core and packet
ATX PLL to drive the device transceiver channel.
JTAG controller that communicates with the System Console. You communicate
with the client logic through the System Console.
Table 2. 25GbE IP Core
Hardware Design Example File Descriptions
Quartus Prime project
Quartus project settings
Top-level Verilog HDL design
Hardware design example support
Main file for accessing System Console
Generating the Design Example
Figure 5. Procedure
Figure 6. Example Design Tab in the 25GbE Parameter
Follow these steps to generate the hardware design example and testbench:
Quartus® Prime software, in the IP
Catalog (Tools > IP Catalog), select the Arria 10 target device family.
In the IP Catalog, locate and select
25G Ethernet. The New IP Variation window appears.
Specify a top-level name for your IP variation and click OK. The parameter editor adds the top-level .qsys (in
Quartus® Prime Standard Edition) or .ip (in
Quartus® Prime Pro Edition) file to the
current project automatically. If you are prompted to manually add the .qsysor .ip file to the project, click Project > Add/Remove Files in Project to add the file.
You must select a specific Arria 10 device in the Device field, or keep the default device the Quartus Prime
hardware design example overwrites the selection with the device on the target board. You
specify the target board from the menu of design example options in the Example Design tab (Step 8).
Click OK. The parameter editor
On the IP tab, specify the
parameters for your IP core variation.
On the Example Design tab, for
Example Design Files, select the Simulation option to generate the testbench, and select the
Synthesis option to generate the hardware design
example. Only Verilog HDL files are generated.
Board select the Arria 10 GX Transceiver Signal
Integrity Development Kit.
Note: Contact your Intel FPGA
representative for information about a platform suitable to run this hardware
Click the Generate Example Design
button. The Select Example Design Directory window appears.
If you wish to modify the design example directory path or name from the defaults
), browse to the new path and type the new design
example directory name (<design_example_dir>).
Refer to the KDB Answer How do I compensate for the
jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference
clock? for a workaround you should apply in the hardware_test_design directory in the .sdc file.
Note: You must consult this KDB Answer because the RX path in the 25GbE IP core includes cascaded PLLs. Therefore, the IP core clocks
might experience additional jitter in Arria 10 devices. This KDB Answer clarifies the
software releases in which the workaround is necessary.
Change to the testbench simulation directory <design_example_dir>/example_testbench.
Run the simulation script for the supported simulator of your choice. The
script compiles and runs the testbench in the simulator. Refer to the table "Steps to
Simulate the Testbench".
Analyze the results. The successful testbench sends ten packets, receives
ten packets, and displays "Testbench complete."
Table 3. Steps to Simulate the Testbench
In the command line, type vsim -do
If you prefer to simulate without bringing up the
ModelSim GUI, type vsim -c -do
Note: The ModelSim-AE and ModelSim-ASE simulators do not have the
capacity to simulate this IP core. You must use another supported ModelSim
simulator such as ModelSim SE.
In the command line, type sh
In the command line, type sh
The successful test run displays output confirming the following
Waiting for RX clock to settle
Printing PHY status
Sending 10 packets
Receiving 10 packets
Displaying "Testbench complete."
The following sample output illustrates a successful simulation test
#Ref clock is run at 625 MHz so whole numbers can used for all clock periods.
#Multiply reported frequencies by 33/32 to get actual clock frequencies.
#Waiting for RX alignment
#RX deskew locked
#RX lane alignment locked
#**Sending Packet 1...
#**Sending Packet 2...
#**Sending Packet 3...
#**Sending Packet 4...
#**Sending Packet 5...
#**Sending Packet 6...
#**Sending Packet 7...
#**Received Packet 1...
#**Sending Packet 8...
#**Received Packet 2...
#**Sending Packet 9...
#**Received Packet 3...
#**Sending Packet 10...
#**Received Packet 4...
#**Received Packet 5...
#**Received Packet 6...
#**Received Packet 7...
#**Received Packet 8...
#**Received Packet 9...
#**Received Packet 10...
#** Testbench complete.
Compiling and Configuring the Design Example in Hardware
To compile the hardware design example and configure it on your Arria 10
GT device, follow these steps:
Ensure hardware design example generation is complete.
Quartus® Prime software, open the
Quartus® Prime project <design_example_dir>/hardware_test_design/eth_ex_25g.qpf.
Before compiling, ensure you have implemented the workaround from
the KDB Answer How do I compensate for the jitter of PLL
cascading or non-dedicated clock path for Arria 10 PLL reference clock?
if relevant for your software release.
On the Processing menu, click Start
After you generate a SRAM object file .sof, follow these steps to program the hardware design example on
the Arria 10 device:
On the Tools menu,
In the Programmer, click Hardware Setup.
Select a programming device.
Select and add the Arria 10 GT board with 25G retimer to
Quartus® Prime session.
Ensure that Mode is
set to JTAG.
Select the Arria 10 device and click Add Device. The Programmer displays a block
diagram of the connections between the devices on your board.
In the row with your .sof, check the box for the .sof.
Check the box in the Program/Configure column.
Note: This design example targets the Arria
10 GT device. Please contact your Intel FPGA
representative to inquire about a platform suitable to run this hardware example
The design example demonstrates the functions of the 25GbE IP core. You can generate the design from the
Example Design tab in the 25GbE parameter editor.
To generate the design example, you must first set the parameter values for
the IP core variation you intend to generate in your end product. Generating the design
example creates a copy of the IP core; the testbench and hardware design example use this
variation as the DUT. If you do not set the parameter values for the DUT to match the
parameter values in your end product, the design example you generate does not exercise the IP
core variation you intend.
The testbench sends traffic through the IP core, exercising the
transmit side and receive side of the IP core. In the hardware design example, you
can program the IP core in internal serial loopback mode and generate traffic on the
transmit side that loops back through the receive side.
Design Example Interface Signals
The 25GbE testbench is self-contained and
does not require you to drive any input signals.
Table 4. 25GbE Hardware Design Example
Drive at 50 MHz. The intent is to
drive this from a 50 Mhz oscillator on the board.
Drive at 644.53125 MHz.
Resets the IP core. Active low. Drives
the global hard reset csr_reset_n to the IP
Transceiver PHY output serial
Transceiver PHY input serial
Status signals. The hardware
design example connects these bits to drive LEDs on the target
Table 5. 25GbE Hardware Design Example
Register Map. Lists the memory mapped register ranges for the hardware design example.
You access these registers with the reg_read and
reg_write functions in the System Console.
25GbE IP core
Arria 10 dynamic reconfiguration registers. Register base address is