Quartus® Prime software,
you can generate a programmed I/O (PIO) design example for the
Hard IP for
IP core. The generated design
example reflects the parameters that you specify. The PIO example transfers data from a host
processor to a target device. It is appropriate for low-bandwidth applications. This design
example automatically creates the files necessary to simulate and compile in the
Quartus® Prime software. You can download the compiled
design to the
Stratix® 10-GX FPGA Development Board.
To download to custom hardware, update the
Settings File (.qsf) with the correct pin assignments
Figure 1. Development Steps for the Design Example
1.1. Design Components
Figure 2. Block Diagram for the Platform Designer PIO Design Example
1.2. Directory Structure
Figure 3. Directory Structure for the Generated Design Example
1.3. Generating the Design Example
Follow these steps to generate your
Figure 4. Procedure
Quartus® Prime Pro Edition
software, create a new project (File > New Project Wizard).
Specify the Directory,
Name, and Top-Level
For Project Type,
accept the default value, Empty project.
For Add Files click
For Family, Device & Board
Settings under Family,
(GX/SX/MX/TX) and the Target Device for your design.
In the IP Catalog locate and add the
Stratix® 10Hard IP for
In the New IP Variant
dialog box, specify a name for your
On the IP Settings
tabs, specify the parameters for your IP variation.
On the Example Designs
tab, make the following selections:
For Available Example
Designs, select PIO.
For Example Design
Files, turn on the Simulation and Synthesis
If you do not need these simulation or synthesis files, leaving the
corresponding option(s) turned off significantly reduces the example
design generation time.
If you have selected a x16 configuration, for
Select simulation Root
BFM, choose the appropriate BFM:
BFM: for all configurations up to Gen3 x8. This
bus functional model (BFM) supports x16 configurations by
downtraining to x8.
For Generated HDL
Format, only Verilog is available in the current
For Target Development
Kit, select the appropriate option.
Note: If you select None, the generated design example targets the
in Step 5 above. If you intend to test the design
in hardware, make the appropriate pin assignments in the .qsf
You can also use the pin planner tool to make pin
Select Generate Example
Design to create a design example that you can simulate and
download to hardware. If you select one of the
Stratix® 10 development boards, the device on that board overwrites the
device previously selected in the
project if the devices are different. When the prompt asks you to specify the
directory for your example design,
accept the default directory, <example_design>/pcie_s10_hip_avmm_bridge_0_example_design,
or choose another directory.
Figure 5. Example Design Tab
When you generate an
Stratix® 10 example design, a file called
recommended_pinassignments_s10.txt is created in the
your .ip file when
but it is not required to be able to use the example
The prompt, Recent changes have
not been generated. Generate now?, allows you to create files
for simulation and synthesis of the
variation that you specified in Step 9
only want to work with
design example you have
Close the dummy project.
Open the example design project.
Compile the example design project to generate the .sof file for the complete example design. This
file is what you download to a board to perform hardware verification.
file contains the recommended pin assignments for all the pins in the
example design. If you select a development kit option in the pull-down menu
for Target Development Kit, the pin
assignments in the recommended_pinassignments_s10.txt
file match those that are in the .qsf file in the same
directory. If you chose NONE in the
pull-down menu, the .qsf file does not contain any pin
assignment. In this case, you can copy the pin assignments in the
recommended_pinassignments_s10.txt file to the
.qsf file. You can always change any pin assignment
in the .qsf file to satisfy your design or board
1.4. Simulating the Design Example
Figure 6. Procedure
Change to the testbench simulation directory, pcie_example_design_tb.
Run the simulation script for the simulator of your choice. Refer to the
1ns/1ps\ -NOWARN\ CSINFI"
A successful simulation ends with the following message,
"Simulation stopped due to successful completion!"
This testbench simulates up to x8 variants. It supports x16
variants by down-training to x8. To simulate all lanes of a x16 variant, you can create a
simulation model using the Platform Designer to use in an Avery
testbench. For more information refer to AN-811: Using the Avery BFM
Gen3x16 Simulation on Intel Stratix 10
The simulation reports, "Simulation stopped due to successful completion" if
no errors occur.
In addition, you can use the driver to change the value of the
The selects device by specifying the bus,
and function (BDF) numbers for the required device
The driver also allows you to enable SR-IOV for H-Tile
Complete the following steps to install the kernel
Navigate to ./software/kernel/linux
under the example design generation directory.
Change the permissions on the install, load, and unload
$ chmod 777 install load
Install the driver:
$ sudo ./install
Verify the driver installation:
$ lsmod | grep
intel_fpga_pcie_drv 17792 0
Verify that Linux recognizes the
$ lspci -d 1172:000 -v | grep
Note: If you
have changed the Vendor ID, substitute the new Vendor ID for
Vendor ID in this
Kernel driver in use:
2 Throughout this user guide, the terms word,
DWORD and QWORD have the same meaning that they have in the PCI Express Base
Specification. A word is 16 bits, a DWORD is 32 bits, and a QWORD is 64
1.7. Running the Design Example Application
Navigate to ./software/user/example under the design example
Compile the design example application:
Run the test:
You can run the
Intel® FPGA IP
link test in manual or automatic
In automatic mode, the application automatically selects
the device. The test selects the
device with the lowest BDF by
matching the Vendor ID. The test also selects the lowest available BAR.
In manual mode, the test queries you for the bus,
device, and function number and BAR.
Development Kit, you can determine the BDF by typing the following command:
$ lspci -d 1172
Here are sample transcripts for automatic and manual
Intel FPGA PCIe Link Test - Automatic Mode
0: Automatically select a device
1: Manually select a device
Opened a handle to BAR 0 of a device with BDF 0x100
0: Link test - 100 writes and reads
1: Write memory space
2: Read memory space
3: Write configuration space
4: Read configuration space
5: Change BAR
6: Change device
7: Enable SR-IOV
8: Do a link test for every enabled virtual function
belonging to the current device
9: Perform DMA
10: Quit program
Doing 100 writes and 100 reads . .
Number of write errors: 0
Number of read errors: 0
Number of DWORD mismatches: 0
Intel FPGA PCIe Link Test - Manual Mode
0: Automatically select a device
1: Manually select a device
Enter bus number:
Enter device number:
Enter function number:
BDF is 0x100
Enter BAR number (-1 for none):
Opened a handle to BAR 4 of a device with BDF 0x100
2.1. Functional Description for PIO Design Example
The testbench illustrates PIO traffic between
the host and Endpoint. The PIO design example consists of memory transfers from a host
processor to a target device.
In this example, the host processor issues
single-dword MemRd and MemWr TLPs.
The Endpoint (DUT) and PIO application (APPS) perform the necessary
translation between the PCI Express TLPs and simple Avalon-MM reads and writes to memory.
The PIO testbench includes the following components:
The Root Port BFM that drives downstream TLPs to the Endpoint.
Note: This Intel Root Port BFM
provides a simple method to do basic testing of the Application Layer logic that
interfaces to the DUT. However, the testbench and Root Port BFM are not intended to be a
substitute for a full verification environment. To thoroughly test your application,
obtain commercially available PCI Express verification IP and tools, or do your own
extensive hardware testing or both.
The Generated PCIe Endpoint Variant (DUT) with the parameters you
specified. This component drives TLP data received to the PIO application.
For more details on
this component, refer to the Intel Stratix 10 Avalon Streaming (Avalon-ST) and Single
Root I/O Virtualization (SR-IOV) Interface for PCI Express Solutions User
The PIO Application (APPS) component. Along with some additional
logic, it translates Avalon-ST data to Avalon-MM data for writes and reads to the on-chip
For variants up to Gen3 x8, an on-chip memory (MEM) stores data. Gen3 x16
variants include the memory in the APPs component.
The test program writes and reads back data to 0x00000040 in the on-chip
memory. It compares data read to the expected result. The test reports, "Simulation stopped
due to successful completion" if no errors occur.
Figure 7. Platform Designer System Contents for
Stratix® 10 PCI
Express PIO Design Example The Platform Designer generates this design
for up to Gen3 x16 variants.
This differential, serial interface is the physical link between
a Root Port and an Endpoint.
The PCIe IP Core supports 1, 2, 4, 8, or 16 lanes. Each
lane includes a TX and RX differential pair. Data is striped across all available
Table 2. 1-Bit Interface Signals In the following table <n> is the number of lanes.
Transmit output. These signals are the serial outputs
of lanes <n>-1–0.
Receive input. These signals are the serial inputs of
Refer to Pin-out Files for Intel Devices for
pin-out tables for all Intel devices in .pdf,
.txt, and .xls
Transceiver channels are arranged in groups of six. For GX devices, the
lowest six channels on the left side of the device are labeled GXB_L0, the next group is
GXB_L1, and so on. Channels on the right side of the device are labeled GXB_R0, GXB_R1,
and so on. Be sure to connect the Hard IP for PCI Express on the left side of the device
to appropriate channels on the left side of the device, as specified in the Pin-out Files for Intel Devices.
There are no control registers for the PIO design example. The PCI Express Base Specification 3.0 defines a comprehensive set of
configuration, control, and status registers to control and debug the design example.
A. Document Revision History for the Intel Stratix 10 Avalon -ST Hard IP for PCIe Design Example User Guide
A.1. Intel Stratix 10 Avalon Streaming (Avalon-ST) IP for PCIe Design Example User Guide Revision History
Added the link to the
Avalon® Streaming IP for PCIe User Guide.
Rewrote the Design Example
Description section to change the description from that of a Simple DMA
design to one for a PIO design.
Made the following changes:
Added compilation support.
Added simulation support for NCSim.
Added Linux driver for hardware example.
Revised Generating the
Design topic to create a single .ip for
instead of a complete
system design. Generating the testbench creates a design example
from the .ip .
Added web link to information on using the
Quartus Prime Pro v17.1 Stratix 10 ES Editions
Added support for Gen3 x16 Programmer Object
File (*.pof) generation
using a simplified design example.