RapidIO II Reference Design for Avalon -ST Pass-Through Interface
The RapidIO II reference design for the
Avalon®-ST) pass-through interface demonstrates
the use of the
Avalon®-ST pass-through interface to
implement NWRITE transactions using the RapidIO II IP.
You can use the
interface of the RapidIO II IP to implement RapidIO transaction types not available by our
logical layer (for example, message passing and data streaming). Additionally, you can use
this interface to implement custom functions not specified by the RapidIO protocol but
applicable to a specific system.
Avalon®-ST pass-through interface is
an optional interface that is generated when you select the Avalon-ST pass-through interface in the Transport
and Maintenance page of the RapidIO II IP parameter editor.
The RapidIO II reference design for
Avalon®-ST pass-through interface includes a traffic generator. The traffic generator initiates
NWRITE RapidIO transactions and drives the RapidIO II IP
Avalon®-ST source. The design also includes a traffic checker which sinks the
RapidIO transactions and is connected to the RapidIO II IP
Note: You need the license only if you compile the design or
target the design to your device. Alternatively, you can use the free
Intel® FPGA IP Evaluation Mode feature to evaluate
licensed Intel FPGA IP cores
in simulation and hardware before purchase.
Stratix® 10 GX FPGA Development Board
(1SG280LU3F50E3VGS1 with L-Tile transceivers1)
Perform the following steps to program the FPGA using the Programmer:
Quartus® Prime software.
Before you begin the FPGA configuration, ensure the following:
Intel® FPGA Download Cable II driver is
installed on the host computer.
The board is powered.
No other application is
the JTAG chain.
Intel® FPGA Download Cable II between your host
computer USB port and the USB port on the development board.
On the Tools menu, click
Click Auto Detect to
display the devices in the JTAG chain and select a device.
Right click and select Change
File. Then, select the srio2_s10_avst_6g_de.sof file from the project directory and
Turn on the Program/Configure option for the srio2_s10_avst_6g_de.sof file.
Click Start to download
the srio2_s10_avst_6g_de.sof file to the
FPGA. Configuration is complete when the progress bar reaches 100%.
Running the Design
When the board is set up and the FPGA is programmed, you can start
running the design:
Invoke the system console. This can be done at the
Nios® II command shell or from the
In the command window, change your directory to
system_console by typing the following command :
Execute the following commands at the system console:
The traffic generator module starts to generate RapidIO NWRITE
transactions with a default payload of 64 bytes. The default number of NWRITE
transactions is 0xFFFFFFFF (4,294,967,295 decimal). You can stop the traffic
generator by entering the stop command. The
generated RapidIO transactions are being received at the traffic checker module
since all the traffic is
back through the FMC Loopback Card.
You can view the transactions transmitted and received
counts as well as other statistics by
the link and the stats commands at the system console.
Figure 7. Link Command Execution
Figure 8. Stats Command Execution
Use Signal Tap to view the
packet exchange. This reference design includes the Signal Tap file srio2.stp
which monitors the gen_tx and the gen_rx interfaces of the RapidIO
Avalon®-ST pass-through interface. The figures
below shows the Signal Tap activity.