Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core Release Notes
Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core Release Notes
If a release note is not available for a specific IP core version, the IP core has no changes in that version. Information on the latest update releases is in the Intel Quartus Prime Design Suite Update Release Notes.
Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core v18.1
| Description | Impact | Notes |
|---|---|---|
| Added support for Auto-negotiation (AN) as defined in IEEE Standard 802.3-2015 Clause 73 and the 25G Ethernet Consortium Schedule Draft 1.6. | — | New feature. Use the AN/LT Options parameter to enable this feature. |
| Added support for Link training (LT) as defined in IEEE Standard 802.3-2015 Clauses 92 and 93 and the 25G Ethernet Consortium Schedule Draft 1.6. | — | New feature. Use the AN/LT Options parameters to enable this feature. |
| Added the dynamic control support for RS-FEC bypass capability. | — | — |
| Added support for Partial Reconfiguration. | — | — |
Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core v18.0
| Description | Impact | Notes |
|---|---|---|
|
Added support for local fault and remote fault monitoring and statistics. |
— | — |
|
Added support for optional IEEE 802.3 Clause 31 Ethernet flow control and priority-based flow control. |
— | — |
|
Added support for 322.265625 MHz PHY reference frequency. |
— | — |
|
Transceiver reconfiguration clock and control and status interface clock changed from 100 - 125 MHz to 100 - 162 MHz. |
— | — |
Added
parameters for Low Latency 100G Ethernet Intel FPGA IP core:
|
— | — |
|
Added support for hardware design example generation using Stratix 10 GX Transceiver Signal Integrity Development Kit. |
— | — |
Intel Stratix 10 Low Latency 100G Ethernet IP Core v17.1
| Description | Impact | Notes |
|---|---|---|
|
Initial release in the Intel FPGA IP Library. |
— | — |