Intel Stratix 10 GX Device Errata
Intel Stratix 10 GX Device Errata
Device Errata for the Intel Stratix 10 GX L-Tile Devices
This section lists the errata that apply to the Intel® Stratix® 10 GX L-Tile production devices. Each listed erratum has an associated status that identifies any planned fixes.
Issue | Affected Devices | Planned Fix |
---|---|---|
Device Power Supply, Core Configuration and I/O | ||
Power-on Configuration Intermittent Configuration Failures |
|
If you are using an Intel® Stratix® 10 GX 2800/2500 L-Tile device and a fix is required, move to the Intel® Stratix® 10 SX 2800/2500 L-Tile device, which is drop-in compatible |
Device Security Features |
|
Fixed in:
|
Unexpected AVST_READY Signal Behavior After Power-On-Reset (POR) |
|
No planned fix |
Transceivers | ||
On-Die Instrumentation (ODI) Support |
|
No planned fix |
PCI Express Tile Usage Restrictions |
|
Fixed in:
|
Device Power Supply, Core, Configuration and I/O
Power-on Configuration Intermittent Configuration Failures
Description
Workaround
Software workaround: Configure your FPGA with a dummy design within 18 seconds of the power up sequence completion. When the system is ready to configure, then reconfigure with the full design. Note the following considerations regarding the software workaround:
- For
Intel®
Quartus® Prime Pro Edition
versions prior to 18.0:
- You must use the same version of Intel® Quartus® Prime Pro Edition to create the first programmed bitstream and any subsequent programmed bitstreams.
- For
Intel®
Quartus® Prime Pro Edition
version 18.0:
- You can ensure compatibility of Intel® Quartus® Prime Pro Edition version 18.0 with future versions of Intel® Quartus® Prime Pro Edition by installing patch 0.13 for Microsoft* Windows* 10 or patch 0.13 for Linux* . To install patch 0.13, you must have Intel® Quartus® Prime Pro Edition version 18.0 installed. For more information, refer to the associated Knowledge Base entry.
- For
Intel®
Quartus® Prime Pro Edition
versions after 18.0:
- You can create subsequent configuration files with any Intel® Quartus® Prime Pro Edition version later than 18.0.
Status
- Intel® Stratix® 10 GX 2800 L-Tile devices
- Intel® Stratix® 10 GX 2500 L-Tile devices
Status: If you are using an Intel® Stratix® 10 GX 2800 or 2500 L-Tile device and a fix is required, move to the Intel® Stratix® 10 SX 2800/2500 L-Tile device, which is drop-in compatible.
Device Security Features
Description
If you intend to use the device security features, please contact Intel® Premier Support.
Status
- Intel® Stratix® 10 GX 2800 L-Tile devices
- Intel® Stratix® 10 GX 2500 L-Tile devices
-
Intel®
Stratix® 10 GX L-Tile devices
with AS part number.
For example: 1SG280LN2F43E2VGAS
Unexpected AVST_READY Signal Behavior After Power-On-Reset (POR)

Workaround
After the nCONFIG and nSTATUS pins are high, wait for 500 µs before you monitor the AVST_READY pin and drive the AVST_VALID pin to initiate the Avalon-ST configuration.
Status
- Intel® Stratix® 10 GX 2800 L-Tile devices
- Intel® Stratix® 10 GX 2500 L-Tile devices
Status: No planned fix.
Transceivers
On-Die Instrumentation (ODI) Support
Description
For L-Tile devices, the On-die instrumentation (ODI) is a functional diagnostic utility for remote system debug and link tuning up to 25.8 Gbps. The ODI feature does not support relative channel to channel comparisons on Intel® Stratix® 10 devices with L-Tile transceiver.
Workaround
None
Status
- Intel® Stratix® 10 GX 2800 L-Tile devices
- Intel® Stratix® 10 GX 2500 L-Tile devices
Status: No planned fix.
PCI Express Tile Usage Restrictions
Description
If any transceiver channels share a tile with active PCI Express interfaces that are Gen2 or Gen3 capable and bonded with more than two lanes (x4, x8, x16), the maximum data rate supported for the non-PCIe channels in those tiles is 6.5 Gbps. This restriction applies to both Hard IP and Soft IP implementations for the active PCI Express interfaces.
Running the neighboring transceiver channels within the same tile at data rates faster than 6.5 Gbps may result in bit errors being observed during a PCIe speed change. Transceiver channels that share a tile with active PCI Express interfaces that are only Gen1 capable are not impacted.
Workaround
- Avoid placing other transceiver instances above 6.5 Gbps data rates in the same tile as PCIe channels that are Gen2 or Gen3 capable.
- Bring up the PCIe channels first, followed by non-PCIe channels.
Status
Affects:
- Intel® Stratix® 10 GX L-Tile devices (in PIPE mode)
Status: Fixed in:
- Intel® Stratix® 10 GX L-Tile devices (in Hard IP mode)
Device Errata for the Intel Stratix 10 GX H-Tile Devices
Revision History of Intel Stratix 10 GX Device Errata
Document Version | Changes |
---|---|
2019.12.18 | Updated the following erratum: |
2018.11.20 |
|
2018.10.05 | Made the following changes:
|
2018.07.09 | Made the following changes:
|
2018.02.05 | Initial release. |