Cyclone 10 GX devices offer a range of densities that provide different amounts of device logic resources, including memory, multipliers, and adaptive logic module (ALM) logic cells. Determining the required logic density can be a challenging part of the design planning process. Devices with more logic resources can implement larger and potentially more complex designs, but generally have a higher cost. Smaller devices have lower static power utilization. Cyclone 10 GX devices support vertical migration, which provides flexibility.

Many next-generation designs use a current design as a starting point. If you have other designs that target an Intel device, you can use their resource utilization as an estimate for your new design. Review the resource utilization to find out which device density fits the design. Consider that the coding style, device architecture, and optimization options used in the Intel^® Quartus^® Prime software can significantly affect a design’s resource utilization and timing performance.

Select a device that meets your design requirements with some safety margin in case you want to add more logic later in the design cycle, upgrade, or expand your design. You might also want additional space in the device to ease design floorplan creation for an incremental or team-based design. Consider reserving resources for debugging.

Larger densities and package pin counts offer more full-duplex LVDS channels for different signaling; ensure that your device density-package combination includes enough LVDS channels. Other factors can also affect the number of I/O pins required for a design, including simultaneous switching noise (SSN) concerns, pin placement guidelines, pins used as dedicated inputs, I/O standard availability for each I/O bank, differences between I/O standards and speed for row and column I/O banks, and package migration options. For more information on choosing pin locations, refer to “Pin Connection Considerations for Board Design” and "I/O and Clock Planning"

You can compile any existing designs in the Intel^® Quartus^® Prime software to determine how many I/O pins are used. Also consider reserving I/O pins for debugging, as described in “Planning for On-Chip Debugging”.

The Cyclone^® 10 GX device family contains the following PLLs:

• Fractional PLLs—can function as fractional PLLs or integer PLLs
• I/O PLLs—can only function as integer PLLs

The fractional PLLs are located adjacent to the transceiver blocks in the HSSI banks. Each HSSI bank consists of two fractional PLLs. You can configure each fractional PLL independently in conventional integer mode.

In fractional mode, the fractional PLL can operate with third-order delta-sigma modulation. Each fractional PLL has four C counter outputs and one L counter output. The I/O PLLs are located adjacent to the hard memory controllers and LVDS serializer/deserializer (SERDES) blocks in the I/O banks. Each I/O bank consists of one I/O PLL. The I/O PLLs can operate in conventional integer mode. Each I/O PLL has nine C counter outputs.

Cyclone^® 10 GX devices have up to 6 fractional PLLs and 6 I/O PLLs in the largest densities. Cyclone^® 10 GX PLLs have different core analog structure and features support.

For more information about PLLs, refer to "PLLs and Clock Networks".

The device speed grade affects the device timing performance and timing closure, as well as power utilization. There are two speed grades available: 5 (fastest) and 6. One way to determine which speed grade your design requires is to consider the supported clock rates for specific I/O interfaces.

You can use the fastest speed grade during prototyping to reduce compilation time (because less time is spent optimizing the design to meet timing requirements), and then move to a slower speed grade for production to reduce cost if the design meets its timing requirements.

Cyclone 10 GX devices support vertical migration within the same package, which enables you to migrate to different density devices whose dedicated input pins, configuration pins, and power pins are the same for a given package. This feature allows future upgrades or changes to your design without any changes to the board layout, because you can replace the FPGA on the board with a different density Cyclone 10 GX device.

Determine whether you want the option of migrating your design to another device density. Choose your device density and package to accommodate any possible future device migration to allow flexibility when the design nears completion. You should specify any potential migration options in the Intel^® Quartus^® Prime software at the beginning of your design cycle or as soon as the device migration selection is possible in the Intel^® Quartus^® Prime software. Selecting a migration device can impact the design’s pin placement, because the Fitter ensures your design is compatible with the selected device(s). It is possible to add migration devices later in the design cycle, but it requires extra effort to check pin assignments, and can require design or board layout changes to fit into the new target device. It is easier to consider these issues early in the design cycle than at the end, when the design is near completion and ready for migration.

The Intel^® Quartus^® Prime Pin Planner highlights pins that change function in the migration device when compared to the currently selected device.

FPGA power consumption is an important design consideration and must be estimated accurately to develop an appropriate power budget to design the power supplies, voltage regulators, decouplers, heat sink, and cooling system. Power estimation and analysis have two significant planning requirements:

• Thermal planning—The cooling solution must sufficiently dissipate the heat generated by the device. In particular, the computed junction temperature must fall within normal device specifications.
• Power supply planning—The power supplies must provide adequate current to support device operation.

Power consumption in FPGA devices is dependent on the logic design. This dependence can make power estimation challenging during the early board specification and layout stages. The Intel EPE tool allows you to estimate power utilization before the design is complete by processing information about the device and the device resources that will be used in the design, as well as the operating frequency, toggle rates, and environmental considerations. You can use the tool to perform thermal analysis, including calculation of device junction temperatures derived from the ambient temperature and device power consumption. The EPE then calculates the power, current estimates, and thermal analysis for the design.

If you do not have an existing design, estimate the number of device resources used in your design and enter it manually. The EPE tool accuracy depends on your inputs and your estimation of the device resources. If this information changes (during or after your design is complete), your power estimation results are less accurate. If you have an existing design or a partially-completed compiled design, use the Generate Early Power Estimator File command in the Intel^® Quartus^® Prime software to provide input to the spreadsheet.

The EPE spreadsheet includes the Import Data macro, which parses the information in the Intel^® Quartus^® Prime generated power estimation file, or alternatively from an older version of the EPE, and transfers it into the EPE tool. If you do not want to use the macro, you can transfer the data into the EPE tool manually. You should enter additional resources to be used in the final design manually if the existing Intel^® Quartus^® Prime project represents only a portion of your full design. You can edit the inputs to the EPE tool and add additional device resources or adjust the parameters after importing the power estimation file information.

When the design is complete, the Power Analyzer tool in the Intel^® Quartus^® Prime software provides more accurate estimation of power, ensuring that thermal and supply budgets are not violated. For the most accurate power estimation, use gate-level simulation results with an output file (.vcd) output file from a third-party simulation tool.

The Cyclone^® 10 GX TSD can self-monitor the device junction temperature and be used with external circuitry for activities such as controlling air flow to the FPGA. You can bypass the ADC if you want to use an external temperature sensor, similar to the solution used for a Stratix II device or other devices.

You must include the TSD circuitry in your design if you want to use it. Ensure you make the correct external pin connections, whether you use both the ADC and TSD, or bypass the ADC and connect the sensing diode to an external temperature sensor.

For more information about these features, refer to the "Power Management in Cyclone^® 10 GX Devices" chapter in volume 1 of the Cyclone^® 10 GX Core Fabric and General Purpose I/O Handbook.

• Fast passive parallel (FPP)—A controller supplies the configuration data in a parallel manner to the Cyclone^® 10 GX FPGA. FPP is supported in an 8-bit (FPP ×8), 16-bit (FPP ×16) or 32-bit data width (FPP ×32).
• Active serial (AS)—The Cyclone^® 10 GX FPGA controls the configuration process and gets the configuration data from a quad-serial configuration (EPCQL) device. AS is supported in 1-bit (AS ×1) or 4-bit data width (AS ×4).
• Passive serial (PS)—An external host supplies the configuration data serially to the Cyclone^® 10 GX FPGA.
• Joint Test Action Group (JTAG)—Configured using the IEEE Standard 1149.1 interface with a download cable, or using MAX (MAX II, MAX V, MAX 10) devices, or microprocessor with flash memory.

You can enable any specific configuration scheme by driving the Cyclone^® 10 GX device MSEL pins to specific values on the board.

All configuration schemes use a configuration device, a download cable, or an external controller (for example, MAX^® ( MAX^® II, MAX^® V, Intel^® MAX^® 10) devices or microprocessor).

Serial configuration devices can be programmed using an Intel^® FPGA Download Cable II or Intel FPGA Ethernet Cable II download cable with the Intel^® Quartus^® Prime software through the active serial interface.

Alternatively, you can use the supported third-party programmers such as BP Microsystems and System General, or a microprocessor with the SRunner software driver. SRunner is a software driver developed for embedded serial configuration device programming that designers can customize to fit in different embedded systems.

Serial configuration devices do not directly support the JTAG interface; however, you can program the device with JTAG download cables using the Cyclone 10 GX FPGA as a bridge between the JTAG interface and the configuration device, allowing both devices to use the same JTAG interface.

The Intel^® Quartus^® Prime programmer supports configuration of the Cyclone 10 GX devices directly using JTAG interfaces with Intel programming download cables. You can download design changes directly to the device with Intel download cables, making prototyping easy and enabling you to make multiple design iterations in quick succession. You can use the same download cable to program configuration devices on the board and use JTAG debugging tools such as the Signal Tap Embedded Logic Analyzer.

If your system already contains common flash interface (CFI) flash memory, you can utilize it for Cyclone^® 10 GX device configuration storage as well. You can program CFI flash memory devices through the JTAG interface with the parallel flash loader (PFL) Intel^® FPGA IP in MAX^® II, MAX^® V and Intel^® MAX^® 10 devices. The PFL also provides the logic to control configuration from the flash memory device to the Cyclone^® 10 GX device and supports compression to reduce the size of your configuration data. Both PS and FPP configuration modes are supported using the PFL feature.

Data compression is always enabled in Cyclone 10 GX configuration, the Intel^® Quartus^® Prime software generates configuration files with compressed configuration data. This compressed file reduces the storage requirements in the configuration device or flash memory, and decreases the time required to transmit the configuration bitstream to the Cyclone 10 GX device.

Cyclone^® 10 GX devices support decompression in the FPP, AS, and PS configuration schemes. Use the Cyclone^® 10 GX decompression feature if you use the PS mode to reduce configuration time. The Cyclone^® 10 GX decompression feature is not available in the JTAG configuration scheme.

When compression is turned on, the DCLK to DATA ratio changes accordingly based on the FPP configuration scheme selected (FPP ×8, FPP ×16, or FPP ×32). To ensure a successful configuration, the configuration controller must send the DCLK that meets the DCLK to DATA ratio.

The design security feature ensures that Cyclone^® 10 GX designs are protected from copying, reverse engineering, and tampering. Cyclone^® 10 GX devices have the ability to decrypt configuration bitstreams using the AES algorithm, an industry standard encryption algorithm that is FIPS-197 certified. Cyclone^® 10 GX devices have a design security feature which utilizes a 256-bit security key.

The design security feature is available in the FPP, AS, or PS configuration schemes. The design security feature is not available in JTAG configuration scheme.

When the compression is turned on, the DCLK to DATA ratio changes accordingly based on the FPP configuration scheme selected (FPP ×8, FPP ×16, or FPP ×32). To ensure a successful configuration, the configuration controller must send the DCLK that meets the DCLK to DATA ratio.

Remote system upgrades help deliver feature enhancements and bug fixes without costly recalls, and reduces time-to-market, extends product life, and helps avoid system downtime. Cyclone^® 10 GX devices feature dedicated remote system upgrade circuitry. Soft logic (either the Nios^® embedded processor or user logic) implemented in a Cyclone^® 10 GX device can download a new configuration image from a remote location, store it in the configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle.

Cyclone^® 10 GX devices support remote system upgrades only in the single-device AS configuration scheme with EPCQL devices. You can implement remote system upgrades in conjunction with design security and real-time decompression of configuration data. To implement the remote system upgrade interface, use the altera_remote_update megafunction.

Dedicated circuitry is built into Cyclone^® 10 GX devices for a cyclic redundancy check (CRC) error detection feature that optionally checks for SEUs continuously and automatically. This allows you to confirm that the configuration data stored in a Cyclone^® 10 GX device is correct and alerts the system to a configuration error. To use the SEU mitigation features, use the appropriate megafunction for CRC error detection. Use the CRC_ERROR pin to flag errors and design your system to take appropriate action. If you do not enable the CRC error detection feature, the CRC_ERROR pin is available as a design I/O.

This section covers several configuration options that you can set in the Intel^® Quartus^® Prime software before compilation to generate configuration or programming files. Your board and system design are affected by these settings and pins, so consider them in the planning stages. Set the options on the General category of the Device and Pin Options dialog box.

Optional Configuration Pins

You can enable the following optional configuration pins:

• CLKUSR—The Enable user-supplied start-up clock (CLKUSR) option enables you to select which clock source is used for initialization, either the internal oscillator or an external clock provided on the CLKUSR pin. CLKUSR also allow you to drive the AS configuration clock (DCLK) at 100 MHz maximum. You can enable this feature in the Configuration page of the Device and Pins Option dialog box. The CLKUSR pin is also used as the clock for transceiver calibration, and is a mandatory requirement when using transceivers.
• INIT_DONE—To check if the device has completed initialization and is in user mode, you can monitor the INIT_DONE pin. Enable the INIT_DONE pin with the Enable INIT_DONE output option. During the reset stage, after the device exits POR, and during the beginning of configuration, the INIT_DONE pin is tri-stated and pulled high due to an external pull-up resistor. The INIT_DONE pin is an open-drain output and requires an external pull-up to V_CCPGM.

  Table 14.  Optional Configuration Pins Checklist

  Number	Done?	Checklist Item
  1		Plan the board design to support optional configuration pins CLKUSR and INIT_DONE, as required.

  Restart the Configuration After an Error

You can enable the Auto-restart after configuration error option so that when a configuration error occurs, the device drives nSTATUS low, which resets the device internally. The device releases its nSTATUS pin after a reset time-out period. This enables you to re-initiate the configuration cycle. The nSTATUS pin requires an external 10 kΩ pull-up resistor to V_CCPGM.

On-chip debugging is an optional step in the design flow, and different debugging tools work better for different systems and different designers. Evaluate on-chip debugging options early in your design process to ensure that your system board, Intel^® Quartus^® Prime project, and design are able to support the appropriate options. Planning can reduce time spent debugging, and eliminates design changes later to accommodate your preferred debugging methodologies. Adding debug pins might not be enough, because of internal signal accessibility and I/O pin accessibility on the device. First, select your preferred debugging tool(s).

The Intel^® Quartus^® Prime portfolio of verification tools includes the following in-system debugging features:

• Signal Probe incremental routing—Quickly routes internal signals to I/O pins without affecting the routing of the original design. Starting with a fully routed design, you can select and route signals for debugging to either previously reserved or currently unused I/O pins.
• Signal Tap Embedded Logic Analyzer—Probes the state of internal and I/O signals without the use of external equipment or extra I/O pins, while the design is running at full speed in an FPGA device. Defining custom trigger-condition logic provides greater accuracy and improves the ability to isolate problems. It does not require external probes or changes to the design files to capture the state of the internal nodes or I/O pins in the design; all captured signal data is stored in the device memory until you are ready to read and analyze the data. The Signal Tap Embedded Logic Analyzer works best for synchronous interfaces. For debugging asynchronous interfaces, consider using Signal Probe or an external logic analyzer to view the signals more accurately.
• Logic Analyzer Interface—Enables you to connect and transmit internal FPGA signals to an external logic analyzer for analysis, allowing you to take advantage of advanced features in your external logic analyzer or mixed signal oscilloscope. You can use this feature to connect a large set of internal device signals to a small number of output pins for debugging purposes and it can multiplex signals with design I/O pins if required.
• In-System Memory Content Editor—Provides read and write access to in-system FPGA memories and constants through the JTAG interface, so you can test changes to memory content and constant values in the FPGA while the device is functioning in the system.
• In-System Sources and Probes—Sets up customized register chains to drive or sample the instrumented nodes in your logic design, providing an easy way to input simple virtual stimuli and capture the current value of instrumented nodes.
• Virtual JTAG IP core—Enables you to build your own system-level debugging infrastructure, including both processor-based debugging solutions and debugging tools in the software for system-level debugging. You can instantiate the SLD_VIRTUAL_JTAG IP core directly in your HDL code to provide one or more transparent communication channels to access parts of your FPGA design using the JTAG interface of the device.

If you intend to use any of the on-chip debugging tools, plan for the tool(s) when developing the system board, Intel^® Quartus^® Prime project, and design.

The minimum current requirement for the power-on-reset (POR) supplies must be available during device power-up.

The Cyclone 10 GX device has Power-On Reset Circuitry, which keeps the device in a reset state until the power supply outputs are within the recommended operating range. The device must reach the recommended operating range within the maximum power supply ramp time. If the ramp time is not met, the device I/O pins and programming registers remain tri-stated and device configuration fails. For the Cyclone 10 GX device to exit POR, you must power the V_CCBAT power supply even if you do not use the volatile key.

In Cyclone 10 GX devices, a pin-selectable option (MSEL) allows you to select between a typical POR time setting of 4 ms or 100 ms. In both cases, you can extend the POR time by using an external component to assert the nSTATUS pin low. Extend POR time if the board cannot meet the maximum power ramp time specifications to ensure the device configures properly and enters user mode.

Cyclone 10 GX devices have power-up sequencing and power-down sequencing requirements. You should consider the power-up timing and power-down timing for each rail in order to meet the power sequencing requirements.

Intel uses GND as a reference for I/O buffer designs. Connecting the GND between boards before connecting the power supplies prevents the GND on your board from being pulled up inadvertently by a path to power through other components on your board. A pulled-up GND could otherwise cause an out-of-specification I/O voltage or current condition with the Intel device.

Cyclone^® 10 GX devices require various voltage supplies depending on your design requirements. To verify the core voltage, PLL digital power supply, programmable technology voltage, and other voltage supply levels, refer to the Cyclone^® 10 GX Device Datasheet.

Cyclone^® 10 GX devices support a wide range of industry I/O standards, such as the following V_CCIO voltage levels:

• 3.0 V (only on 3.0 V I/O bank)
• 2.5 V (only on 3.0 V I/O bank)
• 1.8 V
• 1.5 V
• 1.35 V
• 1.25 V
• 1.2 V

Voltage reference (VREF) pins serve as voltage references for certain I/O standards. The VREF pin is used mainly for a voltage bias and does not source or sink much current. The voltage can be created with a regulator or a resistor divider network.

For more information about V_CCIO voltages and VREF pins for different I/O banks, refer to “Selectable I/O Standards and Flexible I/O Banks” chapter.

The V_{REFP_ADC} pin is not a power supply pin. It provides the reference voltage for the ADC for the voltage sensor. For better voltage sensor performance, connect V_{REFP_ADC} to an external reference 1.25 V source. Connecting V_{REFP_ADC} to GND actives an on-chip reference source.

Board decoupling is important for improving overall power supply integrity while ensuring the rated device performance.

Cyclone 10 GX devices include on-die decoupling capacitors to provide high-frequency decoupling. These low-inductance capacitors suppress power noise for excellent power integrity performance, and reduce the number of external PCB decoupling capacitors, saving board space, reducing cost, and greatly simplifying PCB design.

Intel has created an easy-to-use power distribution network (PDN) design tool that optimizes the board-level PDN graphically. The purpose of the board-level PDN is to distribute power and return currents from the voltage regulating module (VRM) to the FPGA power supplies. By using the PDN tool, you can quickly arrive at an optimized PDN decoupling solution for your specific design.

For each power supply, PDN designers must choose a network of bulk and decoupling capacitors. While SPICE simulation could be used to simulate the circuit, the PDN design tool provides a fast, accurate, and interactive way to determine the right number of decoupling capacitors for optimal cost and performance trade-offs.

Plan your board design when you design a power system for PLL usage and to minimize jitter, because PLLs contain analog components embedded in a digital device.

Depending on your configuration scheme, different pull-up/pull-down resistor or signal integrity requirements might apply. Some configuration pins also have specific requirements if unused. It is very important to connect the configuration pins correctly. This section contains guidelines to address common issues.

The TCK and/or DCLK traces should produce clean signals with no overshoot, undershoot, or ringing. When designing the board, lay out the TCK and DCLK traces with the same techniques used to lay out a clock line. Any overshoot, undershoot, ringing, or other noise on the TCK signal can affect JTAG configuration. A noisy DCLK signal can affect configuration and cause a CRC error. For a chain of devices, noise on any of the TCK or DCLK pins in the chain could cause JTAG programming or configuration to fail for the entire chain.

Because JTAG configuration takes precedence over all other configuration methods, the JTAG pins should not be left floating or toggling during configuration if you do not use the JTAG interface. If you use the JTAG interface, follow the guidelines in this section.

JTAG Pin Connections

A device operating in JTAG mode uses four required pins—TDI, TDO, TMS, and TCK— and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and TRST pins have weak internal pull-up resistors. The JTAG output pin TDO and all JTAG input pins are powered by the 1.2 V, 1.5 V, and 1.8 V V_CCPGM. All JTAG pins are tri-stated during JTAG reconfiguration. Do not drive voltage lower than 1.8 V, 1.5 V, and 1.2-V V_CCPGM supply for the TDI, TMS, TCK, and TRST pins. The voltage supplies for TDI, TMS, TCK, and TRST input pins must be the same as set for the V_CCPGM supply.

If you have more than one device in the chain, connect the TDO pin of a device to the TDI pin of the next device in the chain.

Noise on the JTAG pins during configuration, user mode, or power-up can cause the device to go into an undefined state or mode.

Download Cable Operating Voltage

The operating voltage supplied to the Intel download cable by the target board through the 10-pin header determines the operating voltage level of the download cable.

JTAG pins in the Cyclone 10 GX device are powered up by V_CCPGM. In a JTAG chain containing devices with different V_CCIO levels, ensure that the V_IL max, V_IH min, and the maximum V_I specifications of the device JTAG input pins are not violated. Level shifter might be required between devices to meet the voltage specifications of the devices input pin.

JTAG Signal Buffering

You might have to add buffers to a JTAG chain, depending on the JTAG signal integrity, especially the TCK signal, because it is the JTAG clock and the fastest switching JTAG signal. Intel recommends buffering the signals at the connector because cables and board connectors tend to make bad transmission lines and introduce noise to the signals. After this initial buffer at the connector, add buffers as the chain gets longer or whenever the signals cross a board connector.

If a cable drives three or more devices, buffer the JTAG signal at the cable connector to prevent signal deterioration. This also depends on the board layout, loads, connectors, jumpers, and switches on the board. Anything added to the board that affects the inductance or capacitance of the JTAG signals increases the likelihood that a buffer should be added to the chain.

Each buffer should drive no more than eight loads for the TCK and TMS signals, which drive in parallel. If jumpers or switches are added to the path, decrease the number of loads.

JTAG configuration is always available, regardless of the MSEL pin selection. The MSEL pins are powered by the V_CCPGM power supply of the residing bank. The MSEL[2..0] pins have 25 kΩ internal pull-down resistors that are always active.

During POR and reconfiguration, the MSEL pins must be at LVTTL V_IL and V_IH levels to be considered a logic low and logic high, respectively. To avoid problems with detecting an incorrect configuration scheme, hardwire the MSEL pins to V_CCPGM or GND without pull-up or pull-down resistors. Do not drive the MSEL pins with a microprocessor or another device.

In single device configuration or JTAG programming, tie nCE low. In multi-device configuration, tie nCE low on the first device and connect its nCEO pin to the nCE pin on the next device in the chain.

Cyclone 10 GX devices support an optional chip-wide output enable that allows you to override all tri-states on the device I/Os. When this DEV_OE pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all pins behave as programmed. To use this chip-wide output enable, turn on Enable device-wide output enable (DEV_OE) in the Intel^® Quartus^® Prime software before compiling your design in the General category of the Device and Pin Options dialog box. Ensure this pin is driven to a valid logic level on your board if you enable this pin in the Intel^® Quartus^® Prime software. Do not leave this pin floating.

You can specify the state of unused pins in the Intel^® Quartus^® Prime software to allow flexibility in the board design by choosing one of the five allowable states for Reserve all unused pins on the Unused Pins category in the Device and Pin Options dialog box:

• As inputs tri-stated
• As output driving ground
• As outputs driving an unspecified signal
• As input tri-stated with bus-hold circuitry
• As input tri-stated with weak pull-up

The common setting is to set unused pins As inputs tri-stated with weak pull-up. To improve signal integrity, set the unused pins to As output driving ground. Doing this reduces inductance by creating a shorter return path and reduces noise on the neighboring I/Os. This approach should not be used if this results in many via paths causing congestion for signals under the device.

To reduce power dissipation, set clock pins and other unused I/O pins As inputs tri-stated, and tie them to ground.

If your design has high-speed signals, especially with Cyclone 10 GX device high-speed transceivers, the board design has a major impact on the signal integrity in the system.

Voltage deviation on a VREF pin can affect the threshold sensitivity for inputs.

For more information about VREF pins and I/O standards, refer to “I/O Features and Pin Connections”.

SSN is a concern when too many pins (in close proximity) change voltage levels at the same time. Noise generated by SSN can reduce the noise margin and cause incorrect switching. Although SSN is dominant on the device package, plan the board layout according to the board layout recommendations in the PCB guidelines can help with noise reduction.

Voltage-referenced I/O standards require both an V_REF and a termination voltage (V_TT). The reference voltage of the receiving device tracks the termination voltage of the transmitting device. Each voltage-referenced I/O standard requires a unique termination setup.

Although single-ended, non-voltage-referenced I/O standards do not require termination, impedance matching is necessary to reduce reflections and improve signal integrity.

Cyclone 10 GX on-chip series and parallel termination provides the convenience of no external components. Alternatively, you can use external pull-up resistors to terminate the voltage-referenced I/O standards such as SSTL and HSTL.

Differential I/O standards typically require a termination resistor between the two signals at the receiver. The termination resistor must match the differential load impedance of the signal line. Cyclone 10 GX devices provide an optional on-chip differential resistor when using LVDS.

For more information about OCT features and limitations, refer to “I/O Features and Pin Connections”.

With the Intel^® Quartus^® Prime Pin Planner GUI, you can identify I/O banks, VREF groups, and differential pin pairings to help you through the I/O planning process. Right-click in the Pin Planner spreadsheet interface and click the Pin Finder to search for specific pins. If migration devices are selected, the Pin Migration view highlights pins that change function in the migration device when compared to the currently selected device.

You have the option of importing a Microsoft Excel spreadsheet into the Intel^® Quartus^® Prime software to start the I/O planning process if you normally use a spreadsheet in your design flow. You can also export a spreadsheet compatible (.csv) file containing your I/O assignments when all pins are assigned.

When you compile your design in the Intel^® Quartus^® Prime software, I/O Assignment Analysis in the Fitter validates that the assignments meet all the device requirements and generates messages if there are any problems.

Intel^® Quartus^® Prime designers can then pass the pin location information to PCB designers. Pin assignments between the Intel^® Quartus^® Prime software and your schematic and board layout tools must match to ensure the design works correctly on the board where it is placed, especially if changes to the pin-out must be made. The Pin Planner is integrated with certain PCB design EDA tools and can read pin location changes from these tools to check the suggested changes. When you compile your design, the Intel^® Quartus^® Prime software generates the .pin file. You can use this file to verify that each pin is correctly connected in the board schematics.

In many design environments, FPGA designers want to plan top-level FPGA I/O pins early so that board designers can start developing the PCB design and layout. The FPGA device’s I/O capabilities and board layout guidelines influence pin locations and other types of assignments. In cases where the board design team specifies an FPGA pin-out, it is crucial that you verify pin locations in the FPGA place-and-route software as soon as possible to avoid board design changes.

You can use the Quartus Prime Pin Planner for I/O pin assignment planning, assignment, and validation, as described in “Making FPGA Pin Assignments”. The Quartus Prime Start I/O Assignment Analysis command checks that the pin locations and assignments are supported in the target FPGA architecture. Checks include reference voltage pin usage, pin location assignments, and mixing of I/O standards. You can use I/O Assignment Analysis to validate I/O-related assignments that you make or modify throughout the design process.

Starting FPGA pin planning early improves the confidence in early board layouts, reduces the chance of error, and improves the design’s overall time to market. You can create a preliminary pin-out for an Intel FPGA using the Intel^® Quartus^® Prime Pin Planner before the source code is designed.

Early in the design process, the system architect typically has information about the standard I/O interfaces (such as memory and bus interfaces), IP cores to be used in the design, and any other I/O-related assignments defined by system requirements.

The Pin Planner Create/Import IP Core feature interfaces with the IP catalog, and enables you to create or import custom IP cores that use I/O interfaces. Enter PLL and LVDS blocks, including options such as dynamic phase alignment (DPA), because options affect the pin placement rules. When you have entered as much I/O-related information as possible, generate a top-level design netlist file using the Create Top-Level Design File command in the Pin Planner. You can use the I/O analysis results to change pin assignments or IP parameters and repeat the checking process until the I/O interface meets your design requirements and passes the pin checks in the Intel^® Quartus^® Prime software.

When planning is complete, the preliminary pin location information can be passed to PCB designers. When the design is complete, use the reports and messages generated by the Intel^® Quartus^® Prime Fitter for the final sign-off of the pin assignments.

You can use the Quartus Prime Pin Planner for I/O pin assignment planning, assignment, and validation, as described in “Making FPGA Pin Assignments”. The Quartus Prime Start I/O Assignment Analysis command checks that the pin locations and assignments are supported in the target FPGA architecture. Checks include reference voltage pin usage, pin location assignments, and mixing of I/O standards. You can use I/O Assignment Analysis to validate I/O-related assignments that you make or modify throughout the design process.

Cyclone 10 GX I/O pins are designed for ease of use and rapid system integration, while simultaneously providing high bandwidth. Independent modular I/O banks with a common bank structure for vertical migration lend efficiency and flexibility to the high speed I/O.

This section provides guidelines related to I/O features and pin connections. It describes support for different I/O signal types and I/O standards in device I/O banks, as well as other I/O features available for your design. It also provides information about memory interfaces, pad placement guidelines, and special pin connections.

Cyclone 10 GX devices support a wide range of industry I/O standards, including single-ended, voltage-referenced single-ended, and differential I/O standards. This section provides general guidelines for selecting a signaling type.

Single-ended I/O signaling provides a simple rail-to-rail interface. Its speed is limited by the large voltage swing and noise. Single-ended I/Os do not require termination, unless reflection in the system causes undesirable effects.

Voltage-referenced signaling reduces the effects of simultaneous switching outputs (SSO) from pins changing voltage levels at the same time (for example, external memory interface data and address buses). Voltage-referenced signaling also provides an improved logic transition rate with a reduced voltage swing, and minimizes noise caused by reflection with a termination requirement. However, additional termination components are required for the reference voltage source (V_TT).

Differential signaling eliminates the interface performance barrier of single-ended and voltage-referenced signaling, with superior speed using an additional inverted closely-coupled data pair. Differential signaling also avoids the requirement for a clean reference voltage. This is possible because of a lower swing voltage and noise immunity with a common mode noise rejection capability. Considerations for this implementation include the requirements for a dedicated PLL to generate a sampling clock, and matched trace lengths to eliminate the phase difference between an inverted and non-inverted pair.

Cyclone 10 GX I/O pins are organized in pairs to support differential standards. Each I/O pin pair can support differential input or output operations, with the exception of certain clock pins that support differential input operations only. In your design source code, define just one pin to represent a differential pair, and make a pin assignment for this positive end of the pair. When you specify a differential I/O standard, the Intel^® Quartus^® Prime software automatically places the corresponding negative pin.

You can assign I/O standards and make other I/O-related settings in the Pin Planner. Be sure to use the correct dedicated pin inputs for signals such as clocks and global control signals.

For more information about, refer to “Clock and PLL Selection”.

The board must supply each bank with one V_CCIO voltage level for every VCCIO pin in a bank. Each I/O bank is powered by the VCCIO pins of that particular bank, and is independent of the VCCIO pins of other I/O banks. A single I/O bank supports output signals that are driving at the same voltage as the V_CCIO. An I/O bank can simultaneously support any number of input signals with different I/O standards.

To accommodate voltage-referenced I/O standards, each I/O bank supports multiple VREF pins feeding a common VREF bus. Set the VREF pins to the correct voltage for the I/O standards in the bank. Each I/O bank can only have a single V_CCIO voltage level and a single V_REF voltage level at a given time. If the VREF pins are not used as voltage references, they cannot be used as generic I/O pins and should be tied to V_CCIO of that same bank or GND.

An I/O bank including single-ended or differential standards can support voltage-referenced standards as long as all voltage-referenced standards use the same V_REF setting. Voltage-referenced bi-directional and output signals must drive out at the I/O bank’s V_CCIO voltage level.

Different I/O banks include different support for LVDS signaling, and the Cyclone 10 GX transceiver banks include additional support. There are two types of I/O banks, LVDS and 3 V.

The LVDS I/O bank supports differential and single-ended I/O standards up to 1.8 V. The LVDS I/O pins form pairs of true differential LVDS channels. Each pair supports a parallel input/output termination between the two pins.

The 3 V I/O bank supports only single-ended I/O standards up to 3 V. Each adjacent I/O pair also supports Differential SSTL and Differential HSTL I/O standards. The single-ended output of the 3 V I/O has the same set of features as the single-ended output of the DDR I/O IP, except the programmable pre-emphasis feature.

Refer to the Cyclone^® 10 GX I/O banks figure that shows the location of each I/O bank and what each bank supports. The figures describing the number of I/Os in each bank provide bank information specific to each device density. Refer to the section describing I/O bank restrictions for information about which I/O standards can be combined in each bank, and the section describing I/O placement guidelines for details about LVDS restrictions.

Cyclone 10 GX devices provide an efficient architecture to quickly and easily fit wide external memory interfaces with their small modular I/O banks.

The self-calibrating Intel^® Cyclone^® 10 External Memory Interfaces IP core is optimized to take advantage of the Cyclone 10 GX I/O structure. The Intel^® Cyclone^® 10 External Memory Interfaces IP core allows you to set external memory interface features and helps set up the physical interface (PHY) best suited for your system. When you use the Intel memory controller Intel^® FPGA IP functions, the Intel^® Cyclone^® 10 External Memory Interfaces IP core is instantiated automatically. If you design multiple memory interfaces into the device using Intel FPGA IP core, generate a unique interface for each instance to ensure good results instead of designing it once and instantiating it multiple times.

The data strobe DQS and data DQ pin locations are fixed in Cyclone 10 GX devices. Before you design your device pin-out, refer to the memory interface guidelines for details and important restrictions related to the connections for these and other memory-related signals.

You can implement a protocol that is not supported by Intel^® Cyclone^® 10 External Memory Interfaces IP core by using the Intel^® Cyclone^® 10 FPGA PHYLite for Parallel Interfaces.

Address and command pins within the address/command bank must follow a fixed pin-out scheme, as defined in the <variation_name>_readme.txt file generated with your IP core. The pin-out scheme varies according to the topology of the memory interface. The pin-out scheme is a hardware requirement that you must follow. Some schemes require three lanes to implement address and command pins, while others require four lanes.

Cyclone 10 GX devices allow I/O flexibility with dual-purpose configuration pins. You can use dual-purpose configuration pins as general I/Os after device configuration is complete. Select the desired setting for each of the dual-purpose pins on the Dual-Purpose Pins category of the Device and Pin Options dialog box. Depending on the configuration scheme, these pins can be reserved as regular I/O pins, as inputs that are tri-stated, as outputs that drive ground, or as outputs that drive an unspecified signal.

You can also use dedicated clock inputs, which drive the programmable clock routing networks, as general-purpose input pins if they are not used as clock pins. When you use the clock inputs as general inputs, I/O registers use ALM-based registers because the clock input pins do not include dedicated I/O registers.

The device-wide reset and clear pins are available as design I/Os if they are not enabled.

For more information, refer to “Device-Wide Output Enable Pin”.

For more information, refer to “Register Power-Up Levels and Control Signals”.

Refer to the Cyclone^® 10 GX I/O banks figure that shows the location of each I/O bank and what each bank supports. The figures describing the number of I/Os in each bank provide bank information specific to each device density. Refer to the section describing I/O bank restrictions for information about which I/O standards can be combined in each bank, and the section describing I/O placement guidelines for details about LVDS restrictions.

Consider the following checklist items and refer to the appropriate documentation in Table 3 for detailed guidelines:

The first stage in planning your clocking scheme is to determine your system clock requirements. Understand your device’s available clock resources and correspondingly plan the design clocking scheme. Consider your requirements for timing performance, and how much logic is driven by a particular clock.

Cyclone^® 10 GX devices provide dedicated low-skew and high fan-out routing networks. They are organized in a hierarchical structure that provides up to 208 unique clock domains within the device (32 GCLKs + 8 RCLKs + 144 SPCLKs + 24 LPCLKs). There are six fractional PLLs per device with four independently-programmable outputs per fractional PLL, and six I/O PLLs per device with up to nine independently programmable output per I/O PLLs. You can use 16 differential clock input pins or 36 single-ended clock input pins.

The dedicated clock pins drive the clock network directly, ensuring lower skew than other I/O pins. Use the dedicated routing network to have a predictable delay with less skew for high fan-out signals. You can also use the clock pins and clock network to drive control signals like asynchronous reset.

Connect clock inputs to specific PLLs to drive specific low-skew routing networks. Analyze the global resource availability for each PLL and the PLL availability for each clock input pin.

Use the following descriptions to help determine which clock networks are appropriate for the clock signals in your design:

• The GCLK networks can drive throughout the entire device, serving as low-skew clock sources for device logic. This clock region has the maximum delay compared to other clock regions but allows the signal to reach everywhere within the device. This option is good for routing global reset/clear signals or routing clocks throughout the device.
• The RCLK networks only pertain to the quadrant they drive into and provide the lowest clock delay and skew for logic contained within a single device quadrant.
• IOEs and internal logic can also drive GCLKs and RCLKs to create internally generated GCLKs or RCLKs and other high fan-out control signals; for example, synchronous or asynchronous clears and clock enables.
• PLLs cannot be driven by internally-generated GCLKs or RCLKs. The input clock to the PLL must come from dedicated clock input pins or from another pin/PLL-fed GCLK or RCLK.
• PCLK networks are a collection of individual clock networks driven from the periphery of the Cyclone^® 10 GX device. Clock outputs from the DPA block, PLD-transceiver interface, I/O pins, and internal logic can drive the PCLK networks. These PCLKs have higher skew compared to GCLK and RCLK networks and can be used instead of general purpose routing to drive signals into and out of the Cyclone^® 10 GX device.

If your system requires more clock or control signals than are available in the target device, consider cases where the dedicated clock resource could be spared, particularly low fan-out and low-frequency signals where clock delay and clock skew do not have a significant impact on the design performance. Use the Global Signal assignment in the Intel^® Quartus^® Prime Assignment Editor to select the type of global routing, or set the assignment to Off to specify that the signal should not use any global routing resources.

Based on your system requirements, define the required clock frequencies for your FPGA design, and the input frequencies available to the FPGA. Use these specifications to determine your PLL scheme. Use the Intel^® Quartus^® Prime parameter editor to enter your settings in FPGA IOPLL IP core, and check the results to verify whether particular features and input/output frequencies can be implemented in a particular PLL.

Cyclone 10 GX devices contain fractional PLLs in addition to I/O PLLs. You can configure fractional PLLs as integers or as enhanced fractional PLLs.

You can use I/O PLLs and fractional PLLs to reduce the number of oscillators required on the board, as well as to reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source. In addition, you can use fractional PLLs for transmit clocking for transceivers.

Cyclone 10 GX device PLLs are feature rich, and support advanced capabilities such as clock feedback modes, switchover, and dynamic phase shifting.

The default clock feedback mode is direct compensation mode.

Fractional PLLs support the following clock feedback modes:

• Direct compensation
• Feedback compensation bonding

I/O PLLs support the following clock feedback modes:

• Direct compensation
• Normal compensation
• Source synchronous compensation
• LVDS compensation
• ZDB compensation
• External feedback compensation

  Table 46.  Clock Feedback Mode Checklist

  Number	Done?	Checklist Item
  1		Ensure you select the correct PLL feedback compensation mode.

You can connect clock outputs to dedicated clock output pins or dedicated clock networks. There is no dedicated clock out pin for fractional PLL. I/O PLL can connect to a clock network or a dedicated clock pin.

Every GCLK and RCLK network has its own clock control block. The control block provides the following features:

• Clock source selection (with dynamic selection for GCLKs)
• GCLK multiplexing
• Clock power down (with static or dynamic clock enable or disable)

Use these features to select different clock input signals or power-down clock networks to reduce power consumption without using any combinational logic in your design. In Cyclone^® 10 GX devices, the clock enable signals are supported at the clock network level instead of at the PLL output counter level, so you can turn off a clock even when a PLL is not being used.

SSN is a concern when too many I/Os (in close proximity) change voltage levels at the same time. Plan the I/O and clock connections according to the recommendations.

For more information, refer to “ Cyclone^® 10 GX I/O Features” for details about the features you can use.

In a synchronous design, a clock signal triggers all events. When all of the registers’ timing requirements are met, a synchronous design behaves in a predictable and reliable manner for all process, voltage, and temperature (PVT) conditions. You can easily target synchronous designs to different device families or speed grades.

Problems with asynchronous design techniques include reliance on propagation delays in a device, incomplete timing analysis, and possible glitches. Pay particular attention to your clock signals, because they have a large effect on your design’s timing accuracy, performance, and reliability. Problems with clock signals can cause functional and timing problems in your design. Use dedicated clock pins and clock routing for best results. For clock inversion, multiplication, and division, use the device PLLs. For clock multiplexing and gating, use the dedicated clock control block or PLL clock switchover feature instead of combinational logic. If you must use internally generated clock signals, register the output of any combinational logic used as a clock signal to reduce glitches. For example, if you divide a clock using combinational logic, clock the final stage with the clock signal that was used to clock the divider circuit.

For more information, refer to “PLL Board Design Guidelines”.

Cyclone^® 10 GX devices do not support the Quartus Prime Design Assistant design-rule checking tool.

Intel provides parameterizable IP cores that are optimized for Intel device architectures. You can save design time by using IP cores instead of coding your own logic. Additionally, the Intel-provided IP cores can offer more efficient logic synthesis and device implementation. You can scale the IP core’s size and set various options with parameters. IP cores include the library of parameterized modules (LPM) and Intel device-specific IP cores. You can also take advantage of Intel and third-party IP cores and reference designs to save design time. The Intel^® Quartus^® Prime IP catalog provides a user interface to customize IP cores. You should build or change IP core parameters using the parameter editor to ensure you set all ports and parameters correctly.

For more information, refer to “IP Selection”.

The Quartus Prime IP catalog provides a user interface to customize megafunctions. You should build or change megafunction parameters using the parameter editor to ensure you set all ports and parameters correctly.

HDL coding styles can have a significant effect on the quality of results for programmable logic designs. Use Intel’s recommended coding styles to achieve optimal synthesis results. When designing memory and digital system processing (DSP) functions, understand the device architecture so you can take advantage of the dedicated logic block sizes and configurations.

Refer to your synthesis tool’s documentation for any additional tool-specific guidelines. In the Intel^® Quartus^® Prime software, you can use the HDL examples in the Language Templates available from the right-click menu in the text editor.

Cyclone 10 GX devices support an optional chip-wide reset that enables you to override all clears on all device registers, including the registers of the memory blocks (but not the memory contents itself). When this DEV_CLRn pin is driven low, all registers are cleared or reset to 0. If synthesis performs an optimization called NOT-gate-push back due to register control signals, the affected registers behave as though they are preset to a high value when DEV_CLRn is driven low. When the DEV_CLRn pin is driven high, all registers behave as programmed. To use this chip-wide reset, turn on Enable device-wide reset (DEV_CLRn) in the Intel^® Quartus^® Prime software on the General category of the Device and Pin Options dialog box before compiling your design.

Each Cyclone 10 GX logic array block (LAB) also contains dedicated logic for driving register control signals to its ALMs. Register control signals restrict how registers are packed into LABs because signals are shared within the LAB. It is important that control signals use the dedicated control signals in the device architecture, so in some cases you might be required to limit the number of different control signals used in your design.

If the clock signal is not available when reset is asserted, an asynchronous reset is typically used to reset the logic. The recommended reset architecture allows the reset signal to be asserted asynchronously and de-asserted synchronously. The source of the reset signal is then connected to the asynchronous port of the registers, which can be directly connected to global routing resources. The synchronous de-assertion allows all state machines and registers to start at the same time. It also avoids the possibility that an asynchronous reset signal is released at or near the active clock edge of a flipflop, in which case the output of the flipflop could go to a metastable unknown state.

By default, the Intel^® Quartus^® Prime integrated synthesis enables the logic option called Power-Up Don’t Care, which assumes your design does not depend on the power-up state of the device architecture and allows the software to remove registers that become stuck high. Other synthesis tools might use similar assumptions.

Designers typically use an explicit reset signal for the design that forces all registers into their appropriate values after reset but not necessarily at power-up. You can create your design such that the asynchronous reset allows the board to operate in a safe condition. You can then bring up the design with the reset active. Thus, you do not have to depend on the power-up conditions of the device.

If you force a particular power-up condition for your design, use the synthesis options available in your synthesis tool.

Some synthesis tools can also read the default or initial values for registered signals in your source code and implement this behavior in the device. For example, the Intel^® Quartus^® Prime integrated synthesis converts HDL default and initial values for registered signals into Power-Up Level settings. That way, the synthesized behavior matches the power-up state of the HDL code during a functional simulation.

Registers in the device core always power up to a low (0) logic level in the physical device architecture. If you specify a high power-up level or a non-zero reset value (often called a preset signal), synthesis tools typically use the clear signals available on the registers and perform an optimization referred to as NOT-gate push back.

If you assign a high power-up level to a register that is reset low, or assign a low power-up value to a register that is preset high, synthesis tools cannot use the NOT-gate push back optimization technique and might ignore the power-up conditions.

To implement a reset and preset signal on the same register, synthesis tools emulate the controls with logic and latches that can be prone to glitches because of the different delays between the different paths to the register. In addition, the power-up value is undefined for these registers.

The Intel^® Quartus^® Prime incremental compilation feature preserves the results and performance for unchanged logic in your design as you make changes elsewhere, allowing you to perform more design iterations and achieve timing closure more efficiently. In an incremental compilation flow, the system architect splits a large design into smaller partitions that can be designed separately. In a team design environment, team members can work on partitions independently, which simplifies the design process and reduces compilation time. Partitioning your design is optional, but these benefits are important for large Cyclone^® 10 GX designs.

If you want to take advantage of the compilation-time savings and performance preservation of Intel^® Quartus^® Prime incremental compilation, plan for an incremental compilation flow from the beginning of your design cycle. Good partition and floorplan design helps lower-level design blocks meet top-level design requirements, reducing the time spent integrating and verifying the timing of the top-level design.

Follow Intel^® ’s recommendations for creating design partitions to improve the overall quality of results. For example, registering partition I/O boundaries keeps critical timing paths inside one partition that can be optimized independently.

Plan your source code so that each design block is defined in a separate file. The software can automatically detect changes to each block separately. Use hierarchy in your design to provide more flexibility when partitioning. Keep your design logic in the leaves of the hierarchy trees; that is, the top level of the hierarchy should have very little logic, and the lower-level design blocks contain the logic.

If your design is created in multiple Intel^® Quartus^® Prime projects, it is important that the system architect provide guidance to designers of lower-level blocks to ensure that each partition uses the appropriate device resources. Because the designs are developed independently, each lower-level designer has no information about the overall design or how their partition connects with other partitions. This lack of information can lead to problems during system integration. The top-level project information, including pin locations, physical constraints, and timing requirements, should be communicated to the designers of lower-level partitions before they start their design.

The system architect can plan design partitions at the top level and use the Intel^® Quartus^® Prime software Generate Bottom-Up Design Partition Scripts option under the Project menu to automate the process of transferring top-level project information to lower-level modules.

To take full advantage of incremental compilation, you can create a design floorplan to avoid conflicts between design partitions, and to ensure that each partition is well placed relative to other partitions. When you create different location assignments for each partition, no location conflicts occur. In addition, a design floorplan helps avoid situations in which the Fitter is directed to place or replace a portion of the design in an area of the device where most resources have already been claimed. Floorplan assignments are recommended for timing-critical partitions in top-down flows.

You can use the Quartus Prime Chip Planner to create a design floorplan using Logic Lock (Standard) region assignments for each design partition. With a basic design framework for the top-level design, the floorplan editor enables you to view connections between regions, estimate physical timing delays on the chip, and move regions around the device floorplan. When you have compiled the full design, you can also view logic placement and locate areas of routing congestion to improve the floorplan assignments.

The Intel^® Quartus^® Prime software includes advanced and easy-to-use integrated synthesis that fully supports Verilog HDL and VHDL, as well as the Intel hardware description language (AHDL) and schematic design entry. You can also use industry-leading third-party EDA synthesis tools to synthesize your Verilog HDL or VHDL design, and then compile the resulting output netlist file in the Intel^® Quartus^® Prime software. Specify a third-party synthesis tool in the New Project Wizard or the EDA Tools Settings page of the Settings dialog box to use the correct Library Mapping File (.lmf) for your synthesis netlist.

Intel recommends using the most recent version of third-party synthesis tools, because tool vendors are continuously adding new features, fixing tool issues, and enhancing performance for Intel devices.

Different synthesis tools can give different results. If you want to select the best-performing tool for your application, you can experiment by synthesizing typical designs for your application and coding style and comparing the results. Be sure to perform placement and routing in the Intel^® Quartus^® Prime software to get accurate timing analysis and logic utilization results.

Your synthesis tool might offer the capability to create a Intel^® Quartus^® Prime project and pass constraints such as the EDA tool setting, device selection, and timing requirements that you specified in your synthesis project. You can use this capability to save time when setting up your Intel^® Quartus^® Prime project for placement and routing.

After compilation in the Intel^® Quartus^® Prime software, review the device resource utilization information to determine whether the future addition of extra logic or other design changes introduce fitting difficulties. If your compilation results in a no-fit error, resource utilization information is important so you can analyze the fitting problems in your design.

To determine resource usage, refer to the Flow Summary section of the Compilation Report for a percentage representing the total logic utilization, which includes an estimation of resources that cannot be used due to existing connections or logic use.

For Cyclone 10 GX devices, low logic utilization does not have the lowest ALM utilization possible. In addition, a design that is reported as close to 100% full might still have space for extra logic. The Fitter uses ALUTs in different ALMs, even when the logic can be placed within one ALM, so that it can achieve the best timing and routability results. Logic might be spread throughout the device when achieving these results. As the device fills up, the Fitter automatically searches for logic that can be placed together in one ALM.

More detailed resource information is available by viewing the reports under Resource Section in the Fitter section of the Compilation Report. The Fitter Resource Usage Summary report breaks down the logic utilization information and indicates the number of fully and partially used ALMs, and provides other resource information including the number of bits in each type of memory block. There are also reports that describe some of the optimizations that occurred during compilation. For example, if you use the Intel^® Quartus^® Prime integrated synthesis, the reports under the Optimization Results folder in the Analysis & Synthesis section provide information, including registers that were removed during synthesis. Use this report to estimate device resource utilization for a partial design to ensure that registers were not removed due to missing connections with other parts of the design.

Each stage of the compilation flow generates messages, including informational notes, warnings, and critical warnings. Review these messages to check for any design problems. Ensure that you understand the significance of any warning messages, and make changes to the design or settings if required. In the Intel^® Quartus^® Prime user interface, you can use the Message window tabs to look at only certain types of messages, and you can suppress messages if you have determined that they do not require any action from you.

In an FPGA design flow, accurate timing constraints allow timing-driven synthesis software and place-and-route software to obtain optimal results. Timing constraints are critical to ensure designs meet their timing requirements, which represent actual design requirements that must be met for the device to operate correctly. The Intel^® Quartus^® Prime software optimizes and analyzes your design using different timing models for each device speed grade, so you must perform timing analysis for the correct speed grade. The final programmed device might not operate as expected if the timing paths are not fully constrained, analyzed, and verified to meet requirements.

The Intel^® Quartus^® Prime software includes the Intel^® Quartus^® Prime Timing Analyzer, a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design. It supports the industry standard Synopsys Design Constraints (SDC) format timing constraints, and has an easy-to-use GUI with interactive timing reports. It is ideal for constraining high-speed source-synchronous interfaces and clock multiplexing design structures.

The software also supports static timing analysis in the industry-standard Synopsys PrimeTime software. Specify the tool in the New Project Wizard or the EDA Tools Settings page of the Settings dialog box to generate the required timing netlist.

A comprehensive static timing analysis includes analysis of register to register, I/O, and asynchronous reset paths. It is important to specify the frequencies and relationships for all clocks in your design. Use input and output delay constraints to specify external device or board timing parameters. Specify accurate timing requirements for external interfacing components to reflect the exact system intent.

The Timing Analyzer performs static timing analysis on the entire system, using data required times, data arrival times, and clock arrival times to verify circuit performance and detect possible timing violations. It determines the timing relationships that must be met for the design to correctly function.

You can use the report_datasheet command to generate a datasheet report that summarizes the I/O timing characteristics of the entire design.

The assignments and settings described in this section are important for large designs such as those in Cyclone 10 GX devices.

When the Optimize multi-corner timing option is on, the design is optimized to meet its timing requirements at all timing process corners and operating conditions. Therefore, turning on this option helps create a design implementation that is more robust across PVT variations.

In your Timing Analyzer .sdc constraints file, apply the recommended constraints to your design.

This section highlights some of the features offered in the Intel^® Quartus^® Prime software to help optimize area (or resource utilization) and timing performance. If the timing analysis reports that your design requirements were not met, you must make changes to your design or settings and recompile the design to achieve timing closure. If your compilation results in no-fit messages, you must make changes to get successful placement and routing.

You can use the Early Timing Estimation feature to estimate your design’s timing results before the software performs full placement and routing. On the Processing menu, point to Start and click Start Early Timing Estimate to generate initial compilation results after you have run analysis and synthesis.

Physical synthesis optimizations make placement-specific changes to the netlist that improve results for a specific Intel device. You can optimize for performance and fitting in the Physical Synthesis Optimizations page of the Settings dialog box. The options in the Physical Synthesis Optimizations page typically increase compilation time significantly but can provide significant improvements to the quality of results with push-button optimizations. If you turn on these options, ensure that they do improve the results for your design. If you do not require these options to meet your design timing requirements, turn off the options to reduce the compilation time.

The Design Space Explorer (DSE) is a utility that automates the process of finding the optimal collection of the Intel^® Quartus^® Prime software settings for your design. The Search for Best Performance and Search for Best Area options under Exploration Settings use a predefined exploration space to target design performance or area improvements with multiple compilations. You can also set the Optimization Goal to Optimize for Speed or Optimize for Area using the Advanced tab in the DSE window.

The Optimization Advisors provide guidance in making settings that optimize your design. On the Tools menu, point to Advisors and click Resource Optimization Advisor or Timing Optimization Advisor. Evaluate the options and choose the settings that best suit your requirements.

Use the incremental compilation feature to preserve logic in unchanged parts of your design, preserve timing performance, and reach timing closure more efficiently. You can speed up design iteration time by an average of 60% when making changes to the design with the incremental compilation feature.

The Intel^® Quartus^® Prime software can run some algorithms in parallel to take advantage of multiple processors and reduce compilation time when more than one processor is available to compile the design. Set the Parallel compilation option on the Compilation Process Settings page of the Settings dialog box, or change the default setting in the Options dialog box in the Processing page from the Tools menu.

The Compilation Time Advisor provides guidance in making settings that reduce your design compilation time. On the Tools menu, point to Advisors and click Compilation Time Advisor. Using some of these techniques to reduce compilation time can reduce the overall quality of results.

The Intel^® Quartus^® Prime software supports both RTL and gate level functional simulations. Perform functional simulation at the beginning of your design flow to check the design functionality or logical behavior of each design block. You do not have to fully compile your design; you can generate a functional simulation netlist that does not contain timing information.

Intel provides the ModelSim* - Intel^® FPGA Edition FPGA Starter Edition and offers the higher-performance ModelSim^® - Intel FPGA Edition, which enable you to take advantage of advanced testbench capabilities and other features. In addition, the Intel^® Quartus^® Prime EDA Netlist Writer can generate timing netlist files to support other third-party simulation tools such as Synopsys VCS, Cadence NC-Sim, and Aldec Active-HDL. Specify your simulation tool in the EDA Tools Settings page of the Settings dialog box to generate the appropriate output simulation netlist. The software can also generate scripts to help you setup libraries in your tool with NativeLink integration.

If you use a third-party simulation tool, use the software version that is supported with your Intel^® Quartus^® Prime software version. The Intel^® Quartus^® Prime Software Release Notes list the version of each simulation tool that is officially supported with that particular version of the Intel^® Quartus^® Prime software. Use the model libraries provided with your Intel^® Quartus^® Prime software version, because libraries can change between versions, which might cause a mismatch with your simulation netlist. To create a testbench, on the Processing menu, point to Start and click Start Testbench Template Writer.

The Intel^® Quartus^® Prime software supports some formal verification flows. Using a formal verification flow can impact performance results because it requires that certain logic optimizations be turned off, such as register retiming, and forces hierarchy blocks to be preserved, which can restrict optimization. There are other restrictions that can also limit your design; consult the documentation for details.

If formal verification is important to your design, it is easier to plan for limitations and restrictions in the beginning than to make changes later in the design flow.

The " Intel^® Quartus^® Prime Pro Edition Software and Device Support Release Notes" list the version of each formal verification tool that is officially supported with that particular version of the Intel^® Quartus^® Prime software. Specify your formal verification tool in the EDA Tools Settings page of the Settings dialog box to generate the appropriate output netlist.

Before design completion, estimate power consumption using the EPE spreadsheet. After compiling your design, analyze the power consumption and heat dissipation with the Intel^® Quartus^® Prime Power Analyzer to ensure the design has not violated power supply and thermal budgets.

You must compile a design (to provide information about design resources, placement and routing, and I/O standards) and provide signal activity data (toggle rates and static probabilities) to use the Power Analyzer. You can derive signal activity data from simulation results or a user-defined default toggle rate and vectorless estimation. The signal activities used for analysis must be representative of the actual operating behavior. For the most accurate power estimation, use gate-level simulation results with a .vcd output file from a third-party simulation tool. The simulation activity should include typical input vectors over a realistic time period and not the corner cases often used during functional verification. Use the recommended simulator settings (such as glitch filtering) to ensure good results.

You must also specify operating conditions, including the core voltage, device power characteristics, ambient and junction temperature, cooling solution, and the board thermal model. Select the appropriate settings on the Operating Settings and Conditions page in the Settings dialog box.

To calculate the dynamic, static, and I/O thermal power consumption, on the Processing menu, click Power Analyzer Tool. The tool also provides a summary of the signal activities used for analysis and a confidence metric that reflects the overall quality of the data sources for signal activities.

The report is a power estimate based on the data provided, and is not a power specification. Always refer to the datasheet for the power specification of your device.

Cyclone 10 GX devices utilize advanced process and circuit techniques, along with major circuit and architecture innovations, to minimize power and deliver high performance. The Programmable Power Technology feature enables every programmable LAB, DSP block, and memory block to deliver either high speed or low power, depending on your design requirements. The Intel^® Quartus^® Prime software automatically takes advantage of the excess slack found on non-critical design paths to minimize power consumption while maintaining high performance for critical paths.

To reduce dynamic power consumption in Cyclone 10 GX devices, you can use various design and software techniques to optimize your design.

Power optimization in the Intel^® Quartus^® Prime software depends on accurate power analysis results. Use the guidelines in the previous section to ensure the software optimizes the power utilization correctly for the design’s operating behavior and conditions.

This section lists several design techniques that can reduce power consumption. The results of these techniques are different from design to design.

Cyclone^® 10 GX devices also offer "Programmable Power Technology" power saving technique.

If your design includes many critical timing paths that require the high-performance mode, you might be able to reduce power consumption by using a faster speed grade device if available. With a faster device, the software might be able to set more device tiles to use the low-power mode.

Clocks represent a significant portion of dynamic power consumption, because of their high switching activity and long paths. The Intel^® Quartus^® Prime software automatically optimizes clock routing power by enabling only the portions of a clock network that are required to feed downstream registers. You can also use clock control features to dynamically enable or disable the clock network. When a clock network is powered down, all the logic fed by that clock network does not toggle, thereby reducing the overall power consumption of the device.

To reduce LAB-wide clock power consumption without disabling the entire clock tree, use the LAB-wide clock enable signal to gate the LAB-wide clock. The Intel^® Quartus^® Prime software automatically promotes register-level clock enable signals to the LAB level.

The dynamic power consumed in the I/O buffer is proportional to the total load capacitance; therefore, lower capacitance reduces power consumption.

Non-terminated I/O standards such as LVTTL and LVCMOS have a rail to-rail output swing equal to the V_CCIO supply voltage. Because dynamic power is proportional to the square of the voltage, use lower voltage I/O standards to reduce dynamic power. These I/O standards consume little static power.

Because dynamic power is also proportional to the output transition frequency, use resistively-terminated I/O standards such as SSTL for high-frequency applications. The output load voltage swings by an amount smaller than the V_CCIO around a bias point; therefore, dynamic power is lower than for non-terminated I/O under similar conditions.

Resistively-terminated I/O standards dissipate significant static power because current is constantly driven into the termination network. Use the lowest drive strength that meets your speed and waveform requirements to minimize static power when using resistively terminated I/O standards.

The power used by external devices is not included in the EPE calculations, so be sure to include it separately in your system power calculations.

The Intel^® Quartus^® Prime software offers power-optimized synthesis and fitting to reduce core dynamic power. Power-driven compilation works in conjunction with Programmable Power Technology in Cyclone 10 GX silicon.

Optimizing your design for area also saves power because fewer logic blocks are used; therefore, there is typically less switching activity. Improving your design source code to optimize for performance can also reduce power usage because more of the design might be placed using low power tiles instead of requiring the high-performance mode. You can use the DSE and Power Optimization Advisor to provide additional suggestions to reduce power.

The Intel^® Quartus^® Prime software includes the Power Optimization Advisor, which provides specific power optimization advice and recommendations based on the current design project settings and assignments. On the Tools menu, point to Advisors and click Power Optimization Advisor. After making any of the recommended changes, recompile your design and run the Power Analyzer to check the change in your power results.

Each transceiver bank includes six transceiver channels in all devices except for the devices with 10 transceiver channels.

The figures below show the transceiver bank architecture with the phase locked loop (PLL) and clock generation block (CGB) resources available in each bank.

The transceiver channels perform all the required PHY layer functions between the FPGA fabric and the physical medium. The high speed clock required by the transceiver channels is generated by the transceiver PLLs. The master and local clock generation blocks (CGBs) provide the necessary high speed serial and low speed parallel clocks to drive the non-bonded and bonded channels in the transceiver bank.

A PMA is the transceiver's electrical interface to the physical medium. The transceiver PMA consists of standard blocks such as:

• serializer/deserializer (SERDES)
• clock and data recovery PLL
• analog front end transmit drivers
• analog front end receive buffers

The PCS can be bypassed with a PCS-Direct configuration. Both the PMA and PCS blocks are fed by multiple clock networks driven by high performance PLLs. In PCS-Direct configuration, the data flow is through the PCS block, but all the internal PCS blocks are bypassed. In this mode, the PCS functionality is implemented in the FPGA fabric.

Cyclone^® 10 GX transceiver channels have three types of PCS blocks that together support continuous data rates between of 1.0 Gbps to 12.5 Gbps

• Advanced Transmit (ATX) PLL
• Fractional PLL (fPLL)
• Channel PLL / Clock Multiplier Unit (CMU) PLL.

These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB) drive the transceiver channels.

• Master CGB
• Local CGB

Transceiver banks with six transceiver channels have two master CGBs. Master CGB1 is located at the top of the transceiver bank and master CGB0 is located at the bottom of the transceiver bank. Transceiver banks with three channels have only one master CGB. The master CGB divides and distributes bonded clocks to a bonded channel group. It also distributes non-bonded clocks to non-bonded channels across the x6/xN clock network.

Each transceiver channel has a local CGB. The local CGB is used for dividing and distributing non-bonded clocks to its own PCS and PMA blocks.

The calibration engine calibrates the analog portion of the transceiver to allow both the transmitter and receiver to operate at maximum performance. Each Cyclone^® 10 GX device contains two calibration engines and each engine resides on either side of the device. A hard Nios^® II processor controls the calibration flow.

The CLKUSR pin clocks the calibration engine. All transceiver reference clocks and the CLKUSR clock must be free running and stable upon device power-up to successfully complete the calibration process and for optimal transceiver performance.