AN 839: Design Block Reuse Tutorial: for Intel Arria 10 FPGA Development Board

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AN-839 | 2019.07.26

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Updated for:
Intel® Quartus® Prime Design Suite 19.2

1. AN 839: Design Block Reuse Tutorial for Intel Arria 10 FPGA Development Board

This tutorial demonstrates how to reuse design blocks in Intel^® Quartus^® Prime Pro Edition projects. The Intel^® Quartus^® Prime Pro Edition software supports block-based design flows, also known as modular or hierarchical design flows. These flows enable preservation of design blocks (or logic that comprises a hierarchical design instance) within a project, as well as reuse of design blocks in other projects.

You can reuse design blocks with the same periphery interface, share a synthesized design block with another designer, or replicate placed and routed IP in another project. Design, implement, and verify core or periphery blocks once, and then reuse those blocks multiple times across different projects that use the same device. In design block reuse flows, you assign a hierarchical instance of logic as a design partition. You can then preserve, export, and reuse the partition according to the following reuse flows:

Core Partition Reuse—allows reuse of a synthesized or final snapshot of a core logic design partition (LUTs, flip-flops, M20K memory, and DSP blocks) in another project.
Root Partition Reuse—allows reuse of the synthesized or final snapshot of the root partition. The root partition includes periphery resources (including I/O, HSSIO, PCIe, PLLs), as well as any associated core resources, while reserving a region for subsequent development.

1.1. Tutorial Overview

This tutorial describes the core and root partition reuse flows for both the Developer and the Consumer roles. At a high level, the core and root partition reuse flows are similar. Both flows preserve and reuse a design partition as a .qdb file. The Developer defines, compiles, and preserves the block in the Developer project, and the Consumer reuses the block, along with their own logic, in one or more Consumer projects.

Reusing Core Partitions

Core partition reuse allows a Developer to create, preserve, and export a partition for reuse. The Developer exports the core partition as a .qdb, and then a Consumer can reuse that core partition in another project. The core partition can include only core resources, such as LUTs, flip-flops, M20K memory, and DSP blocks. To use this flow you assign the .qdb to an instance in the Consumer project.

Figure 1. Core Partition Reuse Example

Reusing Root Partitions

Root partition reuse enables you to export a synthesized or final snapshot of the device periphery and associated core logic. To export and reuse periphery elements, you export the root partition. The periphery resources include all the hardened IP in the device periphery (such as general purpose I/O, PLLs, high-speed transceivers, PCIe, and external memory interfaces), as well as associated core logic. The Developer also reserves a region for core logic development by the Consumer. The Developer defines this reserved region with a partition. The Developer defines at least the module's port connections as a black box file.

Figure 2. Root Partition Reuse Example

When you export the synthesized or final partition as a .qdb, the .qdb preserves the results of that compilation stage. When you subsequently reuse that partition in another project, the Compiler reuses the previous compilation results from the .qdb for that partition, thereby leveraging the previous design efforts of the Developer.

The tutorial includes the following modules:

Core Partition Reuse—Developer Tutorial
Core Partition Reuse—Consumer Tutorial
Root Partition Reuse—Developer Tutorial
Root Partition Reuse—Consumer Tutorial
(Optional) Step 8: Device Programming

1.2. Tutorial Software and Hardware

This tutorial assumes a basic understanding of Verilog HDL design and the Intel^® Quartus^® Prime Pro Edition design flow. The steps in this tutorial correspond with use of the following Intel^® software and hardware.

Linux installation of Intel^® Quartus^® Prime Pro Edition software version 18.1, with Intel^® Arria^® 10 device support.
The Intel^® Arria^® 10GX FPGA Development Kit.

Note: You can also adapt this tutorial for Windows and other software or hardware configurations.

1.3. Tutorial Files

This tutorial includes a design example organized into directories that correspond with the flow (Core or Root partition reuse) and role (Developer or Consumer).

Tutorial Directory Structure

The Completed directories contain the final versions of all the files required to complete that tutorial module. You can use the files in the Completed directories to bypass tutorial steps, or skip to the final step of the tutorial module. The Script directories contain scripts to automatically run the flows that each module describes.

Follow these steps to use the design example files with this tutorial:

Locate and download the design reuse tutorial design files at:
https://www.intel.com/content/dam/www/programmable/us/en/others/literature/an/q181_design_block_reuse_tutorial.zip
Unzip the q181_design_block_reuse_tutorial.zip file.

The .zip includes the following subdirectories that extract to the q181_design_block_reuse_tutorial directory.

Table 1. Tutorial Design Example Files
Directory Name	Description
Core_Partition_Reuse/Developer/	Contains the source files for completing the core partition reuse Developer tutorial steps.
Core_Partition_Reuse/Consumer/	Contains the source files for completing the core partition reuse Consumer tutorial steps.
Core_Partition_Reuse/Completed/	Contains final versions of all the files to complete the core partition reuse tutorial module.
Root_Partition_Reuse/Developer/	Contains the files for completing the root partition reuse Developer tutorial steps.
Root_Partition_Reuse/Consumer/	Contains the files for completing the root partition reuse Consumer tutorial steps.
Root_Partition_Reuse/Completed/	Contains final versions of all the files to complete the core partition reuse tutorial step.
/Developer/Scripts /Consumer/Scripts	The Consumer and Developer directories contain Scripts subdirectories that include the following helpful scripts: Scripts/run.sh—automatically completes all steps for that flow. Scripts/restore.sh—restores the tutorial files for that flow to default state. You must run these scripts from the project directory in the form of Scripts/run.sh. The Intel^® Quartus^® Prime Pro Edition executable must by in your system path.

1.4. Core Partition Reuse—Developer Tutorial

Follow the steps in this tutorial module to develop a core partition for export and reuse in a Consumer project.

Process Description

As an IP Developer, you define, place, route, and eventually export a block of code within a partition. You then pass the exported .qdb to a Consumer.

Figure 3. Core Partition Reuse Flow

Reuse of the core partition also requires that you provide a black box file to the Consumer. The black box file defines the ports and port interface types for synthesis in the Consumer project. The Compiler ignores any further RTL that you include in the black box file.

You add the black box file to the Consumer project as a source file. You assign the exported .qdb file to a partition in the Consumer design. The .qdb file contains all of the information from the Developer's compilation snapshot. The Consumer can then reuse these compilation results in their project. The synthesis snapshot includes only synthesis results. The final snapshot includes synthesis, placement, and routing results.

Completed Tutorial Files

The Core_Partition_Reuse/Completed/Developer/ tutorial directory contains the completed files for this tutorial module.

Tutorial Steps

This tutorial module includes the following steps:

Step 1: Define a Core Partition
Step 2: Compile and Export the Core Partition
Step 3: Create the Black Box File
Step 4: Copy Files to Consumer Project
Step 5: Hardware Verification (Optional)

Command-Line Alternative Step

You can skip Step 1: Define a Core Partition and Step 2: Compile and Export the Core Partition in this tutorial module by adding the following line to the Intel^® Quartus^® Prime Settings file (.qsf), and then running the Core_Partition_Reuse/Developer/Script/run.sh script.

set_instance_assignment -name PARTITION blinking_led -to \
     u_blinking_led -entity top

1.4.1. Step 1: Define a Core Partition

Follow these steps to open the top.qpf tutorial project in the Intel^® Quartus^® Prime Pro Edition software, run design synthesis, and define a design partition for core logic.

In the Intel^® Quartus^® Prime Pro Edition software, click File > Open Project and open the /Core_Partition_Reuse/Developer/top.qpf project file.
To synthesize the design, click Analysis & Synthesis on the Compilation Dashboard. The Compilation dashboard displays a check mark when synthesis is complete.

Figure 4. Compilation Dashboard
In the Project Navigator, right-click u_blinking_led in the Hierarchy tab, point to Design Partition, and select the Default partition Type. A design partition icon appears next to each instance you assign.

Figure 5. Set as Design Partition
To view and edit all design partitions in the project, click Assignments > Design Partitions Window. You can also define new partitions in this window, or specify automatic export of a partition following compilation.

Figure 6. Design Partitions Window

1.4.2. Step 2: Compile and Export the Core Partition

Follow this step to run full compilation and manually export a final snapshot of your core partition. Alternatively, you can automate partition export each time you run compilation, as Step 1: Create a Reserved Core Partition describes later in this tutorial.

To run full compilation of the design and create the final snapshot, click Compile Design on the Compilation Dashboard. Check marks indicate when each stage of compilation is complete.

Figure 7. Full Compilation Complete
To export the core partition, click Project > Export Design Partition. Select blinking_led for the Partition name, and the final compilation Snapshot for export.

Figure 8. Export Design Partition Dialog Box

Note: Intel^® FPGA IP targeting Intel^® Arria^® 10 devices do not use entity-bound .sdc files by default. To use this option for Intel^® Arria^® 10 devices, you must first bind the .sdc file to the entity in the .qsf. Refer to "Using Entity-bound SDC Files," in Intel^® Quartus^® Prime Pro Edition User Guide: Timing Analyzer.
Confirm blinking_led.qdb as the Partition Database File name, and then click OK. The final blinking_led.qdb that you export preserves the complete placement and routing information from the original project when you reuse the block in a Consumer project.

1.4.3. Step 3: Create the Black Box File

Integrating a core partition .qdb into another project requires that you add a supporting black box file to the Consumer project. The black box file defines the ports and port interface types for the block that you reuse in the Consumer project. Follow these steps to create a black box port definitions file for the blinking_led partition.

To create a new text file, click File > New, select SystemVerilog HDL File under Design Files, and then click OK. Create a file that contains only the port definitions for the partition you export. These are the same port definitions that the blinking_led.sv file specifies:
```
module blinking_led (
    output [3:0] value,
    input      clock
    );

endmodule
```
Save the black box file as blinking_led_bb.sv. When saving this file, disable the option to Add file to current project.

Figure 9. Disable Add File to Current Project

1.4.4. Step 4: Copy Files to Consumer Project

After exporting the core partition and creating the black box file, you copy the files to the Consumer project directory for subsequent use in the Core Partition Reuse—Consumer Tutorial.

Manually copy the blinking_led.qdb and blinking_led_bb.sv files to the Core_Partition_Reuse/Consumer/ directory.

Note: There is no requirement to pass an .sdc file for the partition to the Consumer project, because the .sdc does not influence the logic, placement, or routing of a finalized partition in the Consumer project. However, the Developer can optionally provide an .sdc file for the partition to the Consumer project for timing analysis of the partition after complete integration with the Consumer design.

In the Core Partition Reuse—Consumer Tutorial, you integrate the blinking_led.qdb and blinking_led_bb.sv files into the Consumer project.

1.4.5. Step 5: Hardware Verification (Optional)

You can now optionally verify the results of the Core Partition Reuse—Developer tutorial module in hardware by completing (Optional) Step 8: Device Programming.

After completing this tutorial module, LEDs D6-D3 map to the blinking_led core, and LEDs D10-D7 map to the top-level design. After you configure the FPGA with the SRAM Object File (.sof), the blinking_led core flashes red LEDs in a binary counting order. The top-level design does not illuminate any LEDs.

Figure 10. Illumination of LEDs After Core Partition Reuse—Developer Tutorial Module

1.5. Core Partition Reuse—Consumer Tutorial

Follow the steps in this tutorial module to reuse a core partition in a Consumer project.

Process Description

As a core partition Consumer, you receive the final core partition that the Developer provides. The Consumer adds the black box file and assigns the .qdb in the Consumer project. Because the exported .qdb includes compiled netlist information, the Consumer project must target the same FPGA device part number, and use the same Intel^® Quartus^® Prime version as the Developer project.

Figure 11. File Exchange Between Developer and Consumer

The Consumer must specify all signals and port directions, as well as any Verilog HDL parameters or VHDL generics. The Developer can optionally include an .sdc for the partition to verify the partition timing results after full integration in the Consumer project.

Completed Tutorial Files

The Core_Partition_Reuse/Completed/Consumer/ tutorial directory contains the completed files for this tutorial module.

Tutorial Module Steps

This tutorial module includes the following steps:

Step 1: Add Files and Run Synthesis
Step 2: Create a Partition for blinking_led
Step 3: Compile the Design
Step 4: Hardware Verification (Optional)

Command-Line Alternative Step

You can skip Step 1: Add Files and Run Synthesis through Step 3: Compile the Design in this tutorial module by adding following lines to the .qsf, and then running the Core_Partition_Reuse/Consumer/Script/run.sh script:

#Create the partition
set_instance_assignment -name PARTITION blinking_led \
     -to u_blinking_led -entity top
#Assign the .qdb file to the partition
set_instance_assignment -name QDB_FILE_PARTITION blinking_led.qdb \
     -to u_blinking_led -entity top
#Add the BB file to the file list
set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_bb.sv

1.5.1. Step 1: Add Files and Run Synthesis

To add the core partition to the Consumer project, add the black box as a source file in the project, and assign the core partition .qdb to an instance in the Design Partitions Window, as the following steps describe:

In the Intel^® Quartus^® Prime Pro Edition software, click File > Open Project and open the /Core_Partition_Reuse/Consumer/top.qpf project file.
To add files to the project, click Project > Add/Remove Files in Project.
On the Files pane, click the browse (...) button near File name to locate and select the /Core_Partition_Reuse/Consumer/blinking_led_bb.sv black box file. Click Open, and then click OK. The file is now a source file in the project.

Figure 12. Adding Black Box File to the Project
To synthesize the design, click Analysis & Synthesis on the Compilation Dashboard. The Compilation dashboard displays a check mark when synthesis is complete.

1.5.2. Step 2: Create a Partition for blinking_led

Follow these steps to create a partition for blinking_led.

In the Project Navigator, right-click u_blinking_led in the Hierarchy tab, point to Design Partition, and select the Default partition Type.
To assign the blinking_led.qdb to the partition, click Assignments > Design Partitions Window.
Double-click in the Partition Database File cell, and then click browse (...) to select the blinking_led.qdb from the Developer project.

Figure 13. Assigning QDB in Design Partitions Window

1.5.3. Step 3: Compile the Design

After creating a partition for blinking_led, you are ready to run a full compilation of the design.

To run a full compilation, click Compile Design on the Compilation Dashboard.
View the results of compilation in the Compilation Report.

After you complete these steps, the project uses the blinking_led.qdb file as a source, in place of the RTL. The placement and routing from the previous partition export is preserved. The logic in the top-level design is synthesized, placed, and routed, while preserving the placed and routed blinking_led.qdb partition.

1.5.4. Step 4: Hardware Verification (Optional)

You can now optionally verify the results of the Core Partition Reuse—Consumer Tutorial module in hardware by completing (Optional) Step 8: Device Programming.

After completing this tutorial module, LEDs D6-D3 map to the blinking_led core, and LEDs D10-D7 map to the top-level design. After configuring the FPGA, the blinking_led core flashes red LEDs in a binary counting order. The top-level design shows a shifting bit in green.

Figure 14. Illumination of LEDs After Core Partition Reuse—Consumer Tutorial Module

1.6. Root Partition Reuse—Developer Tutorial

Follow the steps in this tutorial module to develop a root partition for reuse.

Process Description

As a root partition Developer, you create, compile, and eventually export a top-level root partition that includes the device periphery. The Developer also reserves a core partition for subsequent development of core logic in the Consumer project.

Figure 15. Root Partition Reuse Flow

The Developer fully compiles this design and then provides the root partition .qdb and an .sdc file for the top-level design.

The following figure shows the Developer's root partition with a placeholder for the blinking_led module. For this tutorial, blinking_led simply ties the outputs to 4’b1111 to turn off the LEDs.

Figure 16. RTL View of Developer's Root Partition

Completed Tutorial Files

The Root_Partition_Reuse/Completed/Developer/ tutorial directory contains the completed files for this tutorial module.

Tutorial Module Steps

This tutorial module includes the following steps:

Step 1: Create a Reserved Core Partition
Step 2: Define a Logic Lock Region
Step 3: Compile and Export the Root Partition
Step 4: Copy Files to Consumer Project
Step 5: Hardware Verification (Optional)

Command-Line Alternative Tutorial Step

You can skip Step 1: Create a Reserved Core Partition through Step 3: Compile and Export the Root Partition in this tutorial module by adding the following lines to the .qsf, and then running the Root_Partition_Reuse/Developer/Script/run.sh script.

set_instance_assignment -name PARTITION blinking_led \
     -to u_blinking_led -entity top
set_instance_assignment -name PERIPHERY_REUSE_CORE ON -to \
     u_blinking_led -entity top
set_instance_assignment -name PLACE_REGION \
     "X63 Y102 X185 Y162" -to u_blinking_led
set_instance_assignment -name RESERVE_PLACE_REGION ON -to \
     u_blinking_led
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON \
     -to u_blinking_led
set_instance_assignment -name REGION_NAME u_blinking_led -to \
     u_blinking_led
set_instance_assignment -name ROUTE_REGION \
     "X63 Y102 X185 Y162" -to u_blinking_led
set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \
     root_partition.qdb -to | -entity top

1.6.1. Step 1: Create a Reserved Core Partition

To export and reuse the root partition, first create a reserved core partition for subsequent core logic development in the Consumer project. When you define the partition, you can optionally specify settings to automatically export the partition each time you run compilation.

In the Intel^® Quartus^® Prime Pro Edition software, click File > Open Project and open the /Root_Partition_Reuse/Developer/top.qpf project file.
To synthesize the design, click Analysis & Synthesis on the Compilation Dashboard.
In the Project Navigator, right-click u_blinking_led in the Hierarchy tab, point to Design Partition, and select the Reserved Core partition Type.
To automatically export the final root_partition each time you run the Fitter, click Assignments > Design Partitions Window.
Specify a .qdb file name for the Post Final Export File option for the partition. The .qdb exports to the directory you specify, or to the project directory by default.

Figure 17. Setting Reserved Core Partition and Post Final Export File

1.6.2. Step 2: Define a Logic Lock Region

You must define a core-only, reserved, fixed routing region to reserve core resources in the Consumer project for the reserved core partition. The Consumer uses this area for core logic development.

Ensure that the exclusive placement region size is large enough to contain all core logic in the reserved core partition. For projects with multiple core partitions, constrain each partition in a non-overlapping placement or routing region. Follow these steps to define a core-only, reserved, fixed routing region to reserve core resources in the Developer project for non-periphery development:

Right-click the u_blinking_led instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region.
To modify the region properties, click Assignments > Logic Lock Regions Window.
In the Origin column, specify X63_Y102.
Change the Width to 123, and the Height to 61.
Enable the Reserved and Core-Only options.
Click the Routing Region cell. The Logic Lock Routing Region Settings dialog box appears.
Specify Fixed with expansion with Expansion Length of 0 for the Routing Type. The actual size and location are arbitrary for this tutorial. However, you can view and adjust the Logic Lock Region shape in the Chip Planner.

Figure 18. Logic Lock Regions Window
In the Logic Lock Regions window, right-click the u_blinking_led Logic Lock region name, and then click Locate Node > Locate in Chip Planner.

The Logic Lock region is shaded in purple. Preserving the periphery requires exporting everything outside the Logic Lock region. This is the reverse of the core partition reuse flow.

1.6.3. Step 3: Compile and Export the Root Partition

After compilation, the root partition exports automatically at the final stage, according to your specifications for the Post Final Export File option in the Design Partitions Window.

Follow these steps to compile the design and export the root partition:

To run full compilation, click Compile Design on the Compilation Dashboard.
View the exported root_partition.qdb in the project directory.

Note: The .qdb exports to the project directory in your project, regardless of the directory you specify in the Design Partitions Window.

1.6.4. Step 4: Copy Files to Consumer Project

Manually copy the root_partition.qdb and top.sdc files to the Root_Partition_Reuse/Consumer/ directory.

Note: The top-level design requires .sdc constraints. The Consumer can also include a separate .sdc file to constrain the logic that they provide. The Logic Lock boundary is visible in the Chip Planner in the Consumer project for reference only. The Consumer cannot modify this region.

In the Root Partition Reuse—Consumer Tutorial, you integrate the root_partition.qdb and top.sdc files into the Consumer project.

1.6.5. Step 5: Hardware Verification (Optional)

You can now verify the results of the Root Partition Reuse—Developer Tutorial module in hardware by completing the steps in (Optional) Step 8: Device Programming.

After completing this tutorial module, LEDs D6-D3 map to the blinking_led core, and LEDs D10-D7 map to the top-level (root) design. When you create and load the .sof, the blinking_led core does not illuminate any LEDs. The top-level design shows a shifting bit in green.

The behavior of the periphery LED driver carries into the Consumer project via the final .qdb file.

Figure 19. Illumination of LEDs after the Root Partition Reuse—Developer Tutorial

1.7. Root Partition Reuse—Consumer Tutorial

Follow the steps in this tutorial module to reuse a root partition in a Consumer project.

Process Description

As a root partition Consumer, you receive the final top-level, placed, and routed root partition from the Developer. The Developer reserves a core partition for subsequent development by the Consumer. The Consumer completes the final design by adding the root partition and integrating with their own logic.

Figure 20. Root Partition Reuse File Exchange

The following figure shows the RTL view of the Consumer's blinking_led partition. The Developer compiles and exports the final snapshot as a .qdb file. The Consumer adds their own logic to the reserved core partition.

Figure 21. Consumer's RTL View of blinking_led Partition

Finally, the Consumer integrates their logic with the files from the Developer to create the final image.

Figure 22. RTL View of the Integrated Developer and Consumer Partitions

Since the root partition .qdb includes final placement and routing information for the partition, the placement and routing is identical in the Consumer project, with the exception of clock signals that may be global signals.

Completed Files

The Root_Partition_Reuse/Completed/Consumer/ tutorial directory contains the completed files for this tutorial module.

Tutorial Module Steps

This tutorial module includes the following steps:

Step 1: Add the SDC and Root Partition
Step 2: Compile the Design
Step 3: Hardware Verification (Optional)

Command-Line Alternative Tutorial Step

You can skip Step 1: Add the SDC and Root Partition through Step 2: Compile the Design in this tutorial module by adding the following lines to the .qsf, and then running the Root_Partition_Reuse/Consumer/Script/run.sh script.

set_global_assignment -name SDC_FILE top.sdc

set_instance_assignment -name QDB_FILE_PARTITION \
     root_partition.qdb -to | -entity top

1.7.1. Step 1: Add the SDC and Root Partition

Follow these steps to add the .sdc file and the root_partition.qdb to the Consumer project.

In the Intel^® Quartus^® Prime Pro Edition software, click File > Open Project and open the /Root_Partition_Reuse/Consumer/top.qpf project file.
To add the .sdc file to the project, click Project > Add/Remove Files in Project.
On the Files pane, click the browse (...) button near File name to locate and select the top.sdc file. Click Open, and then click OK.
In the Design Partitions Window, specify a .qdb in Partition Database File to replace the root_partition logic.

Figure 23. Specifying the Partition Database File

1.7.2. Step 2: Compile the Design

After adding the .sdc and root partition to the Consumer project, run a full compilation of the design.

To run full compilation, click Compile Design on the Compilation Dashboard.

Figure 24. Compilation Complete
View the results of compilation in the Compilation Report.

1.7.3. Step 3: Hardware Verification (Optional)

You can now verify the results of the Root Partition Reuse—Consumer Tutorial module in hardware by completing the steps in (Optional) Step 8: Device Programming.

After completing this tutorial module, LEDs D6-D3 map to the blinking_led core, and LEDs D10-D7 map to the top-level design. The blinking_led core flashes red LEDs in a binary counting order. The top-level design shows a single bit shifting in green.

Figure 25. Illumination of LEDs after the Root Partition Reuse—Consumer Tutorial

1.8. (Optional) Step 8: Device Programming

You can optionally configure the FPGA on the Intel^® Arria^® 10 GX Development Kit to verify the results in hardware. You can adapt the following steps if you are using a different device or development kit.

Configuring the FPGA involves opening the Intel^® Quartus^® Prime Pro Edition Programmer, connecting to the Development Kit board, and loading the configuration SRAM Object File (.sof) into the SRAM of the FPGA.

Note: A .sof file configures the SRAM of an Intel^® FPGA. A Programmer Object File (.pof) programs a flash memory device with an FPGA configuration image for subsequent loading to an FPGA.

Follow these steps to configure the FPGA on the Intel^® Arria^® 10 GX Development Kit:

To open the Intel^® Quartus^® Prime Programmer, click Tools > Programmer.
Connect the board cables:
- JTAG USB cable to board
- Power cable attached to board and power source
Turn on power to the board.
In the Intel^® Quartus^® Prime Programmer, click Hardware Setup.

Figure 26. Hardware Setup
In the Hardware list, select USB-BlasterII, and then click Close. The device chain appears.

Note: If the device chain does not appear, verify the board connections.
Click Auto-Detect. The device chain populates.
In the Found Devices list, select the device that matches your design and click OK. For this tutorial, select the 10AX115S2 device that matches the 10AX115S2F45I1SG FPGA on the Intel^® Arria^® 10 GX Development Kit.

Figure 27. Select Device
Right-click the 10AX115S2 row in the file list, and then click Change File.

Figure 28. Programmer Window
Browse to select the top.sof file from the appropriate tutorial/output_files/ directory.
Enable the Program/Configure option for the 10AX115S2 row.

Figure 29. Program/Configure Option
Click Start. The progress bar reaches 100% when device configuration is complete. The device is now fully configured and in operation.

Figure 30. Programming Successful

Note: If device configuration fails, make sure the device you select for configuration matches the device you specify during .sof file generation.

1.9. AN 839: Design Block Reuse Tutorial Document Revision History

This document has the following revision history:

Document Version	Intel^® Quartus^® Prime Version	Changes
2019.07.26	19.2.0	Updated link to design example file.
2019.07.15	19.2.0	Updated description of partition type GUI and column display in Design Partitions Window.
2019.04.11	18.1.0	Updated default location of .qdb export to the project directory.
2018.11.20	18.1.0	Removed reference to Placed snapshot. Only Synthesized and Final snapshots are supported for design block reuse. Replaced references to "periphery reuse core" with "reserved core partition." This terminology has changed. Described automated partition export. Described Partition Database File option in Design Partitions Window. Updated link to latest design example files.
2018.01.15	17.1.0	First public release.