AN 869: Partially Reconfiguring a Design: on Intel Cyclone 10 GX FPGA Development Board

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AN-869 | 2019.07.15

Partially Reconfiguring a Design on Intel Cyclone 10 GX FPGA Development Board

This application note demonstrates transforming a simple design into a partially reconfigurable design and implementing the design on the Intel^® Cyclone^® 10 GX FPGA development board.

The partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can create multiple personas for a particular region in your design, without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA device resources. The current version of the software introduces a new and simplified compilation flow for partial reconfiguration.

Partial reconfiguration has the following advantages over a flat design:

Allows run-time design reconfiguration
Increases scalability of the design
Reduces system down-time
Supports dynamic time-multiplexing functions in the design
Lowers cost and power consumption through efficient use of board space

Implementation of this reference design requires basic familiarity with the Intel^® Quartus^® Prime FPGA implementation flow and knowledge of the primary Intel^® Quartus^® Prime project files.

Reference Design Requirements

This reference design requires the following:

Installation and basic familiarity with the Intel^® Quartus^® Prime Pro Edition version 19.1 design flow and project files for the design implementation.

Reference Design Overview

This reference design consists of one 32-bit counter. At the board level, the design connects the clock to a 50 MHz source, and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.

Figure 1. Flat Reference Design without PR Partitioning

Reference Design Files

The partial reconfiguration tutorial is available in the following location:

https://github.com/intel/fpga-partial-reconfig

To download the tutorial:

Click Clone or download.
Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
Navigate to the tutorials/c10_pcie_devkit_blinking_led sub-folder to access the reference design.

The flat folder consists of the following files:

Table 1. Reference Design Files
File Name	Description
top.sv	Top-level file containing the flat implementation of the design. This module instantiates the `blinking_led` sub-partition and the `top_counter` module.
top_counter.sv	Top-level 32-bit counter that controls `LED[1]` directly. The registered output of the counter controls `LED[0]`, and also powers `LED[2]` and `LED[3]` via the `blinking_led` module.
blinking_led.sdc	Defines the timing constraints for the project.
blinking_led.sv	This module acts as the PR partition. The module receives the registered output of `top_counter` module, which controls `LED[2]` and `LED[3]`.
blinking_led.qpf	Intel^® Quartus^® Prime project file containing the list of all the revisions in the project.
blinking_led.qsf	Intel^® Quartus^® Prime settings file containing the assignments and settings for the project.

Note:

The pr folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.

Figure 2. Reference Design Files

Reference Design Walkthrough

The following steps describe the application of partial reconfiguration to a flat design. The tutorial uses the Intel^® Quartus^® Prime Pro Edition software for the Intel^® Cyclone^® 10 GX FPGA development board:

Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration Controller IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board

Step 1: Getting Started

To copy the reference design files to your working environment and compile the blinking_led flat design:

In the Intel^® Quartus^® Prime Pro Edition software, click File > Open Project and select blinking_led.qpf.
To compile the flat design, click Processing > Start Compilation.

Step 2: Creating a Design Partition

You must create design partitions for each PR region that you want to partially reconfigure. You can create any number of independent partitions or PR regions in your design. This tutorial creates a design partition for the u_blinking_led instance.

To create design partition for partial reconfiguration:

Right-click the u_blinking_led instance in the Project Navigator, and then click Design Partition > Reconfigurable. A design partition icon appears next to each instance that is set as a partition. A design partition icon appears next to each instance that is set as a partition.
Figure 3. Creating Design Partitions from Project Navigator
To view and edit all design partitions in the project, click Assignments > Design Partitions Window. The design partition appears on the Assignments View tab of the Design Partitions Window.
Note: When you create a partition, the Intel^® Quartus^® Prime software automatically generates a partition name based on the instance name and hierarchy path. This default partition name can vary with each instance.
Edit the partition name in the Design Partitions Window by double-clicking the name. For this reference design, rename the partition name to pr_partition.
Figure 4. Design Partitions Window
To export the finalized static region from the base revision compile, double-click the entry for root_partition in the Post Final Export File column, and type blinking_led_static.qdb.

Verify that the blinking_led.qsf contains the following assignments, corresponding to your reconfigurable design partition:

set_instance_assignment -name PARTITION pr_partition -to \
     u_blinking_led -entity top
set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON \
        -to u_blinking_led -entity top
set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \	
        blinking_led_static.qdb -to | -entity top

Step 3: Allocating Placement and Routing Region for a PR Partition

For every base revision you create, the PR design flow uses your PR partition region allocation to place the corresponding persona core in the reserved region. To locate and assign the PR region in the device floorplan for your base revision:

Right-click the u_blinking_led instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region.
To view the Logic Lock in the Chip Planner floorplan, right-click the Region Name, and then click Locate Node > Locate in Chip Planner.
Figure 5. blinking_led in Chip Planner
To define the properties of the Logic Lock region, click Assignments > Logic Lock Regions Window.
Specify the placement region co-ordinates in the Origin column. The origin corresponds to the lower-left corner of the region. For example, to set a placement region with (X1 Y1) co-ordinates as (81 15), specify the Origin as X81_Y15. The Intel^® Quartus^® Prime software automatically calculates the (X2 Y2) co-ordinates (top-right) for the placement region, based on the height and width you specify.
Note: This tutorial uses the (X1 Y1) co-ordinates - (81 15), and a height and width of 20 for the placement region. Define any value for the placement region, as long as the region covers the blinking_led logic.
Enable the Reserved and Core-Only options.
Double-click the Routing Region option. The Logic Lock Routing Region Settings dialog box appears.
Select Fixed with expansion for the Routing type and click OK. Selecting this option automatically assigns an expansion length of 1.
Note: The routing region must be larger than the placement region, to provide extra flexibility for the Fitter when the engine routes different personas.
To ensure reliable operation with PR and EDCRC, create a floorplan assignment to reserve the unusable device resources at row Y=59. Use the Logic Lock Regions Window to define an empty reserved region, or add the following .qsf assignment:
```
set_instance_assignment -name EMPTY_PLACE_REGION /
     "X0 Y59 X102 Y59-R:C-empty_region" -to |
```
Figure 6. Empty Logic Lock Region

Verify that the blinking_led.qsf contains the following assignments, corresponding to your floorplanning:

set_instance_assignment -name PLACE_REGION "X81 Y15 X100 Y34" -to u_blinking_led
set_instance_assignment -name RESERVE_PLACE_REGION ON -to u_blinking_led
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to u_blinking_led
set_instance_assignment -name REGION_NAME u_blinking_led -to u_blinking_led
set_instance_assignment -name ROUTE_REGION "X80 Y14 X101 Y35" -to u_blinking_led
set_instance_assignment -name RESERVE_ROUTE_REGION OFF -to u_blinking_led
set_instance_assignment -name EMPTY_PLACE_REGION /
     "X0 Y59 X102 Y59-NR:C-empty_region" -to |

Step 4: Adding the Partial Reconfiguration Controller IP

The Partial Reconfiguration Controller Intel^® Arria^® 10/Cyclone 10 GX FPGA IP enables reconfiguration of the PR partition via .

Follow these steps to add the IP core to your Intel^® Quartus^® Prime project:

Type Partial Reconfiguration in the IP Catalog (Tools > IP Catalog).
Double-click Intel^® Arria^® 10/Cyclone 10 GX FPGA IP.
In the Create IP Variant dialog box, type pr_ip as the File Name, and then click Create. The parameter editor appears
Turn on Use as partial reconfiguration internal host, Enable JTAG debug mode, and Enable freeze interface. Turn off Enable Avalon-MM slave interface.

Figure 7. Partial Reconfiguration Controller IP Core Parameters
Click File > Save, and exit the parameter editor without generating the system. The parameter editor generates the pr_ip.ip IP variation file and adds the file to the blinking_led project.
Note:
1. If you are copying the pr_ip.ip file from the pr folder, manually edit the blinking_led.qsf file to include the following line:
```
set_global_assignment -name IP_FILE pr_ip.ip
```
2. Place the IP_FILE assignment after the SDC_FILE assignments (jtag.sdc and blinking_led.sdc) in your blinking_led.qsf file. This ordering ensures appropriate constraining of the Partial Reconfiguration Controller IP core.
  Note: To detect the clocks, the .sdc file for the PR IP must follow any .sdc that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR IP core comes after any .ip files or .sdc files that you use to create these clocks in the .qsf file for your Intel^® Quartus^® Prime project revision. For more information, refer to the Partial Reconfiguration IP Solutions User Guide.

Updating the Top-Level Design

To update the top.sv file with the PR_IP instance:

To add the pr_ip instance to the top-level design, uncomment the following code block in top.sv file:

pr_ip u_pr_ip
    (
        .clk           (clock),
        .nreset        (1'b1),
        .freeze        (freeze),
        .pr_start      (1'b0),            // ignored for JTAG
        .status        (pr_ip_status),
        .data          (16'b0),
        .data_valid    (1'b0),
        .data_ready    ()
    );

Save the file.

Figure 8. Partial Reconfiguration IP Core Integration

Step 5: Defining Personas

This reference design defines three separate personas for the single PR partition. To define and include the personas in your project:

Create three SystemVerilog files, blinking_led.sv, blinking_led_slow.sv, and blinking_led_empty.sv in your working directory for the three personas.

Note:

blinking_led.sv is already available as part of the files you copy from the flat/ sub-directory. You can simply reuse this file.
If you create the SystemVerilog files from the Intel^® Quartus^® Prime Text Editor, disable the Add file to current project option, when saving the files.

Table 2. PR Persona Definitions
File Name	Description	Code
blinking_led.sv	Default persona with same design as the flat implementation	`timescale 1 ps / 1 ps `default_nettype none module blinking_led ( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_two_on, output wire led_three_on ); localparam COUNTER_TAP = 23; reg led_two_on_r; reg led_three_on_r; assign led_two_on = led_two_on_r; assign led_three_on = led_three_on_r; always_ff @(posedge clock) begin led_two_on_r <= counter[COUNTER_TAP]; led_three_on_r <= counter[COUNTER_TAP]; end endmodule
blinking_led_slow.sv	LEDs blink slower	`timescale 1 ps / 1 ps `default_nettype none module blinking_led_slow ( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_two_on, output wire led_three_on ); localparam COUNTER_TAP = 27; reg led_two_on_r; reg led_three_on_r; assign led_two_on = led_two_on_r; assign led_three_on = led_three_on_r; always_ff @(posedge clock) begin led_two_on_r <= counter[COUNTER_TAP]; led_three_on_r <= counter[COUNTER_TAP]; end endmodule
blinking_led_empty.sv	LEDs stay ON	`timescale 1 ps / 1 ps `default_nettype none module blinking_led_empty( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_two_on, output wire led_three_on ); // LED is active low assign led_two_on = 1'b0; assign led_three_on = 1'b0; endmodule

Table 2. PR Persona Definitions

File Name

Description

Code

blinking_led.sv

Default persona with same design as the flat implementation

`timescale 1 ps / 1 ps
`default_nettype none


module blinking_led (
    // clock
    input wire clock,
    input wire [31:0] counter,

    // Control signals for the LEDs
    output wire led_two_on,
    output wire led_three_on
);

    localparam COUNTER_TAP = 23;

    reg led_two_on_r;
    reg led_three_on_r;
  
    assign led_two_on = led_two_on_r;
    assign led_three_on = led_three_on_r;

    always_ff @(posedge clock) 
    begin
        led_two_on_r <= counter[COUNTER_TAP];
        led_three_on_r <= counter[COUNTER_TAP];
    end

endmodule

blinking_led_slow.sv

LEDs blink slower

`timescale 1 ps / 1 ps
`default_nettype none

module blinking_led_slow (
    // clock
    input wire clock,
    input wire [31:0] counter,

    // Control signals for the LEDs
    output wire led_two_on,
    output wire led_three_on
);

    localparam COUNTER_TAP = 27;

    reg led_two_on_r;
    reg led_three_on_r;
 
    assign led_two_on = led_two_on_r;
    assign led_three_on = led_three_on_r;

    always_ff @(posedge clock) 
    begin
       led_two_on_r <= counter[COUNTER_TAP];
       led_three_on_r <= counter[COUNTER_TAP];
    end

endmodule

blinking_led_empty.sv

LEDs stay ON

`timescale 1 ps / 1 ps
`default_nettype none

module blinking_led_empty(
// clock
input wire clock,
input wire [31:0] counter,

// Control signals for the LEDs
output wire led_two_on,
output wire led_three_on
);
 
// LED is active low
assign led_two_on = 1'b0;
assign led_three_on = 1'b0;

endmodule

Step 6: Creating Revisions

The PR design flow uses the project revisions feature in the Intel^® Quartus^® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA.

From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.

To compile a PR design, you must create a PR implementation revision for each persona. In addition, you must assign revision types for each of the revisions. There are the following revision types:

Partial Reconfiguration - Base
Partial Reconfiguration - Persona Implementation

The following table lists the revision name and the revision type for each of the revisions:

Table 3. Revision Names and Types
Revision Name	Revision Type
`blinking_led.qsf`	Partial Reconfiguration - Base
`blinking_led_default.qsf`	Partial Reconfiguration - Persona Implementation
`blinking_led_slow.qsf`	Partial Reconfiguration - Persona Implementation
`blinking_led_empty.qsf`	Partial Reconfiguration - Persona Implementation

Setting the Base Revision Type

Click Project > Revisions.
Ensure that the blinking_led revision is set as the current revision.
To set the revision type for blinking_led, double -click the Revision Type cell, select Partial Reconfiguration - Base, and click OK.

Verify that the blinking_led.qsf now contains the following assignment:

##blinking_led.qsf
set_global_assignment -name REVISION_TYPE PR_BASE

Creating Implementation Revisions

To open the Revisions dialog box, click Project > Revisions.
To create a new revision, double-click <<new revision>>.
In Revision name, specify blinking_led_default and select blinking_led for Based on revision.
For the Revision type, select Partial Reconfiguration - Persona Implementation.
Enable This project uses a Partition Database (.qdb) file for the root partition. You do not need to specify the Root Partition Database file at this point. You can input this name at a later stage from the Design Partitions Window.

Figure 9. Creating Revisions
Similarly, set the Revision type for the other revisions:
- blinking_led_slow—select Partial Reconfiguration - Persona Implementation.
- blinking_led_empty—select Partial Reconfiguration - Persona Implementation.

Verify that each .qsf file now contains the following assignments:

set_global_assignment -name REVISION_TYPE PR_IMPL
set_instance_assignment -name QDB_FILE_PARTITION place_holder -to |
set_instance_assignment -name ENTITY_REBINDING place_holder -to u_blinking_led

where, place_holder is the default entity name for the newly created PR implementation revision.

Step 7: Compiling the Base Revision

Set blinking_led as the Current Revision.
Open the blinking_led.qsf and that ensure the file contains the following assignments:
```
set_global_assignment -name GENERATE_PR_RBF_FILE ON
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
```
These assignments allow the assembler to automatically generate the required PR bitstreams.
To compile the base revision, click Processing > Start Compilation. Alternatively, the following command compiles the base revision:
```
quartus_sh --flow compile  blinking_led -c blinking_led
```
On successful compilation, the blinking_led_static.qdb file generates in the project directory by default.

Step 8: Preparing PR Implementation Revisions

You must prepare the PR implementation revisions before you can compile and generate the PR bitstream for device programming. This setup includes adding the static region .qdb file as the source file for each implementation revision. In addition, you must specify the corresponding entity of the PR region.

To set the current revision, click Project > Revisions, select blinking_led_default as the Revision name, and then click Set Current.
To verify the correct source for each implementation revision, click Project > Add/Remove Files in Project. The blinking_led.sv file appears in the file list.

Figure 10.

Repeat steps 1 through 2 to verify or add the following other implementation revision source files:

Implementation Revision Name	Source File
blinking_led_default	blinking_led.sv
blinking_led_empty	blinking_led_empty.sv
blinking_led_slow	blinking_led_slow.sv

Set blinking_led_default as the current revision.
To set the .qdb file associated with the root partition, click Assignments > Design Partitions Window. Double-click the Partition Database File cell and specify the blinking_led_static.qdb file.
In the Entity Re-binding cell, specify the entity name of each PR partition that you change in the implementation revision. For the blinking_led_default implementation revision, specify the blinking_led name. This assignment overwrites the u_blinking_led instance from the base revision compile with the new blinking_led entity.
Figure 11. Specifying Partition Database File and Entity Rebinding

Alternatively, the following command assigns this file:
```
set_instance_assignment -name QDB_FILE_PARTITION \
	  blinking_led_static.qdb -to |
```

Repeat steps 4 through 6 to assign the same settings for the other revisions:

Table 4. Implementation Revision Entity Rebinding
Implementation Revision Name	Entity Re-binding
`blinking_led_default`	`blinking_led`
`blinking_led_slow`	`blinking_led_slow`
`blinking_led_empty`	`blinking_led_empty`

To compile the design, click Processing > Start Compilation. Alternatively, the following command compiles this project:
```
quartus_sh --flow compile blinking_led –c blinking_led_default
```
Repeat steps 1 through 8 to prepare blinking_led_slow and blinking_led_empty implementation revisions.

Note: You can specify any Fitter specific settings that you want to apply during the PR implementation compilation. Fitter specific settings impact only the fit of the persona, without affecting the imported static region.

Step 9: Programming the Board

Before you begin:

Connect the power supply to the Intel^® Cyclone^® 10 GX FPGA development board.
Connect the Intel^® FPGA Download Cable between your PC USB port and the Intel^® FPGA Download Cable port on the development board.

Note: This tutorial utilizes the Intel^® Cyclone^® 10 GX FPGA development board on the bench, outside of the PCIe* slot in your host machine.

To run the design on the Intel^® Cyclone^® 10 GX FPGA development board:

Open the Intel^® Quartus^® Prime software and click Tools > Programmer.
In the Programmer, click Hardware Setup and select an Intel FPGA download cable.
Click Auto Detect and select the device, 10CX220YF.
Click OK. The Intel^® Quartus^® Prime software detects and updates the Programmer with the three FPGA chips on the board.
Select the 10CX220YF device, click Change File and load the blinking_led_default.sof file.
Enable Program/Configure for blinking_led_default.sof file.
Click Start and wait for the progress bar to reach 100%.
Observe the LEDs on the board blinking at the same frequency as the original flat design.
To program only the PR region, right-click the blinking_led_default.sof file in the Programmer and click Add PR Programming File.
Select the blinking_led_default.pr_partition.rbf file.
Disable Program/Configure for blinking_led_default.sof file.
Enable Program/Configure for blinking_led_slow.pr_partition.rbf file and click Start. On the board, observe LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, LED[2] and LED[3] blink slower.
To re-program the PR region, right-click the .rbf file in the Programmer and click Change PR Programing File.
Select the .rbf files for the other two personas to observe the behavior on the board. Loading the blinking_led_default.pr_partition.rbf file causes the LEDs to blink at a specific frequency, and loading the blinking_led_empty.pr_partition.rbf file causes the LEDs to stay ON.

Figure 12. Programming the Intel^® Cyclone^® 10 GX FPGA Development Board

Troubleshooting PR Programming Errors

Ensuring proper setup of the Intel^® Quartus^® Prime Programmer and connected hardware helps to avoid any errors during PR programming.

If you face any PR programming errors, refer to "Troubleshooting PR Programming Errors" in the Intel^® Quartus^® Prime Pro Edition User Guide: Partial Reconfiguration for step-by-step troubleshooting tips.

Modifying an Existing Persona

You can change an existing persona, even after fully compiling the base revision.

For example, to cause the blinking_led_slow persona to blink even slower:

In the blinking_led_slow.sv file, modify the COUNTER_TAP parameter from 27 to 28.
Recompile only the blinking_led_slow revision. There is no requirement to modify or recompile the other revisions.

Adding a New Persona to the Design

After fully compiling your base revisions, you can still add new personas and individually compile these personas.

For example, to define a new persona that keeps one LED on and the other LED off:

Copy blinking_led_empty.sv to blinking_led_wink.sv.
In the blinking_led_wink.sv file, modify the assignment, assign led_three_on = 1'b0; to assign led_three_on = 1'b1;.
Create a new implementation revision, blinking_led_wink, by following the steps in Creating Implementation Revisions.

Note: The blinking_led_wink revision must use the blinking_led_wink.sv file, and use the blinking_led_wink in the entity rebinding assignment.
Compile the revision by clicking Processing > Start Compilation.

Document Revision History for AN 869: Partially Reconfiguring a Design on Intel Cyclone 10 GX FPGA Development Board

Date	Intel^® Quartus^® Prime Version	Changes
2019.07.15	19.1	Initial release of the document.