Ethernet Toolkit User Guide
UG-20305 | 2020.09.28
1. Ethernet Toolkit Overview
The Ethernet Toolkit is a TCL based debugging tool that allows you to
interact with an Ethernet Intel FPGA IP in real time.
Block Diagram of the Ethernet Toolkit
You can use the Ethernet Toolkit with hardware design that has standalone Ethernet IP. You can also use the Ethernet Toolkit with an Intel® Quartus® Prime generated Ethernet IP design example.
1.1. Features
The Ethernet Toolkit offers the following features when used with hardware
design that has standalone Ethernet IP as well as with an
Intel®
Quartus® Prime generated Ethernet IP design example:
- Verifies the status of the Ethernet link.
- Reads and writes to status and configuration registers of the IP.
- Displays the values of TX/RX status and statistics registers.
- Ability to assert and deassert IP resets.
- Verifies the IPs error correction capability.
The Ethernet Toolkit also offers some additional features when used with an
Intel®
Quartus® Prime generated Ethernet IP design example:
- Provides access to the example design packet generator.
- Execute testing procedures to verify the functionality of Ethernet IPs.
- Enable and disable MAC loopback.
- Set source and destination MAC addresses.
1.2. Supported Ethernet IP Cores and Devices
| Supported Ethernet IP Cores | Supported Tile | Supported Device | Initial Supported Intel® Quartus® Prime Version | Initial Supported IP Version |
|---|---|---|---|---|
| Intel® Stratix® 10 10GBASE-KR PHY IP | L- and H-tile | Intel® Stratix® 10 | 20.1 | 19.1.0 |
| Low Latency 40G Ethernet Intel® FPGA IP | L- and H-tile | Intel® Stratix® 10 | 20.1 | 19.1.0 |
| Low Latency 100G Ethernet Intel® FPGA IP | L- and H-tile | Intel® Stratix® 10 | 20.1 | 19.1.1 |
| Low Latency 100G Ethernet Intel® Agilex™ FPGA IP | H-tile | Intel® Agilex™ | 20.3 | 20.3.0 |
| H-Tile Hard IP for Ethernet Intel® FPGA IP | H-tile | Intel® Stratix® 10 | 20.1 | 19.2.0 |
| H-Tile Hard IP for Ethernet Intel® Agilex™ FPGA IP | H-tile | Intel® Agilex™ | 20.3 | 20.3.0 |
| Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP | H-tile | Intel® Stratix® 10 GX 10M | 20.1 | 19.1.0 |
| E-Tile Hard IP for Ethernet Intel® FPGA IP | E-tile | Intel® Stratix® 10 | 20.1 | 19.3.0 |
| E-Tile Ethernet IP for Intel Agilex FPGA | E-tile | Intel® Agilex™ | 20.1 | 19.3.0 |
| Low Latency E-Tile 40G Ethernet Intel® FPGA IP | E-tile | Intel® Stratix® 10 | 20.1 | 19.1.0 |
| Intel® Agilex™ |
2. Setting up the Ethernet Toolkit
This section describes how to set up and run the Ethernet Toolkit for
your Ethernet
Intel® FPGA IP.
2.1. System Requirements and Prerequisites
2.1.1. System Requirements
You must meet the following software and hardware requirements to run the Ethernet Toolkit:
- Windows PC or Linux workstation
-
Intel®
Quartus® Prime Pro Edition softwareNote: Refer to Supported Ethernet IP Cores and Devices for information on specific Intel® Quartus® Prime Pro Edition software version needed for each supported Ethernet Intel® FPGA IP.
- Device specific Intel® FPGA Development Kit that you use to run your Ethernet IP
2.1.2. Enabling your Design for the Ethernet Toolkit
To enable the use of the Ethernet Toolkit, you must turn on the Enable JTAG to Avalon Master Bridge parameter in the Ethernet IP
parameter editor.
Figure 1. Example of E-Tile Hard IP for Ethernet
Intel® FPGA IP Parameter Editor
2.2. Running the Ethernet Toolkit
Before you begin with running the Ethernet
toolkit, you must compile your Ethernet Intel FPGA IP with JTAG to Avalon Memory-Mapped
master bridge parameter enabled.
Figure 2. Opening Ethernet Toolkit in
Intel®
Quartus® Prime Software
Perform the following steps to launch the Ethernet Toolkit:
- In the Intel® Quartus® Prime Pro Edition software, select to launch the system console.
- In the system console, click Load Design in the Toolkit Explorer tab, and load the generated .sof file. If you already have Intel® Quartus® Prime project containing .sof is open, you just need to launch the system console.
- You can see all of the Ethernet IP instances supported by Ethernet Toolkit within the design. Select one of the instances. The Ethernet Toolkit can automatically detect an instance of a supported Ethernet Intel® FPGA IP within a design.
- Now select the toolkit corresponding to the Ethernet IP that was selected in Details tab, and click Open Toolkit.
3. Functional Description
The Ethernet Toolkit is a TCL-based graphical user interface (GUI). It
allows you to perform sequences of read and write operations
to
CSRs, and it displays the read information visually through LEDs or
text.
You can obtain the following information through the Ethernet Toolkit:
- Physical Coding Sublayer (PCS) status
- PHY status
- TX and RX Media Access Control (MAC) settings
- Auto Negotiation (AN), and Link Training (LT) status
- Reed Solomon Forward Error Correction (RS-FEC) status
3.1. Ethernet Toolkit Groups and Tabs
The Ethernet Toolkit GUI is organized in the following groups and Tabs:
- IP Configuration and other Information
- General Commands
- Settings
- Tabs:
- Status
- Statistics Counters
- Testing Features
Figure 3. Ethernet Toolkit Groups and Tabs
Note: The following sections
include the examples of Ethernet Toolkit Groups and Tabs for E-Tile Hard IP for Ethernet
Intel FPGA IP.
3.1.1. IP Configuration and Other Information
This IP Configuration and Other
Information group displays information about the variant of the
Ethernet IP being used in the design.
Figure 4. Example of IP Configuration and Other Information
Group
3.1.2. General Commands
The General Commands group provides option to assert and deassert the IP resets.
There is a checkbox for Using Quartus Generate Example Design that provides access to the example design packet generator, and to the PHY and packet generator loopback test. This option releases the JTAG master service provided by the JTAG to Avalon Memory-Mapped master bridge instantiated within the IP, and claims the master service provided by the JTAG to Avalon Memory-Mapped master bridge external to the IP, which the example design instantiates, allowing for the communication with the packet generator.
Figure 5. Example of General Commands Group
3.1.3. Settings
For the E-Tile Hard IP for Ethernet
Intel® FPGA IP and E-Tile Hard IP for Intel Agilex
FPGA IP, the Settings group allows you to select
the number of channels you want to access in case of multi-channel 10G/25G design. In
case of Low Latency 40G Ethernet Intel FPGA IP and Low Latency 100G Ethernet Intel FPGA
IP, you should see a text box that allow you to set the value of clk_status signal. This value is being used in calculation of TX and RX
clock values.
Figure 6. Example of Settings Group
3.1.4. Status
The Status tab provides different values of various status and settings registers.You need to click Start Reading All Status button to start reading the registers. The read happens on discrete time intervals, and continue to read until you click Stop Reading All Status button.
The status tab of the Ethernet Toolkit has the following five tabs:
- Link Bring Up
- PCS Status
- PHY Status
- MAC Settings
- AN and LT Status
3.1.4.1. Link Bring Up
Figure 7. Example of Link Bring Up Tab
3.1.4.2. PCS Status
Figure 8. Example of PCS Status Tab
3.1.4.3. PHY Status
Figure 9. Example of PHY Status Tab
3.1.4.4. MAC Settings
Figure 10. Example of MAC Settings Tab
3.1.4.5. AN and LT Status
Figure 11. Example of AN and LT Status Tab
3.1.5. Statistics Counters
The statistics counters tab has three following tabs:
- Example Design Packet Generator Settings
- Transmitter and Receiver Statistics
- RS-FEC
3.1.5.1. Example Design Packet Generator Settings
You can access Example Design Packet Generator
Settings tab only if you are using
an
Intel®
Quartus® Prime generated design
example. You can start and stop the packet generator using the options from this
tab.You can also set the source and destination address using
this
tab.
You can set the packet generator mode for the following options:
- Random Mode- Random Gap
- Random Mode- No Gap
- Fixed Size Mode
- Incremental Mode
You can set the total number of packets limit using the fixed size and incremental mode options.
Note: The Example Design Packet Generator Settings tab is not available for
E-Tile Hard IP for Ethernet Intel FPGA IP and E-Tile Hard IP for Intel Agilex FPGA
IP variants with PCS only and PCS+RS-FEC modes.
Figure 12. Example Design Packet Generator Settings Tab
3.1.5.2. Transmitter and Receiver Statistics
You can read multiple transmitter and receiver statistics registers in the
Transmitter and Receiver Statistics tab.
Click Start Reading Transmitter or Start Reading Receiver option to read the registers
in discrete time intervals.
Figure 13. Example of Transmitter and Receiver Statistics
Tab
3.1.5.3. RS-FEC
You can use RS-FEC tab to perform error insertion. You
can also read the RS-FEC registers using the Start Reading
RS-FEC Statistics option which displays corrected and uncorrected
codewords.
Figure 14. Example of RS-FEC Tab
3.1.6. Testing Features
The testing features contains three following tabs:
- Example Design PHY and Packet Generator Loopback TestNote: You can access this tab only if you are using an Intel® Quartus® Prime generated design example.
- Read Register
- Write to Register
3.1.6.1. Example Design PHY and Packet Generator Loopback Test
You can access
Example Design PHY and Packet Generator Loopback Test tab
only if you are using an
Intel®
Quartus® Prime
generated design
example. To use this tab of the Ethernet Toolkit, you must disable MAC
Loopback Mode option in Example Design Packet Generator
Settings group under Statistics Counter
tab.
When you turn on the Run Test in External Loopback
Mode option, the internal serial loopback is disabled for the IP.
When you turn on the Start PHY and Packet Generator
Loopback Test option, the test procedure runs
a series
of processes as shown in the figure below.
Figure 15. Example Design PHY and Packet Generator Loopback
Test
3.1.6.2. Read Register
You can directly
read all
accessible IP registers using Read
Register
tab by
providing the 32-bit register base
address.
Note: Do
not attempt to access any register address that is reserved or undefined. Access
to registers that do not exist in your IP core variation have unspecified
results.
Figure 16. Example of Read Register
3.1.6.3. Write to Register
You can directly write to
all
accessible IP registers using Write to
Register
tab by
providing the 32-bit register base
address.
Note: Do
not attempt to access any register address that is reserved or undefined. Access
to registers that do not exist in your IP core variation have unspecified
results.
Figure 17. Example of Write Register
3.2. Link Bring-Up Guidelines
Refer to link bring-up guidelines in individual Ethernet IP user guides and map the steps to GUI options and check boxes.
3.2.1. Example Link Bring-Up using E-Tile Hard IP
This section covers an example of link bring-up for the E-Tile Hard IP for Ethernet Intel® FPGA IP. Perform the following steps to establish Ethernet link:
If your design (.sof) instantiates Ethernet IP with
Enable AN/LT parameter enabled in IP parameter
editor:
- If you configure your IP in internal or external loopback, turn on the Ignore Nonce parameter and if you use only internal loopback then turn on Enable Internal Loopback parameter.
- Click Reset AN/LT Sequencer in AN and LT status tab of the Ethernet Toolkit.
If your design (.sof) instantiates Ethernet IP with
Enable AN/LT parameter disabled in IP
parameter editor:
- If you configure your IP in internal loopback:
- Turn on Enable Internal Loopback parameter.
- Turn on Initial Adaptation parameter.
- If you configure your IP in external loopback or connected to
link partner:
- Choose a recipe from the PMA Adaptation Select option and click Apply.
- Click External Adaption button.
4. Document Revision History for the Ethernet Toolkit User Guide
| Document Version | Changes |
|---|---|
| 2020.09.28 | Initial release. |