This application note describes the implementation of 9.8304 Gbps Common Public Radio Interface (CPRI) using the Arria^® V GT and Arria^® V ST FPGA transceivers.

The hard physical coding sublayer (PCS) block in Arria V FPGAs supports data rates up to 6.5536 Gbps. To implement 9.8304 Gbps CPRI, the transceiver is configured in Physical Media Attachment (PMA) direct mode and a soft PCS block is implemented in the FPGA core.

The following sections describe the configuration of Native PHY IP in PMA direct mode, the architecture of the soft PCS in the FPGA core, and the steps for auto rate negotiation from 9.8304 Gbps down to 1.2288 Gbps.

The soft PCS is implemented in the FPGA core and is connected to the transceiver PMA through the 80-bit interface. The input data width to the transmit and receive registers is 32 bits when 8b/10b encoding is enabled and 40 bits when 8b/10b encoding is disabled.

The transmit and receive registers synchronize the data from the core or PMA with the soft PCS clocks. The reset signal is synchronized with the usr_clk before it is fed to all the blocks. The functionality of the 8b/10b encoder and decoder, the TX Bitslip, and Word Aligner is identical to those in the hard PCS. The word aligner outputs the number of bits slipped on its rx_boundary_sel output port.

The transmit width adapter block is used to convert the input data width in the soft PCS from 32 bits to 64 bits (with 8b/10b encoding) or 80 bits (without 8b/10b encoding) for data rates of 4.9152 Gbps and above. The same block is reused for lower data rates in auto rate negotiation. For data rates of 3.072 Gbps or below, the transmit width adapter converts the data width from 32 bits to 16 bits (with 8b/10b encoding) or 20 bits (without 8b/10b encoding). Because the PMA direct interface mode has a minimum frequency limitation, data width conversion is required.

Similarly, the receive width adapter block reverses the data width from 64 bits (with 8b/10b encoding) or 80 bits (without 8b/10b encoding) to 32 bits for data rates of 4.9152 Gbps and above. For data rates of 3.072 Gbps or below, the receive width adapter converts the data width from 16 bits (with 8b/10b enconding) or 20 bits (without 8b/10b encoding) to 32 bits.

The phase measuring FIFO transfers the data from the write clock domain to the read clock domain. For example, in the TX path it transfers the data from usr_pma_clk clock domain to tx_pma_clk clock domain and similarly, for the RX path it transfers the data from rx_pma_clk clock domain to usr_pma_clk clock domain. The FIFO calculates the phase difference between the read and write clock domains as well as the number of data bits stored in the FIFO for latency calculation.

You can measure the FIFO latency to the desired precision using the dedicated fifo_calc_clk clock signal. The frequency of fifo_calc_clk is related to the usr_pma_clk period. N clock periods of the fifo_calc_clk are equal to M clock periods of usr_pma_clk where N and M are integers. For example, N may be multiple of M, or based on the required accuracy the ratio of M/N may be greater than 1 ( such as 64/63 or 128/127). The accuracy for measuring the FIFO latency using the fifo_calc_clk signal increases as the M/N ratio approaches 1. For the TX and RX phase measuring FIFOs, set the value of N using the tx_fifo_sample_size and rx_fifo_sample_size input ports respectively.

The accuracy for measuring the FIFO latency is N/(least common multiple of usr_pma_clk periods). The FIFO latency can be read from the fifo_latency port.

The accumulated phase difference measured across the sample size of N clock periods can be accessed through phase_measure_acc port. The ph_acc_valid port indicates that the phase_measure_acc port is updated with the new data in fifo_calc_clk domain.

Two system clocks are provided from the core to the soft PCS, unlike the hard PCS where the clock from the transceiver is sent to the core. The upper layer clock usr_clk is used to clock the 32 bit data. The usr_pma_clk is used to clock the 80 bit or 20 bit data. These two clocks are generated from the user system clock.

Both the usr_clk and usr_pma_clk must have 0 parts per million (ppm) phase difference to avoid timing violations in the TX and RX data width adapter blocks. To ensure 0 ppm phase difference between both the clock domains, generate the usr_clk and usr_pma_clk internally using the fPLL from the reference clock source.

You may choose to generate both clocks from an external PLL; however, ensure that the skew between these two clocks is minimized on the PCB. You can select the pin assignments such that dedicated clock pins are used for both clocks. Use the QSF assignments below if you want to use the dedicated clock pins.

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to usr_clk

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to usr_pma_clk

Because the designs for the soft PCS and the hard PCS are different, their latencies are different. The extra flip-flops that are added to the soft PCS datapath to meet the tight timing requirements increase the overall soft PCS latency.

In Arria V GT and Arria V ST FPGAs, a soft PCS implementation supports auto rate negotiation from 9.8304 Gbps to 1.2288 Gbps. Altera recommends to use the hard PCS for CPRI interfaces where the maximum interface data rate is 6.144 Gbps or lower. In this example, the channels are initialized at the highest supported data rate and are switched to successive lower data rates.

To minimize the CMU PLL usage, choose a common appropriate base data rate. To achieve the desired effective data rate, use the local clock divider block. Two CMU PLLs are required to support multiple CPRI channels which require auto rate negotiation independently within the range from 9.8304 Gbps to 1.2288 Gbps.