Intel MAX 10 FPGA Device Overview
Intel MAX 10 FPGA Device Overview
Intel® MAX® 10 devices are single-chip, non-volatile low-cost programmable logic devices (PLDs) to integrate the optimal set of system components.
The highlights of the Intel® MAX® 10 devices include:
- Internally stored dual configuration flash
- User flash memory
- Instant on support
- Integrated analog-to-digital converters (ADCs)
- Single-chip Nios II soft core processor support
Intel® MAX® 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Key Advantages of Intel MAX 10 Devices
Advantage | Supporting Feature |
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Simple and fast configuration | Secure on-die flash memory enables device configuration in less than 10 ms |
Flexibility and integration |
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Low power |
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20-year-estimated life cycle | Built on TSMC's 55 nm embedded flash process technology |
High productivity design tools |
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Summary of Intel MAX 10 Device Features
Feature | Description | |
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Technology | 55 nm TSMC Embedded Flash (Flash + SRAM) process technology | |
Packaging |
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Core architecture |
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Internal memory blocks |
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User flash memory (UFM) |
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Embedded multiplier blocks |
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ADC |
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Clock networks |
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Internal oscillator | Built-in internal ring oscillator | |
PLLs |
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General-purpose I/Os (GPIOs) |
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External memory interface (EMIF) 1 | Supports up to 600
Mbps external memory interfaces:
Note: For 600
Mbps performance, –6 device speed grade is required.
Performance varies according to device grade (commercial,
industrial, or automotive) and device speed grade (–6 or –7). Refer
to the
Intel®
MAX® 10 FPGA Device Datasheet or
External Memory Interface Spec
Estimator for more details.
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Configuration |
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Flexible power supply schemes |
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Intel MAX 10 Device Ordering Information
Intel MAX 10 Device Feature Options
Option | Feature |
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Compact | Devices with core architecture featuring single configuration image with self-configuration capability |
Flash | Devices with core architecture featuring:
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Analog | Devices with core architecture featuring:
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Intel MAX 10 Device Maximum Resources
Resource | Device | |||||||
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10M02 | 10M04 | 10M08 | 10M16 | 10M25 | 10M40 | 10M50 | ||
Logic Elements (LE) (K) | 2 | 4 | 8 | 16 | 25 | 40 | 50 | |
M9K Memory (Kb) | 108 | 189 | 378 | 549 | 675 | 1,260 | 1,638 | |
User Flash Memory (Kb) 2 | 96 | 1,248 | 1,376 | 2,368 | 3,200 | 5,888 | 5,888 | |
18 × 18 Multiplier | 16 | 20 | 24 | 45 | 55 | 125 | 144 | |
PLL | 2 | 2 | 2 | 4 | 4 | 4 | 4 | |
GPIO | 246 | 246 | 250 | 320 | 360 | 500 | 500 | |
LVDS | Dedicated Transmitter | 15 | 15 | 15 | 22 | 24 | 30 | 30 |
Emulated Transmitter | 114 | 114 | 116 | 151 | 171 | 241 | 241 | |
Dedicated Receiver | 114 | 114 | 116 | 151 | 171 | 241 | 241 | |
Internal Configuration Image | 1 | 2 | 2 | 2 | 2 | 2 | 2 | |
ADC | — | 1 | 1 | 1 | 2 | 2 | 2 |
Intel MAX 10 Devices I/O Resources Per Package
Device | Package | ||||
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Type |
M153 153-pin MBGA |
U169 169-pin UBGA |
U324 324-pin UBGA |
E144 144-pin EQFP |
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Size | 8 mm × 8 mm | 11 mm × 11 mm | 15 mm × 15 mm | 22 mm × 22 mm | |
Ball Pitch | 0.5 mm | 0.8 mm | 0.8 mm | 0.5 mm | |
10M02 | 112 | 130 | 246 | 101 | |
10M04 | 112 | 130 | 246 | 101 | |
10M08 | 112 | 130 | 246 | 101 | |
10M16 | — | 130 | 246 | 101 | |
10M25 | — | — | — | 101 | |
10M40 | — | — | — | 101 | |
10M50 | — | — | — | 101 |
Device | Package | ||||||
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Type |
V36 36-pin WLCSP |
V81 81-pin WLCSP |
U324 324-pin UBGA |
F256 256-pin FBGA |
F484 484-pin FBGA |
F672 672-pin FBGA |
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Size | 3 mm × 3 mm | 4 mm × 4 mm | 15 mm × 15 mm | 17 mm × 17 mm | 23 mm × 23 mm | 27 mm × 27 mm | |
Ball Pitch | 0.4 mm | 0.4 mm | 0.8 mm | 1.0 mm | 1.0 mm | 1.0 mm | |
10M02 | 27 | — | 160 | — | — | — | |
10M04 | — | — | 246 | 178 | — | — | |
10M08 | — | 56 | 246 | 178 | 250 | — | |
10M16 | — | — | 246 | 178 | 320 | — | |
10M25 | — | — | — | 178 | 360 | — | |
10M40 | — | — | — | 178 | 360 | 500 | |
10M50 | — | — | — | 178 | 360 | 500 |
Intel MAX 10 Vertical Migration Support
Intel MAX 10 I/O Vertical Migration Support
- The arrows indicate the migration paths. The devices included in each vertical migration path are shaded. Non-migratable devices are omitted. Some packages have several migration paths. Devices with lesser I/O resources in the same path have lighter shades.
- To achieve the full I/O migration across product lines in the same migration path, restrict I/Os usage to match the product line with the lowest I/O count.
Intel MAX 10 ADC Vertical Migration Support
Source | Target | Migratable Pins |
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Single ADC device | Single ADC device | You can migrate all ADC input pins |
Dual ADC device | Dual ADC device | |
Single ADC device | Dual ADC device |
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Dual ADC device | Single ADC device |
Logic Elements and Logic Array Blocks
The LAB consists of 16 logic elements (LE) and a LAB-wide control block. An LE is the smallest unit of logic in the Intel® MAX® 10 device architecture. Each LE has four inputs, a four-input look-up table (LUT), a register, and output logic. The four-input LUT is a function generator that can implement any function with four variables.
Analog-to-Digital Converter
Feature | Description |
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12-bit resolution |
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Up to 1 MSPS sampling rate | Monitors single-ended external inputs with a cumulative sampling rate of 25 kilosamples per second to 1 MSPS in normal mode |
Up to 17 single-ended external inputs for single ADC devices | One dedicated analog and 16 dual function input pins |
Up to 18 single-ended external inputs for dual ADC devices |
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On-chip temperature sensor | Monitors external temperature data input with a sampling rate of up to 50 kilosamples per second |
User Flash Memory
The user flash memory (UFM) block in Intel® MAX® 10 devices stores non-volatile information.
UFM provides an ideal storage solution that you can access using Avalon Memory-Mapped (Avalon-MM) slave interface protocol.
Features | Capacity |
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Endurance | Counts to at least 10,000 program/erase cycles |
Data retention |
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Operating frequency | Maximum 116 MHz for parallel interface and 7.25 MHz for serial interface |
Data length | Stores data up to 32 bits length in parallel |
Embedded Multipliers and Digital Signal Processing Support
Intel® MAX® 10 devices support up to 144 embedded multiplier blocks. Each block supports one individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers.
With the combination of on-chip resources and external interfaces in Intel® MAX® 10 devices, you can build DSP systems with high performance, low system cost, and low power consumption.
You can use the Intel® MAX® 10 device on its own or as a DSP device co-processor to improve price-to-performance ratios of DSP systems.
You can control the operation of the embedded multiplier blocks using the following options:
- Parameterize the relevant IP cores with the Intel® Quartus® Prime parameter editor
- Infer the multipliers directly with VHDL or Verilog HDL
- DSP IP cores:
- Common DSP processing functions such as finite impulse response (FIR), fast Fourier transform (FFT), and numerically controlled oscillator (NCO) functions
- Suites of common video and image processing functions
- Complete reference designs for end-market applications
- DSP Builder for Intel® FPGAs interface tool between the Intel® Quartus® Prime software and the MathWorks Simulink and MATLAB design environments
- DSP development kits
Embedded Memory Blocks
You can configure the M9K memory blocks as RAM, FIFO buffers, or ROM.
The Intel® MAX® 10 device memory blocks are optimized for applications such as high throughput packet processing, embedded processor program, and embedded data storage.
Operation Modes | Port Widths |
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Single port | ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36 |
Simple dual port | ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36 |
True dual port | ×1, ×2, ×4, ×8, ×9, ×16, and ×18 |
Clocking and PLL
Intel® MAX® 10 devices offer the following resources: global clock (GCLK) networks and phase-locked loops (PLLs) with a 116-MHz built-in oscillator.
Intel® MAX® 10 devices support up to 20 global clock (GCLK) networks with operating frequency up to 450 MHz. The GCLK networks have high drive strength and low skew.
- Reduction in the number of oscillators required on the board
- Reduction in the device clock pins through multiple clock frequency synthesis from a single reference clock source
- Frequency synthesis
- On-chip clock de-skew
- Jitter attenuation
- Dynamic phase-shift
- Zero delay buffer
- Counter reconfiguration
- Bandwidth reconfiguration
- Programmable output duty cycle
- PLL cascading
- Reference clock switchover
- Driving of the ADC block
FPGA General Purpose I/O
The Intel® MAX® 10 I/O buffers support a range of programmable features.
These features increase the flexibility of I/O utilization and provide an alternative to reduce the usage of external discrete components such as a pull-up resistor and a PCI clamp diode.
External Memory Interface
Dual-supply Intel® MAX® 10 devices feature external memory interfaces solution that uses the I/O elements on the right side of the devices together with the UniPHY IP.
With this solution, you can create external memory interfaces to 16-bit SDRAM components with error correction coding (ECC).
Configuration
Feature | Description |
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Dual configuration |
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Design security |
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SEU Mitigation |
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Dual-purpose configuration pin |
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Configuration data compression |
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Instant-on | Provides the fastest power-up mode for Intel® MAX® 10 devices. |
Configuration Scheme | Compression | Encryption | Dual Image Configuration | Data Width |
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Internal Configuration | Yes | Yes | Yes | — |
JTAG | — | — | — | 1 |
Power Management
Power Options | Advantage |
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Single-supply device | Saves board space and costs. |
Dual-supply device |
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Power management controller scheme |
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Document Revision History for Intel MAX 10 FPGA Device Overview
Date | Version | Changes |
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December 2017 | 2017.12.15 |
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February 2017 | 2017.02.21 |
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December 2016 | 2016.12.20 |
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May 2016 | 2016.05.02 |
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November 2015 | 2015.11.02 |
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May 2015 | 2015.05.04 |
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December 2014 | 2014.12.15 |
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September 2014 | 2014.09.22 | Initial release. |