Altera Quartus Prime Standard Edition Settings File Reference Manual
Altera Quartus Prime Standard Edition Settings File Reference Manual
Advanced I/O Timing Assignments
BOARD_MODEL_EBD_FAR_END
Specifies the far-end node to be used in the Electronic Board Description (EBD) path description.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name BOARD_MODEL_EBD_FAR_END -to <to> -entity <entity name> <value>
BOARD_MODEL_EBD_FILE_NAME
Specifies the Electronic Board Description (EBD) file that contains the path description for an I/O pin.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name BOARD_MODEL_EBD_FILE_NAME -to <to> -entity <entity name> <value>
BOARD_MODEL_EBD_SIGNAL_NAME
Specifies the Electronic Board Description (EBD) path description to be used with an I/O pin. You must specify the EBD file name.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name BOARD_MODEL_EBD_SIGNAL_NAME -to <to> -entity <entity name> <value>
BOARD_MODEL_FAR_C
Specifies, in farads, the board trace model far capacitance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_C -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_FAR_C -section_id <section identifier> <value>
BOARD_MODEL_FAR_DIFFERENTIAL_R
Specifies, in ohms, the board trace model far differential resistance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -section_id <section identifier> <value>
BOARD_MODEL_FAR_PULLDOWN_R
Specifies, in ohms, the board trace model far pull-down resistance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -section_id <section identifier> <value>
BOARD_MODEL_FAR_PULLUP_R
Specifies, in ohms, the board trace model far pull-up resistance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_FAR_PULLUP_R -section_id <section identifier> <value>
BOARD_MODEL_FAR_SERIES_R
Specifies, in ohms, the board trace model far series resistance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_FAR_SERIES_R -section_id <section identifier> <value>
BOARD_MODEL_NEAR_C
Specifies, in farads, the board trace model near capacitance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_C -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_C -section_id <section identifier> <value>
BOARD_MODEL_NEAR_DIFFERENTIAL_R
Specifies, in ohms, the board trace model near differential resistance.
Type
String
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -section_id <section identifier> <value>
BOARD_MODEL_NEAR_PULLDOWN_R
Specifies, in ohms, the board trace model near pull-down resistance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -section_id <section identifier> <value>
BOARD_MODEL_NEAR_PULLUP_R
Specifies, in ohms, the board trace model near pull-up resistance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_PULLUP_R -section_id <section identifier> <value>
BOARD_MODEL_NEAR_SERIES_R
Specifies, in ohms, the board trace model near series resistance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_SERIES_R -section_id <section identifier> <value>
BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
Specifies, in farads/inch, the board trace model near transmission line distributed capacitance.
Type
String
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -section_id <section identifier> <value>
BOARD_MODEL_NEAR_TLINE_LENGTH
Specifies, in inches, the board trace model near transmission line length.
Type
String
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -section_id <section identifier> <value>
BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
Specifies, in henrys/inch, the board trace model near transmission line distributed inductance.
Type
String
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -section_id <section identifier> <value>
BOARD_MODEL_TERMINATION_V
Specifies, in volts, the board trace model termination voltage.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TERMINATION_V -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_TERMINATION_V -section_id <section identifier> <value>
BOARD_MODEL_TLINE_C_PER_LENGTH
Specifies, in farads/inch, the board trace model far transmission line distributed capacitance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -section_id <section identifier> <value>
BOARD_MODEL_TLINE_LENGTH
Specifies, in inches, the board trace model far transmission line length.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_TLINE_LENGTH -section_id <section identifier> <value>
BOARD_MODEL_TLINE_L_PER_LENGTH
Specifies, in henrys/inch, the board trace model far transmission line distributed inductance.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -section_id <section identifier> <value>
ENABLE_ADVANCED_IO_TIMING
Allows the TimeQuest Timing Analyzer to use Advanced I/O Timing to generate I/O timing results. Timing results are based on the board trace model specified for each pin, and may differ from the results currently reported.
Type
Boolean
Device Support
- Arria GX
- Stratix II
- Stratix II GX
Notes
None
Syntax
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING <value>
OUTPUT_IO_TIMING_ENDPOINT
Specifies the node at which output I/O Timing ends.
Type
Enumeration
Values
- Far End
- Near End
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name OUTPUT_IO_TIMING_ENDPOINT -to <to> -entity <entity name> <value> set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT -entity <entity name> <value> set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT <value>
Default Value
Near End
OUTPUT_IO_TIMING_FAR_END_VMEAS
Specifies, in volts, the measurement voltage at the far-end.
Type
String
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -to <to> -entity <entity name> <value> set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -section_id <section identifier> <value> set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS <value>
OUTPUT_IO_TIMING_NEAR_END_VMEAS
Specifies, in volts, the measurement voltage at the near-end.
Type
String
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -to <to> -entity <entity name> <value> set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -section_id <section identifier> <value> set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS <value>
PCB_LAYER
Specifies which PCB layer the signal breaks out on
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name PCB_LAYER -to <to> -entity <entity name> <value> set_global_assignment -name PCB_LAYER -section_id <section identifier> <value>
PCB_LAYERS
Specifies the properties of all PCB layers
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name PCB_LAYERS -to <to> <value>
PCB_LAYER_THICKNESS
Thickness of the specific PCB layer
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name PCB_LAYER_THICKNESS -to <to> -entity <entity name> <value> set_global_assignment -name PCB_LAYER_THICKNESS -section_id <section identifier> <value>
SYNCHRONOUS_GROUP
A logic option that assigns a synchronous group number for the specified node. This option directs the SSN Analyzer to view the specified nodes as a synchronous group during SSN voltage noise analysis. This option can be set in the Assignment Editor.
Type
Integer
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- MAX 10
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name SYNCHRONOUS_GROUP -to <to> -entity <entity name> <value>
Analysis & Synthesis Assignments
ADV_NETLIST_OPT_ALLOWED
Specifies whether the Compiler should perform advanced netlist optimizations, such as gate-level retiming or physical synthesis, on the specified node or entity. If this option is set to 'Default', the Compiler duplicates, moves, or changes the synthesis of the node or entity, or allows register retiming during netlist optimization, only if doing so does not negatively affect the timing or performance of the design. If this option is set to 'Always Allow', the Compiler can alter the node or entity, even if doing so affects the timing or performance of the design. Altera does not recommend using this setting. If this option is set to 'Never Allow' the Compiler cannot alter the node or entity.
Type
Enumeration
Values
- Always Allow
- Default
- Never Allow
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ADV_NETLIST_OPT_ALLOWED -entity <entity name> <value> set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name adv_netlist_opt_allowed "always allow" -to reg
ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
Allows the Compiler to infer RAMs of any size, even if they don't meet the current minimum requirements.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION <value> set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -entity <entity name> <value> set_instance_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name allow_any_ram_size_for_recognition off set_instance_assignment -name allow_any_ram_size_for_recognition off -to foo
ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
Allows the Compiler to infer ROMs of any size even if the ROMs do not meet the design's current minimum size requirements.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION <value> set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -entity <entity name> <value> set_instance_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name allow_any_rom_size_for_recognition off set_instance_assignment -name allow_any_rom_size_for_recognition off -to foo
ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
Allows the Compiler to infer shift registers of any size even if they do not meet the design's current minimum size requirements.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION <value> set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION -entity <entity name> <value> set_instance_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name allow_any_shift_register_size_for_recognition off set_instance_assignment -name allow_any_shift_register_size_for_recognition off -to foo
ALLOW_CHILD_PARTITIONS
Specifies whether or not an instance or a section of design hierarchy can contain user partitions.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_CHILD_PARTITIONS -entity <entity name> <value> set_instance_assignment -name ALLOW_CHILD_PARTITIONS -to <to> -entity <entity name> <value>
Example
set_global_assignment -name allow_child_partitions off set_instance_assignment -name allow_child_partitions off -to "sub:inst"
ALLOW_POWER_UP_DONT_CARE
Causes registers that do not have a Power-Up Level logic option setting to power up with a don't care logic level (X). A don't care setting allows the Compiler to change the power-up level of a register to minimize the area of the design.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE <value>
Default Value
On
Example
set_global_assignment -name allow_power_up_dont_care off
See Also
Power-Up Level
ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
Allows the Compiler to take shift registers from different hierarchies of the design and put them in the same RAM.
Type
Enumeration
Values
- Always
- Auto
- Off
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES <value> set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES -entity <entity name> <value> set_instance_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES -to <to> -entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name allow_shift_register_merging_across_hierarchies off set_instance_assignment -name allow_shift_register_merging_across_hierarchies off -to foo
See Also
Auto Shift Register Replacement
ALLOW_SYNCH_CTRL_USAGE
Allows the Compiler to utilize synchronous clear and/or synchronous load signals in normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE <value> set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE -entity <entity name> <value> set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name allow_synch_ctrl_usage off set_instance_assignment -name allow_synch_ctrl_usage off -to foo
See Also
Force Use of Synchronous Clear Signals
ALLOW_XOR_GATE_USAGE
Allows the Compiler to use the XOR gate that exists in a macrocell (that is, in an embedded cell within an Embedded System Block [ESB] that is set to use Product Term mode). This option is ignored if you select 'LUT' or 'ROM' as the setting for the Technology Mapper option.
Type
Boolean
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_XOR_GATE_USAGE <value> set_global_assignment -name ALLOW_XOR_GATE_USAGE -entity <entity name> <value> set_instance_assignment -name ALLOW_XOR_GATE_USAGE -to <to> -entity <entity name> <value>
Default Value
On
Example
set_instance_assignment -name allow_xor_gate_usage off -to clock
ALTERA_A10_IOPLL_BOOTSTRAP
Turns on the A10 IOPLL bootstrap fix
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name ALTERA_A10_IOPLL_BOOTSTRAP <value>
AUTO_CARRY_CHAINS
Allows the Compiler to create carry chains automatically by inserting CARRY_SUM buffers into the design. This option is also required to recognize carry chains in any design containing MAX+PLUS II-style CARRY buffers. The length of the chains is controlled with the Carry Chain Length option. If this option is turned off, CARRY buffers are ignored, but CARRY_SUM buffers are unaffected. The Auto Carry Chains option is ignored if you select 'Product Term' or 'ROM' as the setting for the Technology Mapper option.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_CARRY_CHAINS <value> set_global_assignment -name AUTO_CARRY_CHAINS -entity <entity name> <value> set_instance_assignment -name AUTO_CARRY_CHAINS -to <to> -entity <entity name> <value>
Default Value
On
AUTO_CASCADE_CHAINS
Allows the Compiler to create cascade chains automatically by inserting CASCADE buffers into the design. The length of the chains is controlled with the Cascade Chain Length option. The Auto Cascade Chains option is ignored if you select 'Product Term' or 'ROM' as the setting for the Technology Mapper option.
Type
Boolean
Device Support
- A
- E
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_CASCADE_CHAINS <value> set_global_assignment -name AUTO_CASCADE_CHAINS -entity <entity name> <value> set_instance_assignment -name AUTO_CASCADE_CHAINS -to <to> -entity <entity name> <value>
Default Value
On
AUTO_CLOCK_ENABLE_RECOGNITION
Allows the Compiler to find logic that feeds a register and move the logic to the register's clock enable input port.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION <value> set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -entity <entity name> <value> set_instance_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_clock_enable_replacement off set_instance_assignment -name auto_clock_enable_replacement off -to reg
AUTO_DSP_RECOGNITION
Allows the Compiler to find a multiply-accumulate function or a multiply-add function that can be replaced with the altmult_accum or the altmult_add megafunction.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_DSP_RECOGNITION <value> set_global_assignment -name AUTO_DSP_RECOGNITION -entity <entity name> <value> set_instance_assignment -name AUTO_DSP_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_dsp_recognition off set_instance_assignment -name auto_dsp_recognition off -to foo
AUTO_ENABLE_SMART_COMPILE
Specifies whether the SignalTap II Logic Analyzer should perform a smart compilation if conditions exist in which SignalTap II with incremental routing is used.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE <value>
AUTO_GLOBAL_CLOCK_MAX
Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops as a global clock signal that is made available throughout the device on the global routing paths. If you want to prevent the Compiler from automatically selecting a particular signal as global clock, set the Global Signal option to 'Off' on that signal.
Old Name
Auto Global Clock -- MAX 7000B/7000AE/3000A/7000S/7000A
Type
Boolean
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX <value> set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX -entity <entity name> <value> set_instance_assignment -name AUTO_GLOBAL_CLOCK_MAX -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_global_clock_max off set_instance_assignment -name auto_global_clock_max off -to foo
AUTO_GLOBAL_OE_MAX
Allows the Compiler to choose the signal that feeds the most TRI buffers as a global output enable signal that is made available throughout the device on the global routing paths. If you want to prevent the Compiler from automatically selecting a particular signal as global output enable, set the Global Signal option to 'Off' on that signal.
Old Name
Auto Global Output Enable -- MAX 7000B/7000AE/3000A/7000S/7000A
Type
Boolean
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_GLOBAL_OE_MAX <value> set_global_assignment -name AUTO_GLOBAL_OE_MAX -entity <entity name> <value> set_instance_assignment -name AUTO_GLOBAL_OE_MAX -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_global_oe_max off set_instance_assignment -name auto_global_oe_max off -to foo
AUTO_IMPLEMENT_IN_ROM
Allows the Compiler to automatically implement combinatorial logic in ROM (that is, in an embedded cell within an Embedded System Block [ESB] or Embedded Array Block [EAB] that is set to use ROM mode), to improve speed or area usage. Using ROM in this way can free up logic cells that would otherwise be needed to implement the combinatorial logic. This option is ignored if you select 'Product Term' as the setting for the Technology Mapper option.
Type
Boolean
Device Support
- A
- E
- Mercury
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM <value> set_global_assignment -name AUTO_IMPLEMENT_IN_ROM -entity <entity name> <value> set_instance_assignment -name AUTO_IMPLEMENT_IN_ROM -to <to> -entity <entity name> <value>
Default Value
Off
AUTO_LCELL_INSERTION
Allows the Compiler to insert macrocells into the design. This option is ignored if it is assigned to anything other than a design entity. If you want to prevent the Compiler from automatically inserting macrocells into the design, set the Auto Logic Cell Insertion option to 'Off' on that signal.
Type
Boolean
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_LCELL_INSERTION <value> set_global_assignment -name AUTO_LCELL_INSERTION -entity <entity name> <value> set_instance_assignment -name AUTO_LCELL_INSERTION -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_lcell_insertion off set_instance_assignment -name auto_lcell_insertion off -to foo
AUTO_OPEN_DRAIN_PINS
Allows the Compiler to automatically convert a tri-state buffer with a strong low data input into the equivalent open-drain buffer.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_OPEN_DRAIN_PINS <value> set_global_assignment -name AUTO_OPEN_DRAIN_PINS -entity <entity name> <value> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_open_drain_pins off set_instance_assignment -name auto_open_drain_pins off -to foo
AUTO_PARALLEL_EXPANDERS
Allows the Compiler to automatically create chains of parallel expander product terms. Parallel expanders are available in macrocells, that is, embedded cells within an Embedded System Block [ESB] that is set to use Product Term mode. The length of the chains is controlled with the Parallel Expander Chain Length option. The Auto Parallel Expanders option is ignored if you select 'LUT' or 'ROM' as the setting for the Technology Mapper option.
Type
Boolean
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_PARALLEL_EXPANDERS <value> set_global_assignment -name AUTO_PARALLEL_EXPANDERS -entity <entity name> <value> set_instance_assignment -name AUTO_PARALLEL_EXPANDERS -to <to> -entity <entity name> <value>
Default Value
On
Example
set_instance_assignment -name auto_parallel_expanders on -to clock
AUTO_PARALLEL_SYNTHESIS
Option to enable/disable automatic parallel synthesis. This option can be used to speed up synthesis compile time by using multiple processors when available.
Type
Boolean
Device Support
- Arria 10
- Arria V
- Arria V GZ
- Cyclone V
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS <value>
Default Value
On
Example
set_global_assignment -name auto_parallel_synthesis on
AUTO_RAM_BLOCK_BALANCING
Enables the Compiler to automatically use different memory types when using auto RAM blocks and allows the Compiler to use different RAM partitions with the same memory types.
Type
Boolean
Device Support
- Arria GX
- Arria II GX
- Arria II GZ
- Cyclone
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING <value>
Default Value
On
Example
set_global_assignment -name auto_ram_block_balancing off
AUTO_RAM_RECOGNITION
Allows the Compiler to find a set of registers and logic that can be replaced with the altsyncram or the lpm_ram_dp megafunction. Turning on this option may change the functionality of the design.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_RAM_RECOGNITION <value> set_global_assignment -name AUTO_RAM_RECOGNITION -entity <entity name> <value> set_instance_assignment -name AUTO_RAM_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_ram_recognition off set_instance_assignment -name auto_ram_recognition off -to foo
AUTO_RAM_TO_LCELL_CONVERSION
Allows the Compiler to convert small RAM blocks into logic cells.
Type
Boolean
Device Support
- Arria GX
- Arria II GX
- Arria II GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION <value> set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION -entity <entity name> <value> set_instance_assignment -name AUTO_RAM_TO_LCELL_CONVERSION -to <to> -entity <entity name> <value>
Default Value
Off
AUTO_RESOURCE_SHARING
Allows the Compiler to share hardware resources among many similar, but mutually exclusive, operations in your HDL source code. If you enable this option, the Compiler will merge compatible addition, subtraction, and multiplication operations. By merging operations, this may reduce the area required by your design. Because resource sharing introduces extra muxing and control logic on each shared resource, it may negatively impact the final fmax of your design.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_RESOURCE_SHARING <value> set_global_assignment -name AUTO_RESOURCE_SHARING -entity <entity name> <value> set_instance_assignment -name AUTO_RESOURCE_SHARING -to <to> -entity <entity name> <value>
Default Value
Off
AUTO_ROM_RECOGNITION
Allows the Compiler to find logic that can be replaced with the altsyncram or the lpm_rom megafunction. Turning on this option may change the power-up state of the design.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_ROM_RECOGNITION <value> set_global_assignment -name AUTO_ROM_RECOGNITION -entity <entity name> <value> set_instance_assignment -name AUTO_ROM_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_rom_recognition off set_instance_assignment -name auto_rom_recognition off -to foo
AUTO_SHIFT_REGISTER_RECOGNITION
Allows the Compiler to find a group of shift registers of the same length that can be replaced with the altshift_taps megafunction. The shift registers must all use the same clock and clock enable signals, must not have any other secondary signals, and must have equally spaced taps that are at least three registers apart.
Type
Enumeration
Values
- Always
- Auto
- Off
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION <value> set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -entity <entity name> <value> set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name auto_shift_register_recognition off set_instance_assignment -name auto_shift_register_recognition off -to foo
BLOCK_DESIGN_NAMING
Specify the naming scheme used for the block design. This option is ignored if it is assigned to anything other than a design entity.
Type
Enumeration
Values
- Auto
- MaxPlusII
- QuartusII
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name BLOCK_DESIGN_NAMING -entity <entity name> <value> set_instance_assignment -name BLOCK_DESIGN_NAMING -to <to> -entity <entity name> <value> set_global_assignment -name BLOCK_DESIGN_NAMING <value>
Default Value
Auto
Example
set_global_assignment -name block_design_naming MaxPlusII set_instance_assignment -name block_design_naming MaxPlusII -to top
BOARD
Specifies the board or development kit to use.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name BOARD <value>
CARRY_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized CARRY_SUM buffers. Carry chains that exceed this length are broken into separate chains. (This option also applies to MAX+PLUS II-style CARRY buffers.)
Type
Integer
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name CARRY_CHAIN_LENGTH <value> set_global_assignment -name CARRY_CHAIN_LENGTH -entity <entity name> <value> set_instance_assignment -name CARRY_CHAIN_LENGTH -to <to> -entity <entity name> <value>
Default Value
48
CASCADE_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized CASCADE buffers. Cascade chains that exceed this length are broken into separate chains.
Type
Integer
Device Support
- A
- E
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name CASCADE_CHAIN_LENGTH <value> set_global_assignment -name CASCADE_CHAIN_LENGTH -entity <entity name> <value> set_instance_assignment -name CASCADE_CHAIN_LENGTH -to <to> -entity <entity name> <value>
Default Value
2
CLKLOCKX1_INPUT_FREQ
Creates an internal ClockLock phase-locked loop (PLL) and specifies its frequency. Turning this option on is equivalent to instantiating an altclklock megafunction with either of its ClockBoost parameters set to a value of 1. The CLKLOCKx1 Input Frequency option is provided primarily for backward compatibility with MAX+PLUS II designs. Altera recommends using the MegaWizard Plug-In Manager to instantiate PLLs in new designs. This option is ignored if it is assigned to anything other than an input pin or to a device that does not have the PLL feature.
Type
Frequency
Device Support
- Arria GX
- Arria II GX
- Arria II GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
Notes
None
Syntax
set_instance_assignment -name CLKLOCKX1_INPUT_FREQ -to <to> -entity <entity name> <value>
CYCLONEII_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance, minimize logic usage, or balance high performance with minimal logic usage.
Old Name
Optimization Technique -- Cyclone II/Cyclone III
Type
Enumeration
Values
- Area
- Balanced
- Speed
Device Support
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- MAX 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE <value> set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE -entity <entity name> <value> set_instance_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity name> <value>
Default Value
Balanced
Example
set_global_assignment -name cycloneii_optimization_technique speed
CYCLONE_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance, minimize logic usage, or balance high performance with minimal logic usage.
Old Name
Optimization Technique -- Cyclone
Type
Enumeration
Values
- Area
- Balanced
- Speed
Device Support
Cyclone
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE <value> set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE -entity <entity name> <value> set_instance_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity name> <value>
Default Value
Balanced
Example
set_global_assignment -name cyclone_optimization_technique speed
DEVICE_FILTER_PACKAGE
Package filter for available devices.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_PACKAGE <value>
Default Value
Any
DEVICE_FILTER_PIN_COUNT
Pin count filter for available devices.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_PIN_COUNT <value>
Default Value
Any
DEVICE_FILTER_SPEED_GRADE
Speed grade filter for available devices.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE <value>
Default Value
Any
DEVICE_FILTER_VOLTAGE
Voltage filter for available devices.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_VOLTAGE <value>
DISABLE_DSP_NEGATE_INFERENCING
Allow you to specify whether to use the negate port on an inferred DSP block.
Type
Boolean
Device Support
- Arria 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING -entity <entity name> <value> set_instance_assignment -name DISABLE_DSP_NEGATE_INFERENCING -to <to> -entity <entity name> <value> set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING <value>
Default Value
Off
Example
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING ON set_instance_assignment -name DISABLE_DSP_NEGATE_INFERENCING OFF -to dps1
DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
Specifies whether registers that are in different hierarchies are allowed to be merged if their inputs are the same.
Type
Enumeration
Values
- Auto
- Off
- On
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES <value>
Default Value
Auto
DONT_MERGE_REGISTER
When set to On, this option prevents the specified register from merging with other registers, and prevents other registers from merging with the specified register.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name DONT_MERGE_REGISTER -entity <entity name> <value> set_instance_assignment -name DONT_MERGE_REGISTER -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name dont_merge_register on -to foo
DQS_DELAY
Increases the propagation delay from a DQS I/O pin to the interior of the device. This option is used to center-align the DQS signal to the DQ data signals and should be selected to ensure the desired setup and hold margins across process, voltage, and temperature ranges.
Type
Time
Device Support
- Cyclone
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
Notes
None
Syntax
set_instance_assignment -name DQS_DELAY -to <to> -entity <entity name> <value>
DQS_FREQUENCY
Specifies the DQS system clock frequency by which data is transferred between a device and an external RAM that uses double data rate (DDR). You can specify the desired frequency setting.
Type
Frequency
Device Support
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- MAX 10
- Stratix
- Stratix GX
Notes
None
Syntax
set_instance_assignment -name DQS_FREQUENCY -to <to> -entity <entity name> <value>
DQS_SHIFT
Specifies the interval of arrival between the DQ data signals and DQS signal during data transfer between a device and an external RAM that uses double data rate (DDR). This option is ignored if it is applied to anything other than pins intended for use with the dedicated DDR SDRAM interface.
Type
Enumeration
Values
- Phase of 0 degrees
- Phase of 72 degrees
- Phase of 90 degrees
Device Support
- Stratix
- Stratix GX
Notes
None
Syntax
set_instance_assignment -name DQS_SHIFT -to <to> -entity <entity name> <value>
DQS_SYSTEM_CLOCK
Specifies the clock input used as a frequency reference for a DQS I/O pin. The clock is the pin that drives the DDIO circuitry for the dedicated DDR SDRAM interface.
Type
String
Device Support
- Stratix
- Stratix GX
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name DQS_SYSTEM_CLOCK -to <to> -entity <entity name> <value>
DSE_SYNTH_EXTRA_EFFORT_MODE
Specifies the Design Space Explorer synthesis extra effort mode.
Type
Enumeration
Values
- MODE_1
- MODE_2
- MODE_3
- MODE_4
- MODE_5
- MODE_DEFAULT
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name DSE_SYNTH_EXTRA_EFFORT_MODE <value>
DSP_BLOCK_BALANCING
Allows you to control the conversion of certain DSP block slices during DSP block balancing.
Type
Enumeration
Values
- Auto
- DSP blocks
- Logic Elements
- Off
- Simple 18-bit Multipliers
- Simple Multipliers
- Width 18-bit Multipliers
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name DSP_BLOCK_BALANCING -entity <entity name> <value> set_instance_assignment -name DSP_BLOCK_BALANCING -to <to> -entity <entity name> <value> set_global_assignment -name DSP_BLOCK_BALANCING <value>
Default Value
Auto
Example
set_global_assignment -name dsp_block_balancing "dsp blocks" set_instance_assignment -name dsp_block_balancing "logic elements" -to mult0
EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
Specifies the third-party EDA tool used for design entry/synthesis
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL <value> set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL -entity <entity name> <value>
Default Value
<None>
EDA_INPUT_DATA_FORMAT
Specifies the format of the input data read from other EDA design entry/synthesis tools.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_INPUT_DATA_FORMAT -section_id <section identifier> <value> set_global_assignment -name EDA_INPUT_DATA_FORMAT -entity <entity name> -section_id <section identifier> <value>
Default Value
NONE, requires section identifier
EDA_INPUT_GND_NAME
Specifies the global high signal used in the files generated by the EDA synthesis tool, which is GND.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_INPUT_GND_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_INPUT_GND_NAME -entity <entity name> -section_id <section identifier> <value>
Default Value
GND, requires section identifier
EDA_INPUT_VCC_NAME
Specifies the global power-down signal.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_INPUT_VCC_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_INPUT_VCC_NAME -entity <entity name> -section_id <section identifier> <value>
Default Value
VCC, requires section identifier
EDA_LMF_FILE
Specifies the default Library Mapping File (.lmf) for the current compilation.
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_LMF_FILE -section_id <section identifier> <value> set_global_assignment -name EDA_LMF_FILE -entity <entity name> -section_id <section identifier> <value>
EDA_RUN_TOOL_AUTOMATICALLY
Runs the third-party EDA tool automatically from Quartus Prime when a design is compiled.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -section_id <section identifier> <value> set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_SHOW_LMF_MAPPING_MESSAGES
Determines whether to display messages describing the mappings used in the Library Mapping File.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -section_id <section identifier> <value> set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_VHDL_LIBRARY
Specifies the logical name of a user-defined VHDL design library : physical name.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name EDA_VHDL_LIBRARY -to <to> -section_id <section identifier> <value> set_instance_assignment -name EDA_VHDL_LIBRARY -to <to> -entity <entity name> -section_id <section identifier> <value>
ENABLE_IP_DEBUG
Make certain nodes (for example, important registers, pins, and state machines) visible for all the MegaCore functions in a design. You can use a MegaCore function's nodes to effectively debug the megafunction, particularly when using the megafunction with the SignalTap II Logic Analyzer. The Node Finder, using SignalTap II Logic Analyzer filters, displays all the nodes that Analysis & Synthesis makes visible. When making the debugging nodes visible, Analysis & Synthesis can change the fmax and number of logic cells in MegaCore functions.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ENABLE_IP_DEBUG <value>
Default Value
Off
ENABLE_M512
Enables the compiler to use M512 memory blocks in a design. Because HardCopy II designs do not support M512 memory blocks, this option is useful when you migrate a compiled Stratix II design to a HardCopy II design.
Type
Boolean
Device Support
- Arria GX
- Cyclone
- HardCopy II
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ENABLE_M512 <value>
Example
set_global_assignment -name enable_m512 off
ENABLE_STATE_MACHINE_INFERENCE
Allows the Compiler to infer state machines from Verilog/Vhdl Design Files. The Compiler optimizes state machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler extracts and optimizes state machines in Verilog/VHDL Design Files as regular logic.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE <value>
Default Value
Off
Example
set_global_assignment -name enable_state_machine_inference on
EXTRACT_VERILOG_STATE_MACHINES
Allows the Compiler to extract state machines from Verilog Design Files. The Compiler optimizes state machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler extracts and optimizes state machines in Verilog Design Files as regular logic.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES <value>
Default Value
On
Example
set_global_assignment -name extract_verilog_state_machines off
See Also
State Machine Processing Extract VHDL State Machines
EXTRACT_VHDL_STATE_MACHINES
Allows the Compiler to extract state machines from VHDL Design Files. The Compiler optimizes state machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler extracts and optimizes state machines in VHDL Design Files as regular logic.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES <value>
Default Value
On
Example
set_global_assignment -name extract_vhdl_state_machines off
See Also
State Machine Processing Extract Verilog State Machines
FAMILY
Specifies the device family to use for compilation.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name FAMILY <value>
Default Value
Cyclone V
FORCE_SYNCH_CLEAR
Forces the Compiler to utilize synchronous clear signals in normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name FORCE_SYNCH_CLEAR <value> set_global_assignment -name FORCE_SYNCH_CLEAR -entity <entity name> <value> set_instance_assignment -name FORCE_SYNCH_CLEAR -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name force_synch_clear on set_instance_assignment -name force_synch_clear on -to foo
See Also
Allow Synchronous Control Signals
HDL_INITIAL_FANOUT_LIMIT
Directs Integrated Synthesis to check the initial fan-out of each net in the netlist immediately after elaboration but prior to any netlist optimizations. If the fan-out for a net exceeds the specified limit, then Integrated Synthesis will issue a warning.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name HDL_INITIAL_FANOUT_LIMIT -entity <entity name> <value> set_instance_assignment -name HDL_INITIAL_FANOUT_LIMIT -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name hdl_initial_fanout_limit 100 -to foo
HDL_MESSAGE_LEVEL
Specifies the type of HDL messages you want to view, including messages that display processing errors in the HDL source code. 'Level1' allows you to view only the most important HDL messages. 'Level2' allows you to view most HDL messages, including warning and information based messages. 'Level3' allows you to view all HDL messages, including warning and information based messages and alerts about potential design problems or lint errors.
Type
Enumeration
Values
- Level1
- Level2
- Level3
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name HDL_MESSAGE_LEVEL <value>
Default Value
Level2
HDL_MESSAGE_OFF
Specifies the list of HDL message ids you want to turn off for this project.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
INTEGER_RANGE
10000, 11000
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name HDL_MESSAGE_OFF <value>
HDL_MESSAGE_ON
Specifies the list of HDL message ids you want to turn on for this project.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
INTEGER_RANGE
10000, 11000
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name HDL_MESSAGE_ON <value>
HPS_PARTITION
Specifies whether an entity or instance is a special-purpose partition that models the internals of the Hard Processor System (HPS).
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name HPS_PARTITION -entity <entity name> <value> set_instance_assignment -name HPS_PARTITION -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name hps_partition on -entity hps
IGNORE_CARRY_BUFFERS
Ignores CARRY_SUM buffers that are instantiated in the design. The Ignore CARRY Buffers option is ignored if it is applied to anything other than an individual CARRY_SUM buffer or to a design entity containing CARRY_SUM buffers. (This option also applies to MAX+PLUS II-style CARRY buffers.)
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_CARRY_BUFFERS <value> set_global_assignment -name IGNORE_CARRY_BUFFERS -entity <entity name> <value> set_instance_assignment -name IGNORE_CARRY_BUFFERS -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name ignore_carry_buffers on set_instance_assignment -name ignore_carry_buffers on -to foo
IGNORE_CASCADE_BUFFERS
Ignores CASCADE buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual CASCADE buffer or a design entity containing CASCADE buffers.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_CASCADE_BUFFERS <value> set_global_assignment -name IGNORE_CASCADE_BUFFERS -entity <entity name> <value> set_instance_assignment -name IGNORE_CASCADE_BUFFERS -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name ignore_cascade_buffers on set_instance_assignment -name ignore_cascade_buffers on -to foo
IGNORE_GLOBAL_BUFFERS
Ignores GLOBAL buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual GLOBAL buffer or a design entity containing GLOBAL buffers.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_GLOBAL_BUFFERS <value> set_global_assignment -name IGNORE_GLOBAL_BUFFERS -entity <entity name> <value> set_instance_assignment -name IGNORE_GLOBAL_BUFFERS -to <to> -entity <entity name> <value>
Default Value
Off
IGNORE_LCELL_BUFFERS
Ignores LCELL buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual LCELL buffer or a design entity containing LCELL buffers.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_LCELL_BUFFERS <value> set_global_assignment -name IGNORE_LCELL_BUFFERS -entity <entity name> <value> set_instance_assignment -name IGNORE_LCELL_BUFFERS -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name ignore_lcell_buffers on set_instance_assignment -name ignore_lcell_buffers on -to foo
IGNORE_MAX_FANOUT_ASSIGNMENTS
Directs the Compiler to ignore the Maximum Fan-Out Assignments on a node, an entity, or the whole design. For HCII migration, the Maximum Fan-Out assignments can cause mismatches in Revision Compare. One can remove the Maximum Fan-Out assignments from the project but it is inconvenient/impossible as some assignments are embedded in the HDL sources. One should turn on this assignment to direct Quartus Prime to ignore the Maximum Fan-Out assignments.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS <value> set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS -entity <entity name> <value> set_instance_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS -to <to> -entity <entity name> <value>
Default Value
Off
IGNORE_ROW_GLOBAL_BUFFERS
Ignores ROW GLOBAL buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual GLOBAL buffer or a design entity containing GLOBAL buffers.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS <value> set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS -entity <entity name> <value> set_instance_assignment -name IGNORE_ROW_GLOBAL_BUFFERS -to <to> -entity <entity name> <value>
Default Value
Off
IGNORE_SOFT_BUFFERS
Ignores SOFT buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual SOFT buffer or a design entity containing SOFT buffers.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_SOFT_BUFFERS <value> set_global_assignment -name IGNORE_SOFT_BUFFERS -entity <entity name> <value> set_instance_assignment -name IGNORE_SOFT_BUFFERS -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name ignore_soft_buffers off set_instance_assignment -name ignore_soft_buffers off -to foo
IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
Instructs Analysis & Synthesis to ignore all translate_off/synthesis_off synthesis directives in your Verilog and VHDL design files. You can use this option to disable these synthesis directives and include previously ignored code during elaboration.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF <value>
Default Value
Off
Example
set_global_assignment -name ignore_translate_off_and_synthesis_off on
IGNORE_VERILOG_INITIAL_CONSTRUCTS
Instructs Analysis & Synthesis to ignore initial constructs and variable declaration assignments in your Verilog HDL design files. By default, Analysis & Synthesis derives power-up conditions for your design by elaborating these constructs. This option is provided for backwards compatibility with previous versions of the Quartus Prime software that ignored these constructs by default. You can use this option to restore the previous behavior of your design in the current version of the software.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS <value> set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -entity <entity name> <value> set_instance_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name ignore_verilog_initial_constructs off
IMPLEMENT_AS_CLOCK_ENABLE
Specifies that this node should function as a clock enable signal for one or more registers.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_instance_assignment -name IMPLEMENT_AS_CLOCK_ENABLE -to <to> -entity <entity name> <value>
IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL
Implements the output of a primitive in a logic cell. You can apply this option to a logic function that would not ordinarily be implemented in a logic cell, typically a combinatorial function such as an AND2 gate. Implementing the output of a primitive a logic cell makes it possible to observe its output in simulation and timing analysis. However, because an additional logic cell is used, overall device utilization will increase. This option does not insert an additional logic cell on a function that is already implemented in a logic cell, such as a flipflop. This option is ignored if it is applied to anything other than a primitive.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name implement_as_output_of_logic_cell on -to foo
INFER_RAMS_FROM_RAW_LOGIC
Instructs the Compiler to infer RAM from registers and multiplexers. Some HDL patterns that differ from Altera RAM templates are initially converted into logic. However, these structures function as RAM and, because of that, the Compiler may create an altsyncram megafunction instance for them at a later stage when this assignment is on. With this assignment is turned on, the Compiler may use more device RAM resources and less LABs.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC <value> set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC -entity <entity name> <value> set_instance_assignment -name INFER_RAMS_FROM_RAW_LOGIC -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name infer_rams_from_raw_logic off set_instance_assignment -name infer_rams_from_raw_logic off -to foo
IP_SEARCH_PATHS
Specifies the IP search paths specific to the project.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name IP_SEARCH_PATHS <value>
LCELL_INSERTION
Allows you to insert one or more logic cells between two nodes without changing the design files. The value you assign this option is the number of logic cells you want to insert. The inserted logic cell(s) act as a simple buffer and do not alter the functionality of the design. For more detailed information, go to Quartus Prime online help.
Type
Integer
Device Support
- Arria GX
- Cyclone
- Cyclone II
- A
- E
- HardCopy II
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
Notes
None
Syntax
set_instance_assignment -name LCELL_INSERTION -to <to> -entity <entity name> <value> set_instance_assignment -name LCELL_INSERTION -from <from> -to <to> -entity <entity name> <value>
LIMIT_AHDL_INTEGERS_TO_32_BITS
Specifies whether an AHDL-based design should have a limit on integer size of 32 bits. This option is provided for backward compatibility with pre-2000.09 releases of the Quartus software, which do not support integers larger than 32 bits in AHDL.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS <value>
Default Value
Off
MAX7000_FANIN_PER_CELL
Specifies the maximum fan-in per macrocell. Legal integer values, in percentage terms, range from 20 through 100.
Old Name
Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A
Type
Integer
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX7000_FANIN_PER_CELL <value> set_global_assignment -name MAX7000_FANIN_PER_CELL -entity <entity name> <value> set_instance_assignment -name MAX7000_FANIN_PER_CELL -to <to> -entity <entity name> <value>
Default Value
100
Example
set_global_assignment -name max7000_fanin_per_cell 20 set_instance_assignment -name max7000_fanin_per_cell 20 -to foo
MAX7000_IGNORE_LCELL_BUFFERS
Ignores LCELL buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual LCELL buffer or a design entity containing LCELL buffers.
Old Name
Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A
Type
Enumeration
Values
- Auto
- Off
- On
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS <value> set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS -entity <entity name> <value> set_instance_assignment -name MAX7000_IGNORE_LCELL_BUFFERS -to <to> -entity <entity name> <value>
Default Value
AUTO
Example
set_global_assignment -name max7000_ignore_lcell_buffers on set_instance_assignment -name max7000_ignore_lcell_buffers on -to foo
MAX7000_IGNORE_SOFT_BUFFERS
Ignores SOFT buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual SOFT buffer or a design entity containing SOFT buffers.
Old Name
Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A
Type
Boolean
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS <value> set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS -entity <entity name> <value> set_instance_assignment -name MAX7000_IGNORE_SOFT_BUFFERS -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name max7000_ignore_soft_buffers on set_instance_assignment -name max7000_ignore_soft_buffers on -to foo
MAX7000_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance or minimize logic usage.
Old Name
Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A
Type
Enumeration
Values
- Area
- Balanced
- Speed
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE <value> set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE -entity <entity name> <value> set_instance_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity name> <value>
Default Value
Speed
Example
set_global_assignment -name max7000_optimization_technique balanced
MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of Compiler-synthesized parallel expander product terms.
Old Name
Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A
Type
Integer
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH <value> set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH -entity <entity name> <value> set_instance_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH -to <to> -entity <entity name> <value>
Default Value
4
Example
set_global_assignment -name max7000_parallel_expander_chain_length 3
MAXII_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance, minimize logic usage, or balance high performance with minimal logic usage.
Old Name
Optimization Technique -- MAX II, TSUNAMI_OPTIMIZATION_TECHNIQUE
Type
Enumeration
Values
- Area
- Balanced
- Speed
Device Support
- MAX II
- MAX V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE <value> set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE -entity <entity name> <value> set_instance_assignment -name MAXII_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity name> <value>
Default Value
Balanced
Example
set_global_assignment -name maxii_optimization_technique speed
MAX_AUTO_GLOBAL_REGISTER_CONTROLS
Allows the Compiler to choose the signals that feed the most control signal inputs to flipflops (excluding clock signals) as global signals that are made available throughout the device on the global routing paths. Depending on the target device family, these control signals can include asynchronous clear and load, synchronous clear and load, clock enable, and preset signals.If you want to prevent the Compiler from automatically selecting a particular signal as global register control signal, set the Global Signal option to 'Off' on that signal.
Old Name
Auto Global Register Control Signals -- MAX 7000B/7000AE/3000A/7000S/7000A
Type
Boolean
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS <value> set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS -entity <entity name> <value> set_instance_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name max_auto_global_register_controls off set_instance_assignment -name max_auto_global_register_controls off -to foo
MAX_BALANCING_DSP_BLOCKS
Allows you to specify the maximum number of DSP blocks that the DSP block balancer will assume exist in the current device for each partition. This option overrides the usual method of using the maximum number of DSP blocks the current device supports. For HardCopy II devices, the number of DSP blocks represents the number of DSP blocks used in the equivalent Stratix II device. This option is useful for HardCopy II device migration, where the number of DSP blocks that can be implemented in a HardCopy II device is more than the number of DSP blocks that can be implemented in its equivalent Stratix II device.This option is also useful in incremental compilation to set different DSP block usage limits for different partitions.
Type
Integer
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS <value> set_instance_assignment -name MAX_BALANCING_DSP_BLOCKS -to <to> -entity <entity name> <value>
Default Value
-1 (Unlimited)
Example
set_global_assignment -name max_balancing_dsp_blocks 4 set_instance_assignment -name max_balancing_dsp -to "my_partition_root_entity:my_partition_root_entity_inst"
MAX_FANOUT
Directs the Compiler to control the number of destinations the specified node feeds so the fan-out count does not exceed the value specified as the maximum number of fan-out allowed from the node.
Type
Integer
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_FANOUT -entity <entity name> <value> set_instance_assignment -name MAX_FANOUT -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name max_fanout 10 -to foo
MAX_LABS
Allows you to specify the maximum number of LABs that Analysis & Synthesis should try to utilize for a device. This option overrides the usual method of using the maximum number of LABs the current device supports, when the value is non-negative and is less than the maximum number of LABs available on the current device.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_LABS <value> set_instance_assignment -name MAX_LABS -to <to> -entity <entity name> <value>
Default Value
-1 (Unlimited)
Example
set_global_assignment -name max_labs 100
MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS
Allows you to specify the maximum number of registers that Analysis & Synthesis can use for conversion of uninferred RAMs. You can use this option as a project-wide option or on a specific partition by setting the assignment on the instance name of the partition root. The assignment on a partition overrides the global assignment (if any) for that particular partition. This option prevents synthesis from causing long compilations and running out of memory when many registers are used for uninferred RAMs. Instead of continuing the compilation, the Quartus Prime software issues an error and exits.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS <value> set_instance_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS -to <to> -entity <entity name> <value>
Default Value
-1 (Unlimited)
Example
set_global_assignment -name max_number_of_registers_from_uninferred_rams 2048
MAX_RAM_BLOCKS_M4K
Allows you to specify the maximum number of M4K,M9K,M20K,or M10K memory blocks that the Compiler may use for a device. This option overrides the usual method of using the maximum number of M4K,M9K,M20K, or M10K memory blocks the current device supports, when the value is non-negative and is less than the maximum number of M4K,M9K,M20K, or M10K memory blocks available on the current device.
Type
Integer
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_RAM_BLOCKS_M4K <value> set_instance_assignment -name MAX_RAM_BLOCKS_M4K -to <to> -entity <entity name> <value>
Default Value
-1 (Unlimited)
Example
set_global_assignment -name max_ram_blocks_m4k 4
See Also
Maximum Number of M512 Memory Blocks Maximum Number of M-RAM Memory Blocks
MAX_RAM_BLOCKS_M512
Allows you to specify the maximum number of M512 memory blocks that the Compiler may utilize for a device. This option overrides the usual method of using the maximum number of M512 memory blocks the current device supports, when the value is non-negative and is less than the maximum number of M512 memory blocks available on the current device.
Type
Integer
Device Support
- Arria GX
- Cyclone
- HardCopy II
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_RAM_BLOCKS_M512 <value> set_instance_assignment -name MAX_RAM_BLOCKS_M512 -to <to> -entity <entity name> <value>
Default Value
-1 (Unlimited)
Example
set_global_assignment -name max_ram_blocks_m512 4
See Also
Maximum Number of M4K Memory Blocks Maximum Number of M-RAM Memory Blocks
MAX_RAM_BLOCKS_MRAM
Allows you to specify the maximum number of M-RAM/M144K memory blocks that the Compiler may utilize for a device. This option overrides the usual method of using the maximum number of M-RAM/M144K memory blocks the selected device supports, when the value is non-negative and is less than the maximum number of M-RAM/M144K memory blocks available on the current device.
Type
Integer
Device Support
- Arria GX
- Arria II GX
- Arria II GZ
- Cyclone
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_RAM_BLOCKS_MRAM <value> set_instance_assignment -name MAX_RAM_BLOCKS_MRAM -to <to> -entity <entity name> <value>
Default Value
-1 (Unlimited)
Example
set_global_assignment -name max_ram_blocks_mram 4
See Also
Maximum Number of M512 Memory Blocks Maximum Number of M4K Memory Blocks
MERCURY_CARRY_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized CARRY_SUM buffers. Carry chains that exceed this length are broken into separate chains. (This option also applies to MAX+PLUS II-style CARRY buffers.)
Old Name
Carry Chain Length -- Mercury
Type
Integer
Device Support
Mercury
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH <value> set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH -entity <entity name> <value> set_instance_assignment -name MERCURY_CARRY_CHAIN_LENGTH -to <to> -entity <entity name> <value>
Default Value
48
MERCURY_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance or minimize logic usage.
Old Name
Optimization Technique -- Mercury
Type
Enumeration
Values
- Area
- Speed
Device Support
Mercury
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE <value> set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE -entity <entity name> <value> set_instance_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity name> <value>
Default Value
Area
Example
set_global_assignment -name mercury_optimization_technique speed
MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE
Allows you to specify whether you want the TimeQuest Timing Analyzer to evaluate timing constraints between the write and the read operation of the MLAB memory block. Performing a write and read operation simultaneously at the same address might result in metastability because no timing constraints between those operations exist by default. Turning on this option introduces timing constraints between the write and read operation on the MLAB memory block and thereby avoids metastability issues; however, turning on this option degrades the performance of the MLAB memory blocks. If your design does not perform write and read operations simulataneously at the same address you do not need to set this option.
Type
Boolean
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone V
- HardCopy III
- HardCopy IV
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE -entity <entity name> <value> set_instance_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE -to <to> -entity <entity name> <value> set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE <value>
Default Value
Off
MUX_RESTRUCTURE
Allows the Compiler to reduce the number of logic elements required to implement multiplexers in a design. This option is useful if your design contains buses of fragmented multiplexers. This option repacks multiplexers more efficiently for area, allowing the design to implement multiplexers with a reduced number of logic elements. You can select the 'On' setting to minimize your design area; it will decrease logic element usage but may negatively affect design clock speed (fMAX). You can select the 'Off' to disable multiplexer restructuring; it does not decrease logic element usage and does not affect design clock speed (fMAX). You may select 'Auto' setting to allow the Quartus Prime software to determine whether multiplexer restructuring should be enabled. The Quartus Prime software uses other synthesis settings, for example, the Optimization Technique option, to determine if multiplexer restructuring should be applied to the design; the 'Auto' setting will decrease logic element usage but may negatively affect design clock speed (fMAX).
Type
Enumeration
Values
- Auto
- Off
- On
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MUX_RESTRUCTURE <value> set_global_assignment -name MUX_RESTRUCTURE -entity <entity name> <value> set_instance_assignment -name MUX_RESTRUCTURE -to <to> -entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name mux_restructure off set_instance_assignment -name mux_restructure on -to accel
NOT_GATE_PUSH_BACK
Allows the Compiler to push an inversion (that is, a NOT gate) back through a register and implement it on that register's data input if it is necessary to implement the design. If this option is turned on, a register may power up to an active-high state, so it may need to be explicitly cleared during initial operation of the device. This option is ignored if it is applied to anything other than an individual register or a design entity containing registers. If it is applied to an output pin that is directly fed by a register, it is automatically transferred to that register.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name NOT_GATE_PUSH_BACK -entity <entity name> <value> set_instance_assignment -name NOT_GATE_PUSH_BACK -to <to> -entity <entity name> <value> set_global_assignment -name NOT_GATE_PUSH_BACK <value>
Default Value
On
Example
set_global_assignment -name not_gate_push_back off set_instance_assignment -name not_gate_push_back off -to reg
NUMBER_OF_INVERTED_REGISTERS_REPORTED
Allows you to specify the maximum number of inverted registers that the Synthesis Report should display.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED <value>
Default Value
100
Example
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 200
NUMBER_OF_PROTECTED_REGISTERS_REPORTED
Allows you to specify the maximum number of protected registers that the Synthesis Report should display.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED <value>
Default Value
100
Example
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 200
NUMBER_OF_REMOVED_REGISTERS_REPORTED
Allows you to specify the maximum number of removed registers that the Synthesis Report should display.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED <value>
Default Value
5000
Example
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 200
NUMBER_OF_SWEPT_NODES_REPORTED
Allows you to specify the maximum number of swept nodes that the Synthesis Report displays. A swept node is any node which was eliminated from your design because the Quartus Prime software found the node to be unnecessary.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED <value>
Default Value
5000
Example
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 200
NUMBER_OF_SYNTHESIS_MIGRATION_ROWS
Allows you to specify the maximum number of rows that a report in Synthesis Migration Checks should display.
Type
Integer
Device Support
Arria 10
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS <value>
Default Value
5000
Example
set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 200
OCP_HW_EVAL
Enables or disables OpenCore Plus hardware evaluation feature.
Type
Enumeration
Values
- Disable
- Enable
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name OCP_HW_EVAL <value>
Default Value
Enable
OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance, minimize logic usage, or balance high performance with minimal logic usage.
Old Name
Optimization Technique -- Stratix IV
Type
Enumeration
Values
- Area
- Balanced
- Speed
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone V
- HardCopy IV
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name OPTIMIZATION_TECHNIQUE <value> set_global_assignment -name OPTIMIZATION_TECHNIQUE -entity <entity name> <value> set_instance_assignment -name OPTIMIZATION_TECHNIQUE -to <to> -entity <entity name> <value>
Default Value
Balanced
Example
set_global_assignment -name optimization_technique speed
OPTIMIZE_POWER_DURING_SYNTHESIS
Controls the power-driven compilation setting of Analysis & Synthesis. This option determines how aggressively Analysis & Synthesis optimizes the design for power. If this option is set to 'Off', Analysis & Synthesis does not perform any power optimizations. If this option is set to 'Normal compilation', Analysis & Synthesis performs power optimizations as long as they are not expected to reduce design performance. When this option is set to 'Extra effort', Analysis & Synthesis will perform additional power optimizations which may reduce design performance.
Type
Enumeration
Values
- Extra effort
- Normal compilation
- Off
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS <value> set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS -entity <entity name> <value> set_instance_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS -to <to> -entity <entity name> <value>
Default Value
Normal compilation
Example
set_global_assignment -name optimize_power_during_synthesis off
PARALLEL_EXPANDER_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of Compiler-synthesized parallel expander product terms.
Old Name
Parallel Expander Chain Length -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur
Type
Integer
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH <value> set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH -entity <entity name> <value> set_instance_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH -to <to> -entity <entity name> <value>
Default Value
16
PARALLEL_SYNTHESIS
Option to enable/disable parallel synthesis
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name PARALLEL_SYNTHESIS <value>
Default Value
On
Example
set_global_assignment -name parallel_synthesis on
PARAMETER
Assigns an attribute that determines the logic created or used to implement the function, for example, the width of a bus. Parameters are characteristics that determine the size, behavior, or silicon implementation of a function. Parameter values are inherited from project defaults or higher hierarchical levels unless you make explicit assignments to individual nodes. Parameters are also overridden by explicit logic synthesis and fitting options.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_parameter <value> set_parameter -entity <entity name> <value>
POWER_UP_LEVEL
Causes a register to power up with the specified logic level, either High (1) or Low (0). If this option is specified for an input pin, it is automatically transferred to the register that is driven by the pin if the following conditions are present: (1) there is no intervening logic, other than inversion, between the pin and the register; (2) the input pin drives the data input of the register; and (3) the input pin does not fan-out to any other logic. If this option is specified for an output or bidirectional pin, it is automatically transferred to the register that feeds the pin if: (1) there is no intervening logic, other than inversion, between the register and the pin; and (2) the register does not fan-out to any other logic. You can assign this option to any register, or to a pin with any logic configuration other than those described above. You can also assign this option to a design entity containing registers if you want to set the power level for all registers in the design entity. In order for the register to power up with the specified logic level, the Compiler may perform NOT Gate Push-Back on the register.
Type
Enumeration
Values
- High
- Low
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name POWER_UP_LEVEL -entity <entity name> <value> set_instance_assignment -name POWER_UP_LEVEL -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name power_up_level low -to foo
See Also
Power-Up Don't Care
PRESERVE_FANOUT_FREE_NODE
Prevents a register that has no fan-out from being removed during synthesis.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
None
Syntax
set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name preserve_fanout_free_node on -to reg
PRESERVE_REGISTER
Prevents a register from minimizing away during synthesis and prevents sequential netlist optimizations. Sequential netlist optimizations can eliminate redundant registers and registers with constant drivers.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name PRESERVE_REGISTER -entity <entity name> <value> set_instance_assignment -name PRESERVE_REGISTER -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name preserve_register on -to foo
PRE_MAPPING_RESYNTHESIS
Specifies that the Quartus Prime software should perform a resynthesis optimization step immediately before technology mapping. The 'On' setting increases design performance; it will increase design clock speed (fMAX) but may also slightly increase logic element usage and compilation time. The 'Off' selection disables this optimization.
Type
Boolean
Device Support
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- MAX 10
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name PRE_MAPPING_RESYNTHESIS <value>
Default Value
Off
PRPOF_ID
Specifies whether a register is a unique partial reconfiguration bitstream identifier. The same identifier value will be used to generate the partial reconfiguration bitstream.
Type
Boolean
Device Support
- Arria 10
- Arria V
- Arria V GZ
- Cyclone V
- Stratix V
Notes
This assignment is included in the Fitter report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name PRPOF_ID -entity <entity name> <value> set_instance_assignment -name PRPOF_ID -to <to> -entity <entity name> <value> set_global_assignment -name PRPOF_ID <value>
Default Value
Off
Example
set_instance_assignment -name prpof_id on -to reg
RBCGEN_CRITICAL_WARNING_TO_ERROR
To convert Quartus Prime critical warning to error.
Type
Boolean
Device Support
- Arria 10
- Arria V
- Arria V GZ
- Cyclone V
- Stratix V
Notes
None
Syntax
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR <value>
Default Value
On
REMOVE_DUPLICATE_REGISTERS
Removes a register if it is identical to another register. If two registers generate the same logic, the second one will be deleted and the first one will be made to fan out to the second one's destinations. Also, if the deleted register has different logic option assignments, they will be ignored. This option is useful if you wish to prevent the Compiler from removing duplicate registers that you have used deliberately. You can do this by setting the option to Off. This option is ignored if it is applied to anything other than an individual register or a design entity containing registers.
Old Name
DUPLICATE_REGISTER_EXTRACTION
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS <value> set_global_assignment -name REMOVE_DUPLICATE_REGISTERS -entity <entity name> <value> set_instance_assignment -name REMOVE_DUPLICATE_REGISTERS -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name remove_duplicate_registers off set_instance_assignment -name remove_duplicate_registers off -to foo
REMOVE_REDUNDANT_LOGIC_CELLS
Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option on optimizes a circuit for area and speed. This option is ignored if it is applied to anything other than a design entity.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -entity <entity name> <value> set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -to <to> -entity <entity name> <value> set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS <value>
Default Value
Off
Example
set_global_assignment -name remove_redundant_logic_cells on set_instance_assignment -name remove_redundant_logic_cells on -to node
REPORT_CONNECTIVITY_CHECKS
Specifies whether the synthesis report should include the panels in the Connectivity Checks folder
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS <value>
Default Value
On
REPORT_PARAMETER_SETTINGS
Specifies whether the synthesis report should include the panels in the Parameter Settings by Entity Instance folder
Old Name
SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_PARAMETER_SETTINGS <value>
Default Value
On
REPORT_PARAMETER_SETTINGS_PRO
Specifies whether the synthesis report should include the panels in the Parameter Settings by Entity Instance folder
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO <value>
Default Value
On
REPORT_SOURCE_ASSIGNMENTS
Specifies whether the synthesis report should include the panels in the Source Assignments folder
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS <value>
Default Value
On
REPORT_SOURCE_ASSIGNMENTS_PRO
Specifies whether the synthesis report should include the panels in the Source Assignments folder
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO <value>
Default Value
On
RESYNTHESIS_OPTIMIZATION_EFFORT
Specifies whether the resynthesis tool should focus on fmax or area during resynthesis.
Type
Enumeration
Values
- Low
- Normal
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT -section_id <section identifier> <value> set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT -entity <entity name> -section_id <section identifier> <value>
Default Value
Normal, requires section identifier
RESYNTHESIS_PHYSICAL_SYNTHESIS
Specifies the physical synthesis level for resynthesis.
Type
Enumeration
Values
- ADVANCED
- Normal
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS -section_id <section identifier> <value> set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS -entity <entity name> -section_id <section identifier> <value>
Default Value
Normal, requires section identifier
RESYNTHESIS_RETIMING
Specifies the paths on which retiming will be performed: all paths, register-to-register paths only, or none.
Type
Enumeration
Values
- CORE
- Full
- Off
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name RESYNTHESIS_RETIMING -section_id <section identifier> <value> set_global_assignment -name RESYNTHESIS_RETIMING -entity <entity name> -section_id <section identifier> <value>
Default Value
FULL, requires section identifier
SAFE_STATE_MACHINE
Tells the compiler to implement state machines that can recover gracefully from an illegal state.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SAFE_STATE_MACHINE -entity <entity name> <value> set_instance_assignment -name SAFE_STATE_MACHINE -to <to> -entity <entity name> <value> set_global_assignment -name SAFE_STATE_MACHINE <value>
Default Value
Off
Example
set_global_assignment -name safe_state_machine on set_instance_assignment -name safe_state_machine on -to foo
See Also
State Machine Processing Extract Verilog State Machines Extract VHDL State Machines
SAVE_DISK_SPACE
Saves disk space by reducing the number of node names available for entering assignments, simulation, timing analysis, reporting, etc.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SAVE_DISK_SPACE <value>
Default Value
On
SEARCH_PATH
Specifies the path name of a user-defined library.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name SEARCH_PATH <value>
SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL
Allows the Compiler to find a group of shift registers of the same length that can be replaced with the altshift_taps megafunction. The shift registers must all use the same aclr signals, must not have any other secondary signals, and must have equally spaced taps that are at least three registers apart. To use this option, you must turn on the Auto Shift Register Replacement logic option.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL <value> set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL -entity <entity name> <value> set_instance_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name shift_register_recognition_aclr_signal off set_instance_assignment -name shift_register_recognition_aclr_signal off -to foo
SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES
Allows the Compiler to skip the fitting stage during smart recompilation when design changes may affect timing requirements. This option is available only for changes to Cyclone, Stratix, and Stratix GX PLL parameters, and Stratix GX gigabit transceiver block (GXB) parameters.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES <value>
Default Value
Off
STATE_MACHINE_PROCESSING
Specifies the processing style used to compile a state machine. You can use your own 'User-Encoded' style, or select 'One-Hot', 'Minimal Bits', 'Gray', 'Johnson', 'Sequential' or 'Auto' (Compiler-selected) encoding.
Type
Enumeration
Values
- Auto
- Gray
- Johnson
- Minimal Bits
- One-Hot
- Sequential
- User-Encoded
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name STATE_MACHINE_PROCESSING -entity <entity name> <value> set_instance_assignment -name STATE_MACHINE_PROCESSING -to <to> -entity <entity name> <value> set_global_assignment -name STATE_MACHINE_PROCESSING <value>
Default Value
Auto
Example
set_global_assignment -name state_machine_processing "one-hot" set_instance_assignment -name state_machine_processing "one-hot" -to foo
See Also
Extract Verilog State Machines Extract VHDL State Machines
STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT
Directs the compiler to not modify the Force Signal Detect and Signal Threshold Select parameters on GXB Receiver channels
Type
Boolean
Device Support
- Arria GX
- Stratix GX
- Stratix II GX
Notes
None
Syntax
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT <value>
Default Value
Off
STRATIXII_CARRY_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized CARRY_SUM buffers. Carry chains that exceed this length are broken into separate chains. (This option also applies to MAX+PLUS II-style CARRY buffers.)
Old Name
ARMSTRONG_CARRY_CHAIN_LENGTH, Carry Chain Length -- Stratix II/Stratix III
Type
Integer
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH <value> set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH -entity <entity name> <value> set_instance_assignment -name STRATIXII_CARRY_CHAIN_LENGTH -to <to> -entity <entity name> <value>
Default Value
70
STRATIXII_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance, minimize logic usage, or balance high performance with minimal logic usage.
Old Name
ARMSTRONG_OPTIMIZATION_TECHNIQUE, Optimization Technique -- Stratix II/III/HardCopy II/Stratix II GX/Arria GX
Type
Enumeration
Values
- Area
- Balanced
- Speed
Device Support
- Arria GX
- HardCopy II
- HardCopy III
- Stratix II
- Stratix II GX
- Stratix III
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE <value> set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE -entity <entity name> <value> set_instance_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity name> <value>
Default Value
Balanced
Example
set_global_assignment -name stratixii_optimization_technique speed
STRATIX_CARRY_CHAIN_LENGTH
Specifies the maximum allowable length of a chain of both user-entered and Compiler-synthesized CARRY_SUM buffers. Carry chains that exceed this length are broken into separate chains. (This option also applies to MAX+PLUS II-style CARRY buffers.)
Old Name
Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III
Type
Integer
Device Support
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH <value> set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH -entity <entity name> <value> set_instance_assignment -name STRATIX_CARRY_CHAIN_LENGTH -to <to> -entity <entity name> <value>
Default Value
70
STRATIX_OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance, minimize logic usage, or balance high performance with minimal logic usage.
Old Name
Optimization Technique -- Stratix/Stratix GX, YEAGER_OPTIMIZATION_TECHNIQUE
Type
Enumeration
Values
- Area
- Balanced
- Speed
Device Support
- Stratix
- Stratix GX
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE <value> set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE -entity <entity name> <value> set_instance_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE -to <to> -entity <entity name> <value>
Default Value
Balanced
Example
set_global_assignment -name stratix_optimization_technique speed
STRICT_RAM_RECOGNITION
When this option is ON, the Compiler is only allowed to replace RAM if the hardware matches the design exactly.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name STRICT_RAM_RECOGNITION <value> set_global_assignment -name STRICT_RAM_RECOGNITION -entity <entity name> <value> set_instance_assignment -name STRICT_RAM_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name strict_ram_recognition on set_global_assignment -name strict_ram_recognition on -to foo
SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
This setting specifies the maximum number of registers in a row to be considered as a synchronization chain. Synchronization chains are sequences of registers with the same clock, no fanout in between, such that the first register is fed by a pin, or by logic in another clock domain. These registers will be considered for metastability analysis (available for some families), and are also protected from optimizations such as retiming. When gate-level retiming is turned on, these registers will not be moved. The default length is device-specific.
Old Name
ADV_NETLIST_OPT_METASTABLE_REGS
Type
Integer
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH <value> set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -entity <entity name> <value> set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -to <to> -entity <entity name> <value>
SYNTHESIS_EFFORT
Controls the synthesis trade-off between compilation speed and performance and area. The default is 'Auto'. You can select 'Fast' for faster compilation speed at the cost of performance and area.
Type
Enumeration
Values
- Auto
- Fast
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTHESIS_EFFORT <value>
Default Value
Auto
Example
set_global_assignment -name synthesis_effort fast
SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
When this option is set to On, synthesis will keep the synchronous clear/preset behavior when remap I/O wysiwyg primitives (from other device families) using DDIO INPUT feature to the targeted device family.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER -entity <entity name> <value> set_instance_assignment -name SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER -to <to> -entity <entity name> <value> set_global_assignment -name SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER <value>
Example
set_global_assignment -name synthesis_keep_synch_clear_preset_behavior_in_unmapper on set_instance_assignment -name synthesis_keep_synch_clear_preset_behavior_in_unmapper on -to foo
SYNTH_CLOCK_MUX_PROTECTION
Causes the multiplexers in the clock network to be decomposed to 2to1 multiplexer trees, and protected from being merged with, or transferred to, other logic. This option helps the TimeQuest timing analyzer to understand clock behavior.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION <value>
Default Value
On
Example
set_global_assignment -name synth_clock_mux_protection off
SYNTH_GATED_CLOCK_CONVERSION
Automatically converts gated clocks in the design to use clock enable pins if clock enable pins are not used in the original design. Clock gating logic can contain AND, OR, MUX, and NOT gates. Turning on this option may increase memory use and overall run time. You must use the TimeQuest Timing Analyzer for timing analysis, and you must define all base clocks in Synopsys Design Constraints (SDC) format.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION -entity <entity name> <value> set_instance_assignment -name SYNTH_GATED_CLOCK_CONVERSION -to <to> -entity <entity name> <value> set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION <value>
Default Value
Off
Example
set_global_assignment -name synth_gated_clock_conversion on set_instance_assignment -name synth_gated_clock_conversion on -to foo
SYNTH_MESSAGE_LEVEL
Specifies the type of Analysis & Synthesis messages you want to view. Setting this option to 'Low' allows you to view only the most important Analysis & Synthesis messages. Setting this option to 'Medium' allows you to view most Analysis & Synthesis messages, but hides the detailed messages in Analysis & Synthesis report. Setting this option to 'High' allows you to view all Analysis & Synthesis messages.
Type
Enumeration
Values
- High
- Low
- Medium
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTH_MESSAGE_LEVEL <value>
Default Value
Medium
SYNTH_PROTECT_SDC_CONSTRAINT
Causes SDC constraint checking in register merging. It helps to maintain the validity of SDC constraints through compilation.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT <value>
Default Value
Off
Example
set_global_assignment -name synth_protect_sdc_constraint on
SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM
Specifies whether RAM, ROM, and shift-register inference should take the design and device resources into account.
Type
Boolean
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix
- Stratix II
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM <value>
Example
set_global_assignment -name synth_resource_aware_inference_for_block_ram on
SYNTH_TIMING_DRIVEN_SYNTHESIS
Allows synthesis to use timing information during synthesis to better optimize the design.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS <value> set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -entity <entity name> <value> set_instance_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -to <to> -entity <entity name> <value>
Example
set_global_assignment -name synth_timing_driven_synthesis on
TOP_LEVEL_ENTITY
Specifies the full hierarchichal path of the entity that is the focus of the current compilation or simulation.
Old Name
FOCUS_ENTITY_NAME
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name TOP_LEVEL_ENTITY <value>
TRUE_WYSIWYG_FLOW
Specifies that the Quartus Prime software should not try to optimize this WYSIWYG design.
Type
Boolean
Device Support
- Cyclone
- A
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name TRUE_WYSIWYG_FLOW <value>
Default Value
Off
USER_LIBRARIES
Specifies the pathnames of user-defined libraries.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name USER_LIBRARIES <value>
USE_GENERATED_PHYSICAL_CONSTRAINTS
Specifies the physical constraints file generated by the resynthesis tool to be used by the Quartus Prime software
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS -section_id <section identifier> <value> set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier
USE_HIGH_SPEED_ADDER
Tells the Compiler whether to use high speed adder circuitry to implement arithmetic functions or not. This option is useful for improving the performance of the design when set to On and minimizing the total number of HCells used in the design when set to Off. This option applies to HardCopy series devices only. It can only be used as a project-wide option. This option defaults to Auto, which has the same behavior as On when the Optimization Technique is set to Speed or Balanced, and as Off when the Optimization Technique is set to Area.
Type
Enumeration
Values
- Auto
- Off
- On
Device Support
- HardCopy II
- HardCopy III
- HardCopy IV
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name USE_HIGH_SPEED_ADDER <value> set_global_assignment -name USE_HIGH_SPEED_ADDER -entity <entity name> <value> set_instance_assignment -name USE_HIGH_SPEED_ADDER -to <to> -entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name use_high_speed_adder off
USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING
Directs the compiler to use LogicLock constraints during DSP and RAM balancing.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING <value>
Default Value
On
Example
set_global_assignment -name use_logiclock_constraints_in_balancing on
VERILOG_CONSTANT_LOOP_LIMIT
Defines the iteration limit for Verilog loops with loop conditions that evaluate to compile-time constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust memory or trap the software in an actual infinite loop.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT <value> set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -entity <entity name> <value> set_instance_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -to <to> -entity <entity name> <value>
Default Value
5000
Example
set_global_assignment -name verilog_constant_loop_limit 3000
VERILOG_INPUT_VERSION
Specifies the language dialect to use when processing Verilog Design Files: Verilog-1995 (IEEE Std. 1364-1995), Verilog-2001 (IEEE Std. 1364-2001), or SystemVerilog-2005 (IEEE Std. 1800-2005). Verilog 2001 is the default dialect.
Type
Enumeration
Values
- SystemVerilog_2005
- Verilog_1995
- Verilog_2001
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VERILOG_INPUT_VERSION <value>
Default Value
Verilog_2001
VERILOG_LMF_FILE
Specifies the default Library Mapping File (.lmf) for the current compilation.
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VERILOG_LMF_FILE <value>
VERILOG_MACRO
Defines Verilog HDL macro - same as `define directive
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name VERILOG_MACRO <value>
VERILOG_NON_CONSTANT_LOOP_LIMIT
Defines the iteration limit for Verilog loops with loop conditions that do not evaluate to compile-time constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust memory or trap the software in an actual infinite loop.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT <value> set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -entity <entity name> <value> set_instance_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -to <to> -entity <entity name> <value>
Default Value
250
Example
set_global_assignment -name verilog_non_constant_loop_limit 3000
VERILOG_SHOW_LMF_MAPPING_MESSAGES
Determines whether to display messages describing the mappings used in the Library Mapping File.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES <value>
VHDL_INPUT_LIBRARY
Specifies the logical name of a user-defined VHDL design library : physical name.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name VHDL_INPUT_LIBRARY -to <to> <value>
VHDL_INPUT_VERSION
Specifies the language dialect to use when processing VHDL Design Files: VHDL-1987 (IEEE Std 1076-1987), VHDL-1993 (IEEE Std 1076-1993) or VHDL-2008 (IEEE Std 1076-2008). VHDL-1993 is the default dialect.
Type
Enumeration
Values
- VHDL_1987
- VHDL_1993
- VHDL_2008
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VHDL_INPUT_VERSION <value>
Default Value
VHDL_1993
VHDL_LMF_FILE
Specifies the default Library Mapping File (.lmf) for the current compilation.
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VHDL_LMF_FILE <value>
VHDL_SHOW_LMF_MAPPING_MESSAGES
Determines whether to display messages describing the mappings used in the Library Mapping File.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES <value>
Assembler Assignments
ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE
Allows signaldetect to propogate from PCS to the core, which will be blocked if you fix the CDR lockup issue. This is because a PMA direct route is unavailable in Arria II GX devices.
Type
Boolean
Device Support
Arria II GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE <value> set_instance_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE -to <to> <value>
Default Value
Off
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE
Automatically increments the JTAG user code in the second and subsequent configuration devices if the target device requires multiple configuration devices.
Old Name
AUTO_INCREMENT_USER_JTAG_CODE
Type
Boolean
Device Support
- Cyclone
- E
- Mercury
- Stratix
- Stratix GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE <value>
Default Value
On
AUTO_RESTART_CONFIGURATION
Directs the device to restart the configuration process automatically if a data error is encountered. If this option is turned off, you must externally direct the device to restart the configuration process if an error occurs.
Old Name
Auto restart on configuration error
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_RESTART_CONFIGURATION <value>
Default Value
On
CLOCK_SOURCE
Specifies whether the configuration device generates an internal clock or applies an external clock.
Type
Enumeration
Values
- External
- Internal
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name CLOCK_SOURCE <value>
Default Value
Internal
COMPRESSION_MODE
Allows you to compress SRAM Object Files (.sof) stored in a Programmer Object File (.pof) for a configuration device.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name COMPRESSION_MODE <value>
Default Value
Off
CONFIGURATION_CLOCK_DIVISOR
Specifies the clock frequency divisor, which is used to determine the period of the system clock.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR <value>
Default Value
1
CONFIGURATION_CLOCK_FREQUENCY
Specifies the clock frequency of the configuration device.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY <value>
Default Value
10 MHz
CYCLONEIII_CONFIGURATION_DEVICE
Specifies the configuration device that you want to use as the means of configuring the target device.
Type
String
Device Support
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- MAX 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE <value>
Default Value
Auto
CYCLONEII_M4K_COMPATIBILITY
Direct Quartus Prime software to produce programming files that are compatible with both rev A and rev B silicon. This option applies only to Cyclone II device family. Please see the Cyclone II FPGA Family Errata Sheet for more details.
Type
Boolean
Device Support
Cyclone II
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY <value>
Default Value
On
CYCLONE_CONFIGURATION_DEVICE
Specifies the configuration device that you want to use as the means of configuring the target Cyclone device.
Type
String
Device Support
Cyclone
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE <value>
Default Value
Auto
DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE
Disables the nCS and OE internal pull-ups on the configuration device(s).
Old Name
DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE
Type
Boolean
Device Support
- E
- Mercury
- Stratix
- Stratix GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE <value>
Default Value
Off
ENABLE_ADV_SEU_DETECTION
Allows you to enable the Advanced SEU Detection compiler to generate design SEU sensitivity map file. If this option is turned on, the SMH file will be generated.
Type
Boolean
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone V
- Stratix III
- Stratix IV
- Stratix V
Notes
None
Syntax
set_global_assignment -name ENABLE_ADV_SEU_DETECTION <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_ADV_SEU_DETECTION ON
See Also
PARTITION_ASD_REGION_ID
ENABLE_AUTONOMOUS_PCIE_HIP
Directs the device to release the PCIe HIP after the periphery is configured and before core configuration is completed. This option doesn't take effect in CvP Init mode since the periphery automatically comes up first, all other modes bring the PCIe HIP up first when this option is selected.
Old Name
Auto restart on configuration error
Type
Boolean
Device Support
- Arria 10
- Arria V
- Arria V GZ
- Cyclone V
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP <value>
Default Value
Off
ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
Allows an EPC1 configuration device to operate in a 3.3 V environment.
Type
Boolean
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE <value>
Default Value
On
ENABLE_OCT_DONE
This option controls whether the INIT_DONE signal will be gated by OCT_DONE signal which indicates the Power-Up OCT calibration is completed. If this option is turned off, the INIT_DONE signal is not gated by the OCT_DONE signal.
Type
Boolean
Device Support
- Arria 10
- Arria II GX
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- MAX 10
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_OCT_DONE <value>
ENABLE_SPI_MODE_CHECK
Configure device in Active Serial mode after power-up.
Type
Boolean
Device Support
MAX 10
Notes
None
Syntax
set_global_assignment -name ENABLE_SPI_MODE_CHECK <value>
Default Value
Off
EN_SPI_IO_WEAK_PULLUP
Set SPI IO pins to week pull-up prior to usermode, otherwise SPI IO pins will be input tri-stated
Type
Boolean
Device Support
MAX 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EN_SPI_IO_WEAK_PULLUP <value>
Default Value
On
EN_USER_IO_WEAK_PULLUP
Set IO to week pull-up prior to usermode, otherwise IO will be input tri-stated
Type
Boolean
Device Support
MAX 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EN_USER_IO_WEAK_PULLUP <value>
Default Value
On
EPROM_USE_CHECKSUM_AS_USERCODE
Uses the checksum value from the Programmer Object File (.pof) as the JTAG user code.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE <value>
Default Value
Off
EXTERNAL_FLASH_FALLBACK_ADDRESS
Specifies the fallback image location address in EPCQ configuration device when external fallback is enabled.
Type
String
Device Support
MAX 10
Notes
None
Syntax
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS <value>
Default Value
0
See Also
FALLBACK_TO_EXTERNAL_FLASH
FALLBACK_TO_EXTERNAL_FLASH
During power up, if the default internal configuration image is corrupted, the device will look for primary fallback image in internal flash, if it is also corrupted and if secondary fallback is been enabled, image store in external Flash will be use. This option is only valid when Internal Configuration scheme is selected and to be use with multi images.
Type
Boolean
Device Support
MAX 10
Notes
None
Syntax
set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH <value>
Default Value
Off
FORCE_SSMCLK_TO_ISMCLK
Force SSM clock to use internal oscillator clock.
Type
Boolean
Device Support
MAX 10
Notes
None
Syntax
set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK <value>
Default Value
On
GENERATE_HEX_FILE
Generates a Hexadecimal (Intel-format) Output File (.hexout) containing configuration data that can be programmed into a parallel data source, such as an EPROM or a mass storage device, which then in turn configures the target device.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name GENERATE_HEX_FILE <value>
Default Value
Off
GENERATE_PMSF_FILES
Generate Partial-Masked SOF file (.pmsf) containing both configuration data and region definitions that can be used to re-configure a device region. If this option is turned on, the Partial-Masked SOF files (.pmsf) will be generated instead of Mask Settings files (.msf).
Type
Boolean
Device Support
- Arria 10
Syntax
set_global_assignment -name GENERATE_PMSF_FILES <value>
Default Value
On
Example
set_global_assignment -name GENERATE_PMSF_FILES ON
See Also
GENERATE_PMSF_FILES
GENERATE_RBF_FILE
Generates a Raw Binary File (.rbf) containing configuration data that an intelligent external controller can use to configure the target device.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name GENERATE_RBF_FILE <value>
Default Value
Off
GENERATE_TTF_FILE
Generates a Tabular Text File (.ttf) containing configuration data that an intelligent external controller can use to configure the target device.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name GENERATE_TTF_FILE <value>
Default Value
Off
HARDCOPYII_POWER_ON_EXTRA_DELAY
Directs HardCopy chip to wait before INIT_DONE pin goes high and before the chip is in user mode.
Type
Enumeration
Values
- Off
- Wait 1 ms
- Wait 2 ms
- Wait 4 ms
- Wait 50 ms
- Wait 8 ms
Device Support
- HardCopy II
- HardCopy III
- HardCopy IV
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY <value>
Default Value
Off
HEXOUT_FILE_COUNT_DIRECTION
Specifies the count direction for the data in a Hexadecimal (Intel-Format) Output File (.hexout) as up or down.
Old Name
HEX_FILE_COUNT_UP_DOWN
Type
Enumeration
Values
- Down
- Up
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION <value>
Default Value
Up
HEXOUT_FILE_START_ADDRESS
Specifies the starting memory address for a Hexadecimal (Intel-Format) Output File (.hexout).
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name HEXOUT_FILE_START_ADDRESS <value>
Default Value
0
MAX7000S_JTAG_USER_CODE
Specifies user-defined information about the target device. The JTAG user code is an extension of the option register. This data can be read with the JTAG USERCODE instruction.
Type
String
Device Support
- MAX7000A
- MAX7000S
Notes
None
Syntax
set_global_assignment -name MAX7000S_JTAG_USER_CODE <value>
Default Value
FFFF
MAX7000_JTAG_USER_CODE
Specifies user-defined information about the target device. The JTAG user code is an extension of the option register. This data can be read with the JTAG USERCODE instruction.
Type
String
Device Support
- MAX3000A
- MAX7000AE
- MAX7000B
Notes
None
Syntax
set_global_assignment -name MAX7000_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
MAX7000_USE_CHECKSUM_AS_USERCODE
Sets the JTAG user code to match the checksum value of the device programming file. The programming file is a Programmer Object File (.pof) for non-volatile devices, such as MAX II devices, or an SRAM Object File (.sof) for SRAM-based devices. If you turn this option on, the JTAG user code option is not available.
Type
Boolean
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE <value>
Default Value
Off
MERCURY_CONFIGURATION_DEVICE
Specifies the configuration device that you want to use as the means of configuring the target Mercury device.
Old Name
CONFIGURATION_DEVICE_DALI
Type
String
Device Support
Mercury
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE <value>
Default Value
Auto
MERCURY_CONFIG_DEVICE_JTAG_USER_CODE
Specifies user-defined information about the configuration device. The JTAG user code is an extension of the option register. This data can be read with the JTAG USERCODE instruction.
Old Name
CONFIG_DEVICE_JTAG_USER_CODE_DALI
Type
String
Device Support
Mercury
Notes
None
Syntax
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
MERCURY_JTAG_USER_CODE
Specifies user-defined information about the target device. The JTAG user code is an extension of the option register. This data can be read with the JTAG USERCODE instruction.
Old Name
JTAG_USER_CODE_DALI
Type
String
Device Support
Mercury
Notes
None
Syntax
set_global_assignment -name MERCURY_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
ON_CHIP_BITSTREAM_DECOMPRESSION
Allows the device to accept and decompress bitstreams during configuration. Produces compressed bitstreams and enables bitstream decompression.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION <value>
Default Value
On
POF_VERIFY_PROTECT
Protect configuration data in internal flash from being read through JTAG
Type
Boolean
Device Support
MAX 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name POF_VERIFY_PROTECT <value>
Default Value
Off
POR_SCHEME
Specifies device Power On Reset (POR) scheme.
Type
Enumeration
Values
- Fast POR delay
- Instant ON
- Slow POR delay
Device Support
MAX 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name POR_SCHEME <value>
Default Value
Instant ON
PR_BASE_MSF
Specify block name and path of base revision MSF file for mask comparison in a PR project.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name PR_BASE_MSF <value>
PR_BASE_SOF
Specify path of base revision SOF file for bit settings comparison in a PR project.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name PR_BASE_SOF <value>
PR_SKIP_BASE_CHECK
Disable mask comparison and logic verification for a reconfigurable partition in a PR project.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name PR_SKIP_BASE_CHECK <value>
PWRMGT_VOLTAGE_OUTPUT_FORMAT
Specifies the output format when operation mode is PMBus master.
Type
Enumeration
Values
- Auto discovery
- Direct format
- Linear format
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT <value>
Default Value
Auto discovery
RELEASE_CLEARS_BEFORE_TRI_STATES
Directs the device to release the clear signal on registered logic cells and I/O cells before releasing the output enable override on tri-state buffers. If this option is turned off, the output enable signals are released before the clear overrides are released.
Old Name
Release clears before tri-states
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- A
- E
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES <value>
Default Value
Off
RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND
Reserves all unused pins on the target device in one of three states: as inputs that are tri-stated, or as outputs that drive an unspecified signal.
Old Name
RESERVED_ALL_UNUSED_PINS_NO_OUTPUT_GND
Type
Enumeration
Values
- As input tri-stated
- As output driving an unspecified signal
Device Support
- MAX3000A
- MAX7000A
- MAX7000S
Notes
None
Syntax
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND <value>
Default Value
As output driving an unspecified signal
SECURITY_BIT
Enables the security bit support, which prevents a device from being examined and reprogrammed.
Type
Boolean
Device Support
- MAX II
- MAX V
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECURITY_BIT <value>
Default Value
Off
STRATIXII_CONFIGURATION_DEVICE
Specifies the configuration device that you want to use as the means of configuring the target device.
Old Name
STRATIX_II_CONFIGURATION_DEVICE
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone V
- HardCopy III
- HardCopy IV
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE <value>
Default Value
Auto
STRATIXII_MRAM_COMPATIBILITY
Direct Quartus Prime software to produce programming files that are compatible with both rev A and rev B silicon. This option applies only to EP2S30, EP2S90, EP2S130, EP2S180. Please see the Stratix II Errata Sheet for more details.
Old Name
STRATIXII_SILICON_VERSION
Type
Boolean
Device Support
Stratix II
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY <value>
Default Value
Off
STRATIX_CONFIGURATION_DEVICE
Specifies the configuration device that you want to use as the means of configuring the target device.
Old Name
YEAGER_CONFIGURATION_DEVICE
Type
String
Device Support
- Cyclone II
- MAX II
- MAX V
- Stratix
- Stratix GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE <value>
Default Value
Auto
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE
Specifies user-defined information about the configuration device. The JTAG user code is an extension of the option register. This data can be read with the JTAG USERCODE instruction.
Type
String
Device Support
- Arria GX
- Arria II GX
- Arria II GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
Notes
None
Syntax
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
STRATIX_JTAG_USER_CODE
Specifies user-defined information about the target device. The JTAG user code is an extension of the option register. This data can be read with the JTAG USERCODE instruction.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
None
Syntax
set_global_assignment -name STRATIX_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT
Loads a checkered pattern as initial RAM content into all RAM blocks without specified RAM content that supports content initialization. Turning on this option does not affect simulation, which may cause on-chip behavior to differ from simulation results.
Type
Enumeration
Values
- 0000
- 0101
- 1010
- 1111
- OFF
- ON
- RANDOM
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone V
- Stratix
- Stratix II
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT <value>
Default Value
OFF
USE_CHECKSUM_AS_USERCODE
Sets the JTAG user code to match the checksum value of the device programming file. The programming file is a Programmer Object File (.pof) for non-volatile devices, such as MAX II devices, or an SRAM Object File (.sof) for SRAM-based devices. If you turn this option on, the JTAG user code option is not available.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- E
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name USE_CHECKSUM_AS_USERCODE <value>
Default Value
On
USE_CONFIGURATION_DEVICE
Specifies that you intend to use a configuration device(s) such as the EPC2 as the means of configuring the target device. This option directs the Compiler to create a Programmer Output File (.pof) for programming the configuration device. If multiple configuration devices are needed, one POF is created for each device, with names of the following format: name.pof, name_1.pof, name_2.pof, etc.
Type
Boolean
Device Support
- Arria GX
- Arria II GX
- Arria II GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- EPC1
- EPC2
- Enhanced Configuration Devices
- A
- B
- E
- FLEX8000
- Flash Memory
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
- MAX9000
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Virtual JTAG TAP
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name USE_CONFIGURATION_DEVICE <value>
Assignment Group Assignments
ASSIGNMENT_GROUP_EXCEPTION
Defines a node(s) to be excluded as an excpetion to a previously added member. It can be an instance name or a wildcard representing multiple instance names
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name ASSIGNMENT_GROUP_EXCEPTION -section_id <section identifier> <value>
ASSIGNMENT_GROUP_MEMBER
Defines an element of a group. It can be an instance name or a wildcard representing multiple instance names
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name ASSIGNMENT_GROUP_MEMBER -section_id <section identifier> <value>
Classic Timing Assignments
ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS
Directs the Timing Analyzer to analyze latches as synchronous elements, rather than as combinational elements. Although latches continue to be implemented as a LUT feeding back onto itself, turning on this option directs the Timing Analyzer to analyze all latches as synchronous elements. Specifically, the clock enable is analyzed as an inverted clock. The Timing Analyzer reports the results of setup and hold analysis on these latches
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS <value>
Default Value
On
CUT_OFF_IO_PIN_FEEDBACK
Cuts off feedback from I/O pins during timing analysis. Cutting off I/O pin feedback is especially useful when a bidirectional pin is connected directly or indirectly to both the input and the output of a latch. This type of feedback path is continuous because it is not interrupted by any clocked logic primitives.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK <value>
Default Value
On
CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS
Cuts the paths between registers clocked by unrelated clocks. This option makes the timing analysis reporting similar to MAX+PLUS II timing analysis reporting.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS <value>
Default Value
On
CUT_OFF_READ_DURING_WRITE_PATHS
Cuts the path from the write enable register through the ESB to a destination register.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS <value>
Default Value
On
DEFAULT_HOLD_MULTICYCLE
Determines the default hold multicycle. The 'Same as Multicycle' setting ensures that the signal is latched on the final edge only. The 'One' setting assumes that the design can latch on any edge, up to and including the final edge. The 'Same as Multicycle' setting will give fewer hold time violation warnings. The 'One' setting is more restrictive, but it is the default setting for the TimeQuest Timing Analyzer and other third-party timing analyzers. This setting can be overridden on specific nodes with the Hold Multicycle option.
Type
Enumeration
Values
- One
- Same as Multicycle
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE <value>
Default Value
Same as Multicycle
Example
set_global_assignment -name default_hold_multicycle "Same as Multicycle" set_global_assignment -name default_hold_multicycle "One"
See Also
MULTICYCLE, SRC_MULTICYCLE, HOLD_MULTICYCLE, SRC_HOLD_MULTICYCLE, SETUP_RELATIONSHIP, HOLD_RELATIONSHIP
DO_COMBINED_ANALYSIS
Analyze both the fast corner (min delays) and the slow corner (max delays) and to report the results from each analysis.
Type
Boolean
Device Support
- Arria GX
- Arria II GX
- Arria II GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
Notes
None
Syntax
set_global_assignment -name DO_COMBINED_ANALYSIS <value>
Default Value
Off
EMIF_SOC_PHYCLK_ADVANCE_MODELING
Instructs routing annotation to adjust the AV-SoC Phyclk delays.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING <value>
Default Value
Off
ENABLE_HPS_INTERNAL_TIMING
Enable HPS Internal Timing Characteristics
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING <value>
Default Value
Off
INPUT_TRANSITION_TIME
Specifies the input transition time. This assignment is used in Quartus to adjust the timing of the I/O buffers for all families that support AIOT. It is also used when generating the PrimeTime script that it is used by the HardCopy back end. This assignment gets converted as a set_input_transition SDC command. If the assignment does not exist, Quartus will generate a set_input_transition using 80% of VCCN * 1V/ns where VCCN depends on the I/O Standard used
Type
Time
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix
- Stratix II
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports wildcards.
This assignment is copied to any duplicated nodes.
Syntax
set_instance_assignment -name INPUT_TRANSITION_TIME -to <to> -entity <entity name> <value>
LVDS_FIXED_CLOCK_DATA_PHASE
Specifies exact skew compensation. When the fixed clock-to-data skew is known, clock data synchronization (CDS) can be pre-programmed into the device during configuration. If CDS is pre-programmed into the device, training patterns do not need to be transmitted to the receiver channels. The resolution of each pre-programmed setting is 25% of the data period, to compensate for skew up to 50% of the data period. This option is applied only to input pins that drive the rx_in[] port of the altlvds_rx megafunction. This option is available for APEX II devices only.
Type
Enumeration
Values
- Default
- Negative 180
- Negative 90
- Positive 180
- Positive 90
- Zero
Notes
None
Syntax
set_instance_assignment -name LVDS_FIXED_CLOCK_DATA_PHASE -to <to> -entity <entity name> <value>
MAX_CORE_JUNCTION_TEMP
This is the maximum core junction temperature that will be encountered during operation. Specified in degrees Celsius
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name MAX_CORE_JUNCTION_TEMP <value>
MIN_CORE_JUNCTION_TEMP
This is the minimum core junction temperature that will be encountered during operation. Specified in degrees Celsius
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name MIN_CORE_JUNCTION_TEMP <value>
NOMINAL_CORE_SUPPLY_VOLTAGE
Specifies the voltage for the core power supply. For Stratix III devices, the core supply voltage applies only to the VCCL power rail. Refer to the device datasheet for the current device family for more details.
Type
String
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix III
- Stratix IV
- Stratix V
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE <value>
PACKAGE_SKEW_COMPENSATION
Indicates that that the package skew for the signal has been compensated by the board trace delays.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION -to <to> -entity <entity name> <value>
PLL_EXTERNAL_FEEDBACK_BOARD_DELAY
Specifies an external board delay between a feedback output pin and a feedback input pin (fbin) for a PLL in external feedback mode. This option is ignored if it is assigned to anything other than the fbin pin of a PLL.
Type
Time
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
None
Syntax
set_instance_assignment -name PLL_EXTERNAL_FEEDBACK_BOARD_DELAY -to <to> -entity <entity name> <value> set_global_assignment -name PLL_EXTERNAL_FEEDBACK_BOARD_DELAY <value>
TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT
Instructs the Fitter to aggressively optimize for hold timing closure.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT <value>
Default Value
Off
TIMEQUEST_DO_CCPP_REMOVAL
Directs the TimeQuest Timing Analyzer to remove common clock path pessimism (CCPP) during slack computation.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- EPC1
- EPC2
- Enhanced Configuration Devices
- A
- B
- E
- FLEX8000
- Flash Memory
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
- MAX9000
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
- Virtual JTAG TAP
Notes
None
Syntax
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL <value>
TIMEQUEST_DO_REPORT_TIMING
Directs the TimeQuest Timing Analyzer to report the worst-case path per clock domain and analysis.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING <value>
Default Value
Off
TIMEQUEST_MULTICORNER_ANALYSIS
Directs the TimeQuest Timing Analyzer to perform multicorner timing analysis, which analyzes the design against best-case and worst-case operating conditions. Turning on this option does not enable multicorner analysis in the Fitter. To optimize fast-corner timing, see the Fitter Settings page of the Settings dialog box.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- EPC1
- EPC2
- Enhanced Configuration Devices
- A
- B
- E
- FLEX8000
- Flash Memory
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
- MAX9000
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
- Virtual JTAG TAP
Notes
None
Syntax
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS <value>
TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS
Specifies the maximum number of worst-case timing paths for the TimeQuest Timing Analyzer to report per clock domain and analysis.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
INTEGER_RANGE
1, 100000
Notes
None
Syntax
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS <value>
Default Value
100
TIMEQUEST_REPORT_SCRIPT
Specifies the name of the tcl script that will be used to overwrite the default TimeQuest report panels created during a normal compile.
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT <value>
TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
Directs the TimeQuest Timing Analyzer to perform default timing analysis prior to running the user-specified report script specified by TIMEQUEST_REPORT_SCRIPT.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS <value>
Default Value
On
TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS
Directs the TimeQuest Timing Analyzer to report worst-case timing paths per clock domain and analysis.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- EPC1
- EPC2
- Enhanced Configuration Devices
- A
- B
- E
- FLEX8000
- Flash Memory
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
- MAX9000
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
- Virtual JTAG TAP
Notes
None
Syntax
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS <value>
USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
Instructs STA to take DLL frequency into account while calculating phase shift of DQS delay chain
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN <value>
Default Value
Off
Compiler Assignments
ALLOW_REGISTER_DUPLICATION
Controls whether the Compiler is allowed to duplicate registers to improve design performance. When register duplication is allowed, the Compiler may perform optimizations that create a second copy of a register and move a portion of its fan-out to this new node, in order to improve routability and/or reduce the total routing wire required to route a net with many fan-outs.\r\n\r\nIf register duplication is disabled, optimizations that retime registers will also be disabled.\r\n\r\nThis setting affects Analysis & Synthesis and the Fitter.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ALLOW_REGISTER_DUPLICATION <value>
Default Value
On
Example
set_global_assignment -name allow_register_duplication on
ALLOW_REGISTER_MERGING
Controls whether the Compiler is allowed to remove registers that are identical to other registers in the design. When register merging is allowed, in cases where two registers generate the same logic, one may be deleted and the remaining one will be made to also fan-out to the deleted register's destinations. This option is useful if you wish to prevent the Compiler from removing duplicate registers that you have used deliberately.\r\n\r\nIf register merging is disabled, optimizations that retime registers will also be disabled.\r\n\r\nThis setting affects Analysis & Synthesis and the Fitter.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ALLOW_REGISTER_MERGING <value>
Default Value
On
Example
set_global_assignment -name allow_register_merging off
OPTIMIZATION_MODE
Controls the Compiler's high-level optimization strategy. By default, the Quartus Prime Compiler optimizes in a balanced mode, targeting the design's timing constraints. The alternate modes cause the Compiler to prioritize a particular optimization metric. High effort modes primarily enable additional optimizations that increase compilation time. Aggressive modes may increase compilation time and also make trade-offs that may harm the other optimization metrics (performance, area, etc.).\r\n\r\n'High Performance Effort' mode will cause the compiler to target increased positive timing margin (via Standard Fit compilation), increase the timing optimization effort applied during placement and routing, and enable timing-related Physical Synthesis optimizations (as allowed by the register optimization settings below). Each of these additional optimizations can increase compilation time. 'Aggressive Performance' mode enables the same optimizations as 'High Performance Effort' mode, and additionally enables options during Analysis & Synthesis to maximize design performance at a potential increase to logic area. If design utilization is already very high, this option may lead to difficulty in fitting which could also negatively affect overall optimization quality.\r\n\r\n'High Power Effort' mode guides the Compiler to spend additional compilation time reducing routing utilization, which saves dynamic power. In 'Aggressive Power' mode, the Compiler will further target reducing the routing usage of signals with the highest specified (via Signal Activity File) or estimated toggle rates, saving additional dynamic power but potentially affecting performance.\r\n\r\n'Aggressive Area' mode instructs the Compiler to target an area minimal solution, even if this reduces overall timing performance.\r\n\r\nThis setting affects Analysis & Synthesis and the Fitter.
Type
Enumeration
Values
- Aggressive Area
- Aggressive Performance
- Aggressive Power
- Balanced
- High Performance Effort
- High Power Effort
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name OPTIMIZATION_MODE <value>
Default Value
Balanced
TIMEQUEST_SPECTRA_Q
Controls when the Compiler will use TimeQuest Spectra-Q as its timing analysis engine. This setting is not configurable in Quartus Prime Pro Edition, where TimeQuest Spectra-Q is always used.
Old Name
TIMEQUEST2
Type
Enumeration
Values
- FITTER_ONLY
- OFF
- ON
- SIGNOFF_ONLY
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name TIMEQUEST_SPECTRA_Q <value>
Example
set_global_assignment -name TIMEQUEST_SPECTRA_Q ON
Design Assistant Assignments
ACLK_CAT
Direct Design Assistant to detect asynchronous clock domains on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name ACLK_CAT <value>
ACLK_RULE_IMSZER_ADOMAIN
Direct Design Assistant to detect improper synchronizer which moves data across asynchronous domain boundaries on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name ACLK_RULE_IMSZER_ADOMAIN <value>
ACLK_RULE_NO_SZER_ACLK_DOMAIN
Direct Design Assistant to detect synchronizer between asynchronous clock domains on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name ACLK_RULE_NO_SZER_ACLK_DOMAIN <value>
ACLK_RULE_SZER_BTW_ACLK_DOMAIN
Direct Design Assistant to detect synchronizer for every signal between asynchronous clock domains on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name ACLK_RULE_SZER_BTW_ACLK_DOMAIN <value>
CLK_CAT
Direct Design Assistant to check all clock-related violations on the design. Expand the items to turn off the rule checking if irrelevant.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name CLK_CAT <value>
CLK_RULE_CLKNET_CLKSPINES
Direct Design Assistant to check clock net not mapped to clock spines used on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES <value>
CLK_RULE_CLKNET_CLKSPINES_THRESHOLD
Specifies the threshold value for clock net not mapped to clock spines rule.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD <value>
Default Value
25
CLK_RULE_COMB_CLOCK
Direct Design Assistant to check combinatorial logic output used as on-chip clock on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name CLK_RULE_COMB_CLOCK <value>
CLK_RULE_GATED_CLK_FANOUT
Direct Design Assistant to check gated clock have feed to certain number of clock port to effectively save power.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name CLK_RULE_GATED_CLK_FANOUT <value>
CLK_RULE_INPINS_CLKNET
Direct Design Assistant to check illegal input pins connected to clock net used on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name CLK_RULE_INPINS_CLKNET <value>
CLK_RULE_INV_CLOCK
Direct Design Assistant to check inverted clock used on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name CLK_RULE_INV_CLOCK <value>
CLK_RULE_MIX_EDGES
Direct Design Assistant to check mixed-clock edges used on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name CLK_RULE_MIX_EDGES <value>
DA_CUSTOM_RULE_FILE
Used to set the path for DA custom rule file
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name DA_CUSTOM_RULE_FILE <value>
DISABLE_DA_GX_RULE
Prevents Design Assistant from running when the Fitter is running.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
Syntax
set_global_assignment -name DISABLE_DA_GX_RULE <value> set_instance_assignment -name DISABLE_DA_GX_RULE -to <to> -entity <entity name> <value>
DISABLE_DA_RULE
Suppress design assistant rule locally or turn off design assistant rule globally for general user
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
This assignment is copied to any duplicated nodes.
Syntax
set_global_assignment -name DISABLE_DA_RULE <value> set_instance_assignment -name DISABLE_DA_RULE -to <to> -entity <entity name> <value>
DRC_DEADLOCK_STATE_LIMIT
Specifies the maximum number of states that you want the Design Assistant to detect as a deadlock condition. A larger number will results in longer processing time.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT <value>
Default Value
2
DRC_DETAIL_MESSAGE_LIMIT
Specifies the maximum number of detail messages that you want the Design Assistant to report.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT <value>
Default Value
10
DRC_FANOUT_EXCEEDING
Specifies the minimum amount of fan-out that a node must have to be reported by the Design Assistant.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name DRC_FANOUT_EXCEEDING <value>
Default Value
30
DRC_GATED_CLOCK_FEED
Specifies the minimum amount of clock port a gated clock must feed so that it's an acceptable gated clock.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name DRC_GATED_CLOCK_FEED <value>
Default Value
30
DRC_REPORT_FANOUT_EXCEEDING
Directs the Design Assistant to report all nodes with more than the specified amount of fan-out.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING <value>
DRC_REPORT_TOP_FANOUT
Directs the Design Assistant to report the specified number of nodes with the highest fan-out.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name DRC_REPORT_TOP_FANOUT <value>
DRC_TOP_FANOUT
Specifies the number of nodes with the highest fan-out that you want the Design Assistant to report.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name DRC_TOP_FANOUT <value>
Default Value
50
DRC_VIOLATION_MESSAGE_LIMIT
Specifies the maximum number of violation messages that you want the Design Assistant to report.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT <value>
Default Value
30
ENABLE_DA_RULE
Desuppress design assistant rule locally or turn on design assistant rule globally for general user
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports wildcards.
This assignment is copied to any duplicated nodes.
Syntax
set_global_assignment -name ENABLE_DA_RULE <value> set_instance_assignment -name ENABLE_DA_RULE -to <to> -entity <entity name> <value>
ENABLE_DRC_SETTINGS
Directs the Design Assistant to run during a compilation based on user settings.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name ENABLE_DRC_SETTINGS <value>
Default Value
Off
FSM_CAT
Direct Design Assistant to detect finite state machine rules on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name FSM_CAT <value>
FSM_RULE_DEADLOCK_STATE
Direct Design Assistant to detect deadlock state in state machine on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name FSM_RULE_DEADLOCK_STATE <value>
FSM_RULE_NO_RESET_STATE
Direct Design Assistant to detect if reset state is specified for state machine on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name FSM_RULE_NO_RESET_STATE <value>
FSM_RULE_NO_SZER_ACLK_DOMAIN
Direct Design Assistant to detect synchronizer between asynchronous clock domains feeding to state machine on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name FSM_RULE_NO_SZER_ACLK_DOMAIN <value>
FSM_RULE_UNREACHABLE_STATE
Direct Design Assistant to detect unreachable state in state machine on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name FSM_RULE_UNREACHABLE_STATE <value>
FSM_RULE_UNUSED_TRANSITION
Direct Design Assistant to detect unused transition in state machine on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name FSM_RULE_UNUSED_TRANSITION <value>
HARDCOPY_FLOW_AUTOMATION
Specifies which HardCopy flow will be run in HardCopy timing wizard
Type
Enumeration
Values
- COMPILE_NEW_PROJECT
- FULL_COMPILATION
- MIGRATION_ONLY
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION <value>
Default Value
MIGRATION_ONLY
HARDCOPY_NEW_PROJECT_PATH
Specifies the directory path for the new/migrated HardCopy project.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name HARDCOPY_NEW_PROJECT_PATH <value>
HCPY_CAT
Direct Design Assistant to detect HardCopy rules on the design. All HardCopy rules apply to HardCopy devices only.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name HCPY_CAT <value>
HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES
Direct Design Assistant to detect PLL that feeds multiple clock network types.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES <value>
HCPY_VREF_PINS
Direct Design Assistant to detect VREF pins on the design. This rule applies to HardCopy devices only.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name HCPY_VREF_PINS <value>
NONSYNCHSTRUCT_CAT
Direct Design Assistant to check for non-synchronous design structures on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_CAT <value>
NONSYNCHSTRUCT_RULE_ASYN_RAM
Directs the Design Assistant to detect asynchronous memories targeted by the design. This rule applies to HardCopy devices only.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_ASYN_RAM <value>
NONSYNCHSTRUCT_RULE_COMBLOOP
Direct Design Assistant to check for combinatorial loop with unidentified function on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMBLOOP <value>
NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE
Direct Design Assistant to detect combinatorial logic dirving asynchronous RAM Write Enable signals on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE <value>
NONSYNCHSTRUCT_RULE_DELAY_CHAIN
Direct Design Assistant to check for delay chain with unidentified function on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_DELAY_CHAIN <value>
NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN
Direct Design Assistant to check illegal pulse generator on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN <value>
NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED
Direct Design Assistant to detect latch of unidentified type on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED <value>
NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR
Direct Design Assistant to check multi-vibrator on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR <value>
NONSYNCHSTRUCT_RULE_REG_LOOP
Direct Design Assistant to check for combinatorial loop with output of register feeding its own control signal on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_REG_LOOP <value>
NONSYNCHSTRUCT_RULE_RIPPLE_CLK
Direct Design Assistant to check ripple clock structure on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_RIPPLE_CLK <value>
NONSYNCHSTRUCT_RULE_SRLATCH
Direct Design Assistant to detect SR-latch on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name NONSYNCHSTRUCT_RULE_SRLATCH <value>
RESET_CAT
Direct Design Assistant to check reset-related violations on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name RESET_CAT <value>
RESET_RULE_COMB_ASYNCH_RESET
Direct Design Assistant to check combinatorial logic output used as on-chip asynchronous reset on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name RESET_RULE_COMB_ASYNCH_RESET <value>
RESET_RULE_IMSYNCH_ASYNCH_DOMAIN
Direct Design Assistant to check for reset which is improperly synchronized in receiving asynchronous domain on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name RESET_RULE_IMSYNCH_ASYNCH_DOMAIN <value>
RESET_RULE_IMSYNCH_EXRESET
Direct Design Assistant to check improper synchronization of external reset on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name RESET_RULE_IMSYNCH_EXRESET <value>
RESET_RULE_UNSYNCH_ASYNCH_DOMAIN
Direct Design Assistant to check for reset which is not synchronized in receiving asynchronous domain on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name RESET_RULE_UNSYNCH_ASYNCH_DOMAIN <value>
RESET_RULE_UNSYNCH_EXRESET
Suppress unsynchronized external reset rule.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name RESET_RULE_UNSYNCH_EXRESET <value>
SIGNALRACE_CAT
Direct Design Assistant to check signal race on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name SIGNALRACE_CAT <value>
SIGNALRACE_RULE_CLK_PORT_RACE
Direct Design Assistant to check race condition between clock port and any other port of the same register.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name SIGNALRACE_RULE_CLK_PORT_RACE <value>
SIGNALRACE_RULE_RESET_RACE
Direct Design Assistant to detect synchronous port and asynchronous port of same register driven by same signal source
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name SIGNALRACE_RULE_RESET_RACE <value>
SIGNALRACE_RULE_SECOND_SIGNAL_RACE
Direct Design Assistant to detect more than one secondary signal of same register driven by same signal source
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name SIGNALRACE_RULE_SECOND_SIGNAL_RACE <value>
SIGNALRACE_RULE_TRISTATE
Direct Design Assistant to detect Tri-state signal race condition
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name SIGNALRACE_RULE_TRISTATE <value>
TIMING_CAT
Direct Design Assistant to check timing closure related violations on the design.
Type
Boolean
Device Support
- Cyclone
- E
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
Notes
None
Syntax
set_global_assignment -name TIMING_CAT <value>
EDA Netlist Writer Assignments
EDA_BOARD_BOUNDARY_SCAN_OPERATION
Specify the BSDL file operation either for pre-configuration or post-configuration
Type
Enumeration
Values
- POST_CONFIG
- PRE_CONFIG
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION -section_id <section identifier> <value>
Default Value
PRE_CONFIG, requires section identifier
EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL
Specifies the boundary scan format used for board level boundary scan testing.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL <value> set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL -entity <entity name> <value>
Default Value
<None>
EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL
Specifies the EDA third-party tool used for board level signal integrity analysis.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL <value> set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL -entity <entity name> <value>
Default Value
<None>
EDA_BOARD_DESIGN_SYMBOL_TOOL
Specifies the EDA third-party tool used for board level schematic design.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL <value> set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL -entity <entity name> <value>
Default Value
<None>
EDA_BOARD_DESIGN_TIMING_TOOL
Specifies the EDA third-party tool used for board level timing analysis.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL <value> set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL -entity <entity name> <value>
Default Value
<None>
EDA_BOARD_DESIGN_TOOL
Specifies the EDA third-party tool used for board level design and analysis.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_TOOL <value> set_global_assignment -name EDA_BOARD_DESIGN_TOOL -entity <entity name> <value>
Default Value
<None>
EDA_DESIGN_EXTRA_ALTERA_SIM_LIB
Specify additional ALTERA simulation model libraries required is used by the design files
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_DESIGN_EXTRA_ALTERA_SIM_LIB -section_id <section identifier> <value>
EDA_DESIGN_INSTANCE_NAME
Specify the instance name of the design in the test bench
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME -section_id <section identifier> <value>
EDA_ENABLE_GLITCH_FILTERING
Write logic to filter glitches in the simulation netlist.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING -section_id <section identifier> <value> set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_ENABLE_IPUTF_MODE
Allows you to simulate designs containing hw.tcl based IP cores. This may require adding .sip files to your Quartus Prime project. This variable may be removed in future releases.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_ENABLE_IPUTF_MODE -section_id <section identifier> <value> set_global_assignment -name EDA_ENABLE_IPUTF_MODE -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier
EDA_EXTRA_ELAB_OPTION
Additional custom simulation elaboration options for one or more simulators.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_EXTRA_ELAB_OPTION -section_id <section identifier> <value> set_global_assignment -name EDA_EXTRA_ELAB_OPTION -entity <entity name> -section_id <section identifier> <value>
Default Value
"", requires section identifier
EDA_FLATTEN_BUSES
Flattens all buses when creating the VHDL Output File (.vho). You should turn on this option if your third-party EDA environment does not support buses.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_FLATTEN_BUSES -section_id <section identifier> <value> set_global_assignment -name EDA_FLATTEN_BUSES -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_FORMAL_VERIFICATION_ALLOW_RETIMING
Allow register retiming to be turned on for formal verification
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING -section_id <section identifier> <value> set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_FORMAL_VERIFICATION_TOOL
Specifies the EDA third-party tool used for formal verification.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL <value> set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL -entity <entity name> <value>
Default Value
<None>
EDA_FV_HIERARCHY
Determines how the hierarchy of design entities is to be processed during compilation. 'BLACKBOX' setting causes the entity to be handled as a black-box in the EDA flow. 'NONE' setting is the default and means no special handling to be done. The option applies only to the design entity to which it is assigned; lower-level entities do not inherit their parent entity's setting for this option.
Type
Enumeration
Values
- BLACKBOX
- Off
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_FV_HIERARCHY -entity <entity name> <value> set_instance_assignment -name EDA_FV_HIERARCHY -to <to> -entity <entity name> <value>
EDA_GENERATE_FUNCTIONAL_NETLIST
Generate Verilog/VHDL netlist for functional or timing simulation with EDA simulation tools. When this option is 'On', the EDA Netlist Writer does not generate a Standard Delay Format Output File (.sdo). If the device does not support timing simulation, then only the functional-simulation netlist is available.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -section_id <section identifier> <value> set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT
Directs the EDA Netlist Writer to generate a command script to run gate-level simulation with a third-party EDA tool.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
Syntax
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT -section_id <section identifier> <value> set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_GENERATE_POWER_INPUT_FILE
Generates a Power Input File (.pwf) to perform power analysis in the Quartus Prime software when using third-party simulation tools.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE -section_id <section identifier> <value> set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT
Directs the EDA Netlist Writer to generate a command script to run RTL functional simulation with a third-party EDA tool.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
Syntax
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT -section_id <section identifier> <value> set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_GENERATE_TIMING_CLOSURE_DATA
Generates back-annotation data for performing in-place optimization with the LeonardoSpectrum software.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA -section_id <section identifier> <value> set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_IBIS_EXTENDED_MODEL_SELECTOR
Enable or disable information about related IO Standards in the model selector section of IBIS files. Will turn on EDA_IBIS_MODEL_SELECTOR when set to true.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR -section_id <section identifier> <value> set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_IBIS_MODEL_SELECTOR
Enable or disable model selector feature for IBIS Writer
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR -section_id <section identifier> <value> set_global_assignment -name EDA_IBIS_MODEL_SELECTOR -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_IBIS_MUTUAL_COUPLING
Allows you to print the per pin RLC package model with mutual coupling when generating IBIS Output Files (.ibs) with the EDA Netlist Writer. The lumped RLC package model information appears in the IBIS Output File.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING -section_id <section identifier> <value> set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_IBIS_SPECIFICATION_VERSION
Specifies the IBIS Specification version.
Type
Enumeration
Values
- 4p2
- 5p0
Device Support
- Arria 10
- Arria V
- Arria V GZ
- Cyclone V
- Stratix V
Syntax
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION -section_id <section identifier> <value>
Default Value
4p2, requires section identifier
EDA_IPFS_FILE
Specifies the library to which IPFS file should be compiled
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_IPFS_FILE -section_id <section identifier> <value>
EDA_LAUNCH_CMD_LINE_TOOL
Allows you to launch third-party EDA tools in the command-line mode rather than opening the graphical user interface.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL -section_id <section identifier> <value> set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_MAINTAIN_DESIGN_HIERARCHY
Maintain the original user design hierarchy when generating Verilog or VHDL simulation netlist for the project.
Type
Enumeration
Values
- OFF
- ON
- PARTITION_ONLY
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY -section_id <section identifier> <value> set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY -entity <entity name> -section_id <section identifier> <value>
Default Value
OFF, requires section identifier
EDA_MAP_ILLEGAL_CHARACTERS
Maps the vertical bar (|), tilde (~), and colon (:) characters in Quartus Prime hierarchical node names to the legal Verilog HDL characters z, x, and underscore (_), respectively, in Verilog Output Files. Turning on this option also maps other illegal non-alphanumeric characters, including brackets [], parentheses, (), angle brackets <>, and braces {} to underscores (_).
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -section_id <section identifier> <value> set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_NATIVELINK_GENERATE_SCRIPT_ONLY
Allows you to generate the script for a third-party EDA tool without running the EDA tool.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_NATIVELINK_PORTABLE_FILE_PATHS
Specifies that the file paths in the generated third-party EDA tool command scripts should be written out using relative paths for design and testbench files, and by using a variable to refer to Quartus Prime simulation library path.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS -section_id <section identifier> <value> set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT
Specify the script for EDA Tool. After compiling models, design files and test bench files, Native Link uses this script to set up the simulation
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT -section_id <section identifier> <value>
EDA_NATIVELINK_SIMULATION_TEST_BENCH
Specify the active logical name of the test bench, that will be used to perform NativeLink Simulation
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH -section_id <section identifier> <value>
EDA_NETLIST_WRITER_OUTPUT_DIR
Specify the output directory for EDA Netlist Writer
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR -section_id <section identifier> <value>
EDA_RESYNTHESIS_TOOL
Specifies the EDA tool used for resynthesis.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_RESYNTHESIS_TOOL <value> set_global_assignment -name EDA_RESYNTHESIS_TOOL -entity <entity name> <value>
Default Value
<None>
EDA_RTL_SIMULATION_RUN_SCRIPT
Specifies the script file for performing RTL simulation using third-party simulation software.
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_RTL_SIMULATION_RUN_SCRIPT -section_id <section identifier> <value> set_global_assignment -name EDA_RTL_SIMULATION_RUN_SCRIPT -entity <entity name> -section_id <section identifier> <value>
EDA_RTL_SIM_MODE
Enables the Advanced Options - VHDL or Verilog Simulation options for Test Bench mode or Command/macro mode.
Type
Enumeration
Values
- COMMAND_MACRO_MODE
- NOT_USED
- TEST_BENCH_MODE
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_RTL_SIM_MODE -section_id <section identifier> <value> set_global_assignment -name EDA_RTL_SIM_MODE -entity <entity name> -section_id <section identifier> <value>
Default Value
NOT_USED, requires section identifier
EDA_RTL_TEST_BENCH_FILE_NAME
Specifies the RTL simulation test bench file name for Test Bench Mode. File type can be a VHDL Test Bench File (.vht), VHDL File (.vhd), Verilog HDL Test Bench File (.vt), or Verilog HDL file (.v).
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -entity <entity name> -section_id <section identifier> <value>
EDA_RTL_TEST_BENCH_NAME
Specifies the name of top-level test bench in RTL simulation test bench file.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -entity <entity name> -section_id <section identifier> <value>
EDA_RTL_TEST_BENCH_RUN_FOR
Specifies the time duration for RTL simulation using third-party simulation.
Type
Time
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_RTL_TEST_BENCH_RUN_FOR -section_id <section identifier> <value> set_global_assignment -name EDA_RTL_TEST_BENCH_RUN_FOR -entity <entity name> -section_id <section identifier> <value>
EDA_SDC_FILE_NAME
Name of Design Constraints file to be sourced in scripts generated for third party tools
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_SDC_FILE_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_SDC_FILE_NAME -entity <entity name> -section_id <section identifier> <value>
EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED
Disables setup and hold time violations detection in input registers of bi-directional pins. This setting has no effect when 'Generate functional simulation netlist' is 'On'.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_SIMULATION_RUN_SCRIPT
Specifies the script file for running a third-party simulation in Command/macro mode.
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT -section_id <section identifier> <value> set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT -entity <entity name> -section_id <section identifier> <value>
EDA_SIMULATION_TOOL
Specifies the third-party EDA tool used for simulation.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_SIMULATION_TOOL <value> set_global_assignment -name EDA_SIMULATION_TOOL -entity <entity name> <value>
Default Value
<None>
EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE
Specifies which type of output signals should be written out to the TCL file which can be used in a third-party EDA simulation tool to generate a VCD file. Writing out all output signals to the TCL file may result in a very large VCD file being generated by the third-party simulation tool.
Type
Enumeration
Values
- All
- All Except Combinational Logic Element Outputs
Device Support
- Arria GX
- Cyclone
- MAX II
- MAX V
- MAX3000A
- MAX7000AE
- MAX7000B
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
Notes
None
Syntax
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE -section_id <section identifier> <value>
Default Value
All Except Combinational Logic Element Outputs, requires section identifier
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE
Specifies whether or not a TCL file should be written out which can be used in a third-party EDA simulation tool to generate a VCD file.
Type
Boolean
Device Support
- Arria GX
- Cyclone
- MAX II
- MAX V
- MAX3000A
- MAX7000AE
- MAX7000B
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
Notes
None
Syntax
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME
Specifies the name the TCL file should be written to which can be used in a third-party EDA simulation tool to generate a VCD file.
Type
File name
Device Support
- Arria GX
- Cyclone
- MAX II
- MAX V
- MAX3000A
- MAX7000AE
- MAX7000B
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME -section_id <section identifier> <value>
EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
Specifies the instance name of the design entity in the test bench file.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME -entity <entity name> -section_id <section identifier> <value>
EDA_TEST_BENCH_ENABLE_STATUS
Enables the Advanced Options - VHDL or Verilog Simulation options for Test Bench mode or Command/macro mode.
Type
Enumeration
Values
- COMMAND_MACRO_MODE
- NOT_USED
- TEST_BENCH_MODE
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS -section_id <section identifier> <value> set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS -entity <entity name> -section_id <section identifier> <value>
Default Value
NOT_USED, requires section identifier
EDA_TEST_BENCH_ENTITY_MODULE_NAME
Specifies the top-level design entity in the test bench file.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME -entity <entity name> -section_id <section identifier> <value>
EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB
Tells NativeLink to add extra simulation libraries to the specified module. This is required by the memory controllers (both new and legacy).
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB -section_id <section identifier> <value>
EDA_TEST_BENCH_FILE
Associates a test bench file with the logical test bench name
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_FILE -section_id <section identifier> <value>
EDA_TEST_BENCH_FILE_NAME
Specifies the test bench file name for Test Bench Mode. File type can be a VHDL Test Bench File (.vht), Verilog HDL Test Bench File (.vt), or another design file type.
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_FILE_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_TEST_BENCH_FILE_NAME -entity <entity name> -section_id <section identifier> <value>
EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY
Specify the simulation library to which Gate Level Netlist will be compiled
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY -section_id <section identifier> <value>
EDA_TEST_BENCH_MODULE_NAME
Associates a test bench file with the logical test bench name
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME -section_id <section identifier> <value>
EDA_TEST_BENCH_NAME
Define a logical name for test bench. Each test bench logical name has associated section, containing test bench information, and section_id being the logical test bench name.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_NAME -section_id <section identifier> <value>
EDA_TEST_BENCH_RUN_FOR
Specifies the simulation run time for a third-party simulation in Test Bench Mode.
Type
Time
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_TEST_BENCH_RUN_FOR -section_id <section identifier> <value> set_global_assignment -name EDA_TEST_BENCH_RUN_FOR -entity <entity name> -section_id <section identifier> <value>
EDA_TEST_BENCH_RUN_SIM_FOR
Specify the time interval for running EDA Simulation
Type
Time
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR -section_id <section identifier> <value>
EDA_TIME_SCALE
Specifies the time unit used to represent timing delays in each Verilog Output File. The value for the Time Scale option may be between 0.001 ns and 10ns, and should be a multiple of 10.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_TIME_SCALE -section_id <section identifier> <value> set_global_assignment -name EDA_TIME_SCALE -entity <entity name> -section_id <section identifier> <value>
EDA_TIMING_ANALYSIS_TOOL
Specifies the EDA third-party tool used for timing analysis.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL <value> set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL -entity <entity name> <value>
Default Value
<None>
EDA_TRUNCATE_LONG_HIERARCHY_PATHS
Truncate hierarchical node names to 80 characters.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS -section_id <section identifier> <value> set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY
Specify the directory where you store the library generated with the EDA Simulation Library Compiler tool. Note: Do not use this option to specify the directory for ModelSim-Altera precompiled libraries or Active-HDL precompiled libraries.
Type
File name
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY -section_id <section identifier> <value>
Default Value
<None>, requires section identifier
EDA_VHDL_ARCH_NAME
Specify the name of Architecture in the generated VHDL simulation netlist.
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_VHDL_ARCH_NAME -section_id <section identifier> <value>
Default Value
structure, requires section identifier
EDA_WAIT_FOR_GUI_TOOL_COMPLETION
Specifies that NativeLink should wait for the EDA tool GUI launched by it to finish.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_WRITER_DONT_WRITE_TOP_ENTITY
Do not write top-level entity in VHDL Output File (.vho).
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_WRITE_DEVICE_CONTROL_PORTS
Add the devpor, devclrn, and devoe signals in the design as input ports in the top-level design hierarchy in the Verilog or VHDL simulation netlist for the project.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -section_id <section identifier> <value> set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
EDA_WRITE_NODES_FOR_POWER_ESTIMATION
Write script for Simulation tool to generate VCD file for outputs for power estimation.
Type
Enumeration
Values
- ALL_NODES
- NO_COMBINATIONAL_OUTPUT
- Off
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION -section_id <section identifier> <value> set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION -entity <entity name> -section_id <section identifier> <value>
Default Value
OFF, requires section identifier
Equivalence Checker Assignments
EQC_AUTO_BREAK_CONE
Enable EQC for auto cone break when compare is abort.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_AUTO_BREAK_CONE <value>
Default Value
On
EQC_AUTO_COMP_LOOP_CUT
Enable EQC for auto cut comp loop.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT <value>
Default Value
On
EQC_AUTO_INVERSION
Enable EQC for auto check inversion level.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_AUTO_INVERSION <value>
Default Value
On
EQC_AUTO_PORTSWAP
Enable EQC auto swap the port.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_AUTO_PORTSWAP <value>
Default Value
On
EQC_AUTO_TERMINATE
Enable auto terminates when conclusion(not equivalent or undecided) is met.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_AUTO_TERMINATE <value>
Default Value
On
EQC_BBOX_MERGE
Enable EQC automatic merge black box.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_BBOX_MERGE <value>
Default Value
On
EQC_CONSTANT_DFF_DETECTION
Enable EQC automatic constant DFF detection
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION <value>
Default Value
On
EQC_DETECT_DONT_CARES
Enable EQC detect don't cares.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_DETECT_DONT_CARES <value>
Default Value
On
EQC_DFF_SS_EMULATION
Enable EQC DFF secondary signal emulation.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_DFF_SS_EMULATION <value>
Default Value
On
EQC_DUPLICATE_DFF_DETECTION
Enable EQC automatic duplicate DFF detection
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION <value>
Default Value
On
EQC_LVDS_MERGE
Enable EQC automatic merge LVDS.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_LVDS_MERGE <value>
Default Value
On
EQC_MAC_REGISTER_UNPACK
Enable EQC for auto unpack MAC register.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_MAC_REGISTER_UNPACK <value>
Default Value
On
EQC_PARAMETER_CHECK
Enable EQC check parameter.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_PARAMETER_CHECK <value>
Default Value
On
EQC_POWER_UP_COMPARE
Enable EQC for comparing on the power-up level .
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_POWER_UP_COMPARE <value>
Default Value
Off
EQC_RAM_REGISTER_UNPACK
Enable EQC for auto unpack RAM register.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_RAM_REGISTER_UNPACK <value>
Default Value
On
EQC_RAM_UNMERGING
Enable EQC automatic unmerge RAM.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_RAM_UNMERGING <value>
Default Value
On
EQC_RENAMING_RULES
Enable EQC use renaming rules.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_RENAMING_RULES <value>
Default Value
On
EQC_RENAMING_RULES_LIST
Store eqc renaming rules
Type
String
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EQC_RENAMING_RULES_LIST <value>
EQC_SET_PARTITION_BB_TO_VCC_GND
Enable EQC for set partition Black-box unconnected input to VCC or GND.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND <value>
Default Value
On
EQC_SHOW_ALL_MAPPED_POINTS
Enable EQC show all mapped points.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS <value>
Default Value
Off
EQC_STRUCTURE_MATCHING
Enable EQC for map using structure matching.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_STRUCTURE_MATCHING <value>
Default Value
On
EQC_SUB_CONE_REPORT
Enable EQC show sub cone report.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Syntax
set_global_assignment -name EQC_SUB_CONE_REPORT <value>
Default Value
Off
Fitter Assignments
ACTIVE_SERIAL_CLOCK
Specifies the clock source for Fast Active Serial programming. In 14nm family, maximum frequency is within +/-15% range of specified if internal oscillator is used.
Type
Enumeration
Values
- AS_FREQ_100MHZ
- AS_FREQ_25MHZ
- AS_FREQ_50MHZ
- CLKUSR
- FREQ_100MHz
- FREQ_12_5MHz
- FREQ_20MHz
- FREQ_25MHz
- FREQ_40MHz
- FREQ_50MHz
Device Support
- Altera® Arria® 10
- Arria II GX
- Arria V
- Arria V GZ
- Cyclone IV GX
- Cyclone V
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ACTIVE_SERIAL_CLOCK <value>
Example
set_global_assignment -name active_serial_clock "CLKUSR"
See Also
USER_START_UP_CLOCK
ADCE_ENABLED
To disable ADCE on a PMA direct channel for RX PMA. Setting this option to Off will disable ADCE. Setting this option to Auto will leave the ADCE setting unchanged. The default value is Auto.
Type
Enumeration
Values
- Auto
- Off
Device Support
- Arria II GZ
- HardCopy IV
- Stratix IV
Notes
None
Syntax
set_global_assignment -name ADCE_ENABLED <value> set_instance_assignment -name ADCE_ENABLED -to <to> <value>
Default Value
Auto
ADVANCED_PHYSICAL_OPTIMIZATION
Enable Advanced Physical Optimization to improve the quality of results with more consistent timing closure.
Type
Boolean
Device Support
- Arria 10
- Arria V
- Arria V GZ
- Cyclone V
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION <value>
ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER
Specifies whether the Fitter allows input pins with LVTTL or LVCMOS I/O standards to be placed inside an I/O bank with a lower VCCIO voltage than the voltage specified by the pins. Overdriving the I/O bank results in higher leakage current, which can cause the design to not function as intended.
Type
Boolean
Device Support
- Arria GX
- Cyclone
- Cyclone II
- HardCopy II
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
Notes
None
Syntax
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER <value>
Default Value
Off
ALM_REGISTER_PACKING_EFFORT
This guides how aggressively the Fitter will pack ALMs when trying to place registers into desired LAB locations. Specifically, this option can be used to increase the usage of secondary register locations during placement. Increasing ALM packing density may lower the number of ALMs needed to fit the design but it may also reduce routing flexibility and timing performance. It should also be noted that this setting is used as a hint for the Fitter only. Low - The Fitter will avoid ALM packing configurations that combine LUTs and registers which have no direct connectivity. Avoiding these configurations may improve timing performance but will increase the number of ALMs used to implement the design. Medium - The Fitter allows some configurations that combine unconnected LUTs and registers to be implemented in ALM locations. The Fitter will make more usage of secondary register locations within the ALM.> High - The Fitter enables all legal and desired ALM packing configurations. In dense designs, the Fitter will automatically increase the ALM register packing effort as required to enable the design to fit.
Type
Enumeration
Values
- High
- Low
- Medium
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT <value>
Default Value
Medium
ALWAYS_ENABLE_INPUT_BUFFERS
Enables input buffers on all I/O pins including output pins. This option is required for the SAMPLE/PRELOAD JTAG instruction to function correctly on output pins. Turning on this option consumes more power.
Type
Boolean
Device Support
- Arria GX
- Cyclone II
- HardCopy II
- MAX II
- MAX V
- Stratix II
- Stratix II GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS <value>
Default Value
Off
ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK
Allows the Automatic Asynchronous Signal Pipelining algorithm to run on the specified asynchronous signal even if it feeds synchronous inputs. However, turning this option ON can change circuit functionality. This option is intended for advanced users
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
Syntax
set_global_assignment -name ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK -entity <entity name> <value> set_instance_assignment -name ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK -to <to> -entity <entity name> <value>
ASYNC_PIPELINE_REG_REACH
Specify the maximum number of LABs that the asynchronous signal sourcing at the To register can go across before a new pipeline register is inserted. This requirement might not be met for all pipeline stages, when, due to congestion or over-filled LABs, the register cannot be placed at the desired location
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
Syntax
set_global_assignment -name ASYNC_PIPELINE_REG_REACH -entity <entity name> <value> set_instance_assignment -name ASYNC_PIPELINE_REG_REACH -to <to> -entity <entity name> <value>
AUTO_C3_M9K_BIT_SKIP
Directs the fitter to skip certain bitlines in Cyclone III (including LS) M9K blocks that may be susceptible to read bit error when used in affected modes. 'Standard' setting will reserve the necessary M9K bitlines to ensure correct operation for all devices within the selected temperature range. 'Auto' setting applies the necessary bitline reservation to additional modes (x16/x18) to provide extra margin. 'Maximum' setting applies the most conservative bitline reservation required for Industrial temperature ranges regardless of the targeted device settings. Enabling any of these options can increase the number of M9K blocks required to implement the design. This global setting can be overridden for each memory instance in the Assignment Editor to customize the solution. Certain RAM modes may not be supported for Commercial temperature range devices when the 'Standard' or 'Auto' setting is applied. The fitter will issue an error for these cases. Those RAM cells can be implemented by making an instance assignment with the 'Maximum' setting, in which case additional M9K blocks may be used. Refer to the Cyclone III M9K Errata documentation for more details.
Type
Enumeration
Values
- Auto
- MAXIMUM
- Off
- Standard
Device Support
- Cyclone III
- Cyclone III LS
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP <value>
Default Value
Off
AUTO_DELAY_CHAINS
Allows the Fitter to choose the optimal delay chain to meet tsu and tco timing requirements for all I/O elements. Turning on this option may reduce the number of tsu violations while introducing a minimal number of th violations. Turning on this option does not override delay chain settings on individual nodes.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_DELAY_CHAINS <value>
AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS
Allows the Fitter to choose how to optimize the delay chains for high fanout input pins. You must enable the Auto Delay Chains option for this option to work. Enabling this option may reduce the number of tsu violation, but the compile time increases significantly, as the Fitter tries to optimize the settings for all fanouts.
Type
Enumeration
Values
- Off
- On
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS <value>
Default Value
OFF
AUTO_GLOBAL_CLOCK
Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops as a global clock signal that is made available throughout the device on the global routing paths. If you want to prevent the Compiler from automatically selecting a particular signal as global clock, set the Global Signal option to 'Off' on that signal.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- EPC1
- EPC2
- Enhanced Configuration Devices
- A
- B
- E
- FLEX8000
- Flash Memory
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX9000
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
- Virtual JTAG TAP
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_GLOBAL_CLOCK <value> set_global_assignment -name AUTO_GLOBAL_CLOCK -entity <entity name> <value> set_instance_assignment -name AUTO_GLOBAL_CLOCK -to <to> -entity <entity name> <value>
Default Value
On
AUTO_GLOBAL_MEMORY_CONTROLS
Allows the Compiler to choose the signals that feed the most write enable and read enable inputs to memories as global write enable and read enable signals that are made available throughout the device on the global routing paths. If you want to prevent the Compiler from automatically selecting a particular signal as global memory control signal, set the Global Signal option to 'Off' on that signal.
Type
Boolean
Device Support
- Arria GX
- Cyclone
- Cyclone II
- Cyclone III LS
- A
- E
- HardCopy II
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS <value> set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS -entity <entity name> <value> set_instance_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS -to <to> -entity <entity name> <value>
Default Value
Off
AUTO_GLOBAL_OE
Allows the Compiler to choose the signal that feeds the most TRI buffers as a global output enable signal that is made available throughout the device on the global routing paths. If you want to prevent the Compiler from automatically selecting a particular signal as global output enable, set the Global Signal option to 'Off' on that signal.
Type
Boolean
Device Support
- A
- E
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_GLOBAL_OE <value> set_global_assignment -name AUTO_GLOBAL_OE -entity <entity name> <value> set_instance_assignment -name AUTO_GLOBAL_OE -to <to> -entity <entity name> <value>
Default Value
On
AUTO_GLOBAL_REGISTER_CONTROLS
Allows the Compiler to choose the signals that feed the most control signal inputs to flipflops (excluding clock signals) as global signals that are made available throughout the device on the global routing paths. Depending on the target device family, these control signals can include asynchronous clear and load, synchronous clear and load, clock enable, and preset signals.If you want to prevent the Compiler from automatically selecting a particular signal as global register control signal, set the Global Signal option to 'Off' on that signal.
Type
Boolean
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- EPC1
- EPC2
- Enhanced Configuration Devices
- A
- B
- E
- FLEX8000
- Flash Memory
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- MAX9000
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
- Virtual JTAG TAP
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS <value> set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -entity <entity name> <value> set_instance_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -to <to> -entity <entity name> <value>
Default Value
On
AUTO_MERGE_PLLS
Allows the Compiler to automatically find and merge together two compatible phase-locked loops (PLL) driven by the same clock source, reducing the total number of PLLs used in a design.
Type
Boolean
Device Support
- Arria GX
- Arria II GX
- Arria II GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_MERGE_PLLS <value> set_global_assignment -name AUTO_MERGE_PLLS -entity <entity name> <value> set_instance_assignment -name AUTO_MERGE_PLLS -to <to> -entity <entity name> <value>
Default Value
On
AUTO_PACKED_REGISTERS_MAX
Allows the Compiler to automatically implement a register and a combinational function in the same logic cell. This option controls how aggressively the Fitter combines registers with other function blocks in order to reduce logic element count. If this option is set to 'Off', the Fitter does not attempt to place a pair of logic functions in a single logic cell; however, logic cells specified during synthesis to perform both a combinational and a sequential function are maintained. If this option is set to 'Normal', the Fitter places both a combinational and a sequential operation in a logic cell when it is expected that the placement does not affect design performance. When this option is set to 'Minimize Area', the Fitter aggressively combines unrelated sequential and combinational functions into a single logic cell in order to reduce the logic cell count, even at the expense of design performance. When this option is set to 'Minimize Area with Chains', the Fitter even more aggressively combines sequential and combinational functions that are part of arithmetic or register cascade chains or that can be converted to register cascade chains. When this setting is Auto, the fitter attempts to achieve the best performance while maintaining a fit for the design in the specified device. The fitter will combine all combinational and sequential functions that are deemed to benefit circuit speed. In addition, more aggressive combinations of unrelated combinational and sequential functions are performed to the extent required to reduce the area of the design in order to achieve a fit in the specified device.
Old Name
AUTO_PACKED_REGISTERS_MAXII, AUTO_PACKED_REGISTERS_TSUNAMI, Auto Packed Registers -- MAX II
Type
Enumeration
Values
- Auto
- Minimize Area
- Minimize Area with Chains
- Normal
- Off
Device Support
- MAX II
- MAX V
Notes
This assignment supports Fitter wildcards.
Syntax
set_global_assignment -name AUTO_PACKED_REGISTERS_MAX <value> set_global_assignment -name AUTO_PACKED_REGISTERS_MAX -entity <entity name> <value> set_instance_assignment -name AUTO_PACKED_REGISTERS_MAX -to <to> -entity <entity name> <value>
Default Value
Auto
AUTO_RESERVE_CLKUSR_FOR_CALIBRATION
Automatically reserve CLKUSR pin for calibration purposes
Type
Boolean
Device Support
Arria 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION <value>
Default Value
On
Example
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF
AUTO_TURBO_BIT
Controls the speed vs. power usage trade-off for a macrocell. If the Turbo Bit is on, the macrocell's speed increases; if it is off, its power consumption decreases; if you choose the 'Auto' setting, the Compiler chooses the most appropriate setting for the design.
Type
Enumeration
Values
- Auto
- Off
- On
Device Support
- MAX3000A
- MAX7000A
- MAX7000AE
- MAX7000B
- MAX7000S
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name AUTO_TURBO_BIT <value> set_global_assignment -name AUTO_TURBO_BIT -entity <entity name> <value> set_instance_assignment -name AUTO_TURBO_BIT -to <to> -entity <entity name> <value>
Default Value
ON
BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
Directs the Compiler to base the Pin-Out File (.pin) and floorplan package views on the largest selected SameFrame device.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
None
Syntax
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE <value>
Default Value
Off
BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
Controls whether RAMs implemented in MLAB cells must have equivalent pause read capabilities as RAMs implemented in block RAM. Pausing a read is the ability to keep around the last read value when reading is disabled. Allowing differences in paused read capabilities will provide the fitter more flexibility in implementing RAMs using MLAB cells. If this option is set to 'Don't Care', the Fitter may convert RAMs to MLAB cells even if they won't have equivalent paused read capabilities to a block RAM implementation. The Fitter will also output an information message notifying the user of RAMs with different paused read capabilities. If this option is set to 'Care', the Fitter will not convert RAMs to MLAB cells unless they have the equivalent paused read capabilities to a block RAM implementation. To allow the fitter the most flexibility in deciding which RAMs are implemented using MLAB cells, set this option to 'Don't Care'.
Type
Enumeration
Values
- Care
- Dont Care
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone V
- HardCopy III
- HardCopy IV
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES <value> set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES -entity <entity name> <value> set_instance_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES -to <to> -entity <entity name> <value>
Default Value
Care
BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS
Controls whether RAMs implemented in MLAB cells must have equivalent power up conditions as RAMs implemented in block RAM. Power up conditions occur when the device is powered up or globally reset. Allowing non-equivalent power up conditions will provide the fitter more flexibility in implementing RAMs using MLAB cells. If this option is set to 'Auto', the Fitter may convert RAMs to MLAB cells even if they won't have equivalent power up conditions to a block RAM implementation. The Fitter will also output a warning message notifying the user of RAMs with non-equivalent power up conditions. If this option is set to 'Don't Care', the same behavior as 'Auto' applies, but the warning message will instead be an information message. If this option is set to 'Care', the Fitter will not convert RAMs to MLAB cells unless they have equivalent power up conditions to a block RAM implementation. To allow the fitter the most flexibility in deciding which RAMs are implemented using MLAB cells, set this option to 'Auto' or 'Don't Care'.
Type
Enumeration
Values
- Auto
- Care
- Dont Care
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone V
- HardCopy III
- HardCopy IV
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS <value> set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS -entity <entity name> <value> set_instance_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS -to <to> -entity <entity name> <value>
Default Value
Auto
BLOCK_RAM_TO_MLAB_CELL_CONVERSION
Controls whether the fitter is able to convert RAMs to use LAB locations when those RAMs use 'Auto' as the selected block type. If this option is changed to 'Off' then only MLAB cells in the design or RAM cells with a block type setting of 'MLAB' will use LAB locations to implement memory.
Type
Boolean
Device Support
- Arria 10
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone V
- HardCopy III
- HardCopy IV
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION <value> set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION -entity <entity name> <value> set_instance_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION -to <to> -entity <entity name> <value>
Default Value
On
C3_M9K_BIT_SKIP
Directs the fitter to skip certain bitlines in Cyclone III M9K blocks when implementing the specificed RAM or ROM cell. The default remapping behavior is determined by the overall RAM Bit Reservation fitter setting, accessible from the More Fitter Settings page of the Settings dialog. This setting can be used to override that behavior for a specified RAM. Refer to the description of the global setting for more details of the setting values.
Type
Enumeration
Values
- Auto
- MAXIMUM
- Off
Device Support
- Cyclone III
- Cyclone III LS
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name C3_M9K_BIT_SKIP -to <to> -entity <entity name> <value>
CARRY_OUT_PINS_LCELL_INSERT
Directs the Fitter to enable or disable logic cell insertion when the I/Os are fed by carry or cascade chains. When this option is turned on, the Fitter inserts logic cells where they are needed to improve fitting. When this option is turned off, the Fitter inserts logic cells only to solve deterministic no fits.
Type
Boolean
Device Support
- A
- E
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT <value> set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT -entity <entity name> <value> set_instance_assignment -name CARRY_OUT_PINS_LCELL_INSERT -to <to> -entity <entity name> <value>
Default Value
On
CDR_BANDWIDTH_PRESET
Specifies the CDR (clock data recovery) bandwidth preset setting.
Type
Enumeration
Values
- Auto
- High
- Low
- Medium
Device Support
- Arria 10
- Arria V
- Arria V GZ
- Cyclone V
- Stratix V
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_instance_assignment -name CDR_BANDWIDTH_PRESET -to <to> -entity <entity name> <value>
CKN_CK_PAIR
Specifies the pairing of a CKn pin to a CK pin. The I/O pin of a CK CKn pair must be placed on a differential pin pair. This option is ignored if is assigned to anything other than an I/O pad, input buffer, or output buffer.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name CKN_CK_PAIR -from <from> -to <to> -entity <entity name> <value>
CLAMPING_DIODE
Turns on the Clamping Diode of a pin. The clamping diode can be turned on to limit overshoot voltage for a pin in input operation. The clamping diode is turned on by default for 3.0-V PCI/PCI-X I/O standards. The clamping diode is turned off by default for 3.3-V LVTTL/LVCMOS I/O standards. This option is ignored if it is applied to anything other than a pin or a top-level design entity.
Type
Boolean
Device Support
- Arria II GX
- Arria II GZ
- Arria V
- Cyclone V
- HardCopy III
- HardCopy IV
- Stratix III
- Stratix IV
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name CLAMPING_DIODE -entity <entity name> <value> set_instance_assignment -name CLAMPING_DIODE -to <to> -entity <entity name> <value> set_global_assignment -name CLAMPING_DIODE <value>
Default Value
Off
Example
set_instance_assignment -name CLAMPING_DIODE ON -to pin
CLOCK_ENABLE_ROUTING
Specifies whether a clock enable signal in an I/O cell should be driven by the peripheral bus or the single-pin path. The Single-Pin setting drives the clock enable signal with the local interconnect shared by the I/O cell and the adjacent LAB. The Peripheral setting drives the clock enable signal with a peripheral control bus. This option is ignored if it is assigned to anything other than a logic function assigned to an I/O cell or the signal that drives the clock enable of the I/O cell.
Type
Enumeration
Values
- Peripheral
- Single-Pin
Device Support
- A
- E
Notes
None
Syntax
set_instance_assignment -name CLOCK_ENABLE_ROUTING -to <to> -entity <entity name> <value>
CLOCK_REGION
Specifies that a signal routed using global routing paths should use the specified clock region.\n\nValid values are clock region descriptions of the form \"Regional Clock Region 1\" or \"Periphery Clock Region 1\". The clock region names should match those displayed in the Chip Planner, and can include Global, Regional, Periphery or Spine Clock regions. For Arria 10 designs, one can also specify a comma separated list of assignments (e.g., \"Periphery Clock Region 0, Periphery Clock Region 1\"). If multiple regions are specified, the logic fed by the signal will be constrained to the smallest rectangular clock region that fully contains all of the regions specified. This assignment can also be used in conjunction with the \"Global Signal\" assignment to constrain the logic fed by a clock signal to an area of the chip that is smaller than the clock region specified by the Global Signal assignment. For example, a Global Signal assignment of \"Global Clock\" and a Clock Region assignment of \"Regional Clock Region 1\" constrains the logic to the area fed by Regional Clock Region 1.
Type
String
Device Support
- Arria 10
- Arria V
- Arria V GZ
- Cyclone V
- Stratix V
Notes
This assignment supports wildcards.
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name CLOCK_REGION -to <to> -entity <entity name> <value> set_instance_assignment -name CLOCK_REGION -from <from> -to <to> -entity <entity name> <value>
CLOCK_TO_OUTPUT_DELAY
Specifies the propagation delay to the output or bidirectional pin from the output register implemented in an I/O cell. This is an advanced option that should be used only after you have compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family. This option is off by default. This option is ignored if it is applied to anything other than an output or bidirectional pin.
Type
Integer
Device Support
- Arria GX
- Arria II GX
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- HardCopy II
- MAX 10
- Stratix II
- Stratix II GX
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY -to <to> -entity <entity name> <value>
CONFIGURATION_VCCIO_LEVEL
Specifies the VCCIO voltage of the configuration pins for the current configuration scheme on the target device.
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
None
Syntax
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL <value>
Default Value
Auto
Example
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V
See Also
FORCE_CONFIGURATION_VCCIO
CONVERT_PR_WARNINGS_TO_ERRORS
Turns PR warnings into errors when enabled.
Type
Boolean
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
Syntax
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS <value>
Default Value
Off
Example
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS ON
CRC_ERROR_CHECKING
Specifies error detection CRC usage for the selected device. If error detection CRC is turned on, the device checks the validity of the programming data in the device. Any changes in the data while the device is in operation generates an error.
Old Name
STRATIX_CRC_ERROR_CHECKING, YEAGER_CRC_ERROR_CHECKING
Type
Boolean
Device Support
- Arria GX
- Arria II GX
- Arria II GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- HardCopy II
- HardCopy III
- HardCopy IV
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
Notes
None
Syntax
set_global_assignment -name CRC_ERROR_CHECKING <value>
Default Value
Off
Example
set_global_assignment -name CRC_ERROR_CHECKING ON
See Also
ERROR_CHECK_FREQUENCY_DIVISOR CRC_ERROR_OPEN_DRAIN
CRC_ERROR_OPEN_DRAIN
Specify open drain on the CRC Error pin should be enabled or not
Type
Boolean
Device Support
- Arria 10
- Arria V
- Arria V GZ
- Cyclone 10 LP
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone V
- HardCopy III
- MAX 10
- Stratix III
- Stratix V
Notes
None
Syntax
set_global_assignment -name CRC_ERROR_OPEN_DRAIN <value>
Example
set_global_assignment -name crc_error_open_drain on set_global_assignment -name crc_error_open_drain off
See Also
CRC_ERROR_CHECKING ERROR_CHECK_FREQUENCY_DIVISOR
CURRENT_STRENGTH_NEW
Sets the drive strength of a pin. Specify a number (in mA), MIN, or MAX for output or bidirectional pins that support programmable drive strength. Please refer to the family data sheet for which drive strengths are allowed for each I/O standard. This option is ignored if it is applied to anything other than an output or bidirectional pin.
Old Name
CURRENT_STRENGTH
Type
String
Device Support
- Arria 10
- Arria GX
- Arria II GX
- Arria II GZ
- Arria V
- Arria V GZ
- Cyclone
- Cyclone 10 LP
- Cyclone II
- Cyclone III
- Cyclone III LS
- Cyclone IV E
- Cyclone IV GX
- Cyclone V
- HardCopy II
- HardCopy III
- HardCopy IV
- MAX 10
- MAX II
- MAX V
- Mercury
- Stratix
- Stratix GX
- Stratix II
- Stratix II GX
- Stratix III
- Stratix IV
- Stratix V
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name CURRENT_STRENGTH_NEW -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to output_pin
See Also
IO_STANDARD OUTPUT_TERMINATION
CVP_CONFDONE_OPEN_DRAIN
Specify open drain on the CvP_CONFDONE pin should be enabled or not
Old Name
CVPCIE_CONFDONE_OPEN_DRAIN
Type
Boolean
Device Support
- Arria 10
- Arria V
- Arria V GZ
- Cyclone V
- Stratix V
Notes
None