The advantages of a differential clock over a single-ended clock scheme are:

• The differential clock is more immune to the common-mode noise, simultaneous switching noise (SSN) and ground bounce
• The differential clock is more robust for changing reference or discontinuity

For the single-ended clock input option, SSN can impact the clock input, even if the clock frequency is low frequency below 100 MHz. As shown in Figure 1, when the multi-aggressor input or output signals toggle simultaneously in one bank, large SSN is induced, that degrades power and ground integrity. When the input clock it is degraded by SSN, it can cause the PLL to lose lock, and cause the counter to malfunction. To limit SSN and crosstalk, you must restrict the number of switching outputs in a single bank. If the single-ended clock input is close to the potential crosstalk aggressor signal, it may also result in crosstalk that can cause a glitch in the victim single-ended clock signal.

Intel^® Cyclone^® 10 LP, Cyclone^® IV, and Cyclone^® III devices are designed with wire-bond packages. The inductive coupling between adjacent pins of a wire-bonded package can result in a higher noise. The package inductance of a two-layer wire-bond package is much higher compared to that of a 4-layer package, because it does not have a good reference plane.

The ground balls decrease the mutual inductance of the victim single-ended clock and block crosstalk from adjacent potential aggressor I/O signals.

Intel recommends that you do not assign any other clock signal or normal I/O signal on the original differential clock pair. This signal can cause large coupling noise on the single-ended clock input signal.

Intel recommends that you do not assign any other clock signal or normal I/O signal on the original differential clock pair, if you assign an external clock input as a single-ended clock. This signal can cause large coupling noise on the single-ended clock input signal.

The reflected waveforms in the multi-aggressor signals will transmit back-and-forth and can cause crosstalk noise on the victim clock input signal and can have an effect on power and ground. As shown in Figure 4, terminating potential aggressor signals appropriately will reduce the possibility of degrading the victim clock signal quality and power and ground noise.

In Intel^® Cyclone^® 10 LP, Cyclone^® IV, and Cyclone^® III devices, signal I/O standard can be selected in terminated or un-terminated mode.

To decrease SSN caused by crosstalk, use the slowest slew rate for potential aggressor signals, especially when multiple I/O signals are switching simultaneously.

Crosstalk or SSN on power and ground can induce a glitch or jitter on the victim clock input signal. Increasing the ramp time (V/ns) of the victim clock input signal will mitigate this affect. Fast rise and fall edges reduce the time the clock signal is above V_IH and below V_IL and can push out the glitch from V_IH or V_IL zone such that it no longer affects the clock and reset signals.

To reduce the impact of SSN due to potential aggressor signals, I/O restrictions are essential to control the number of toggling aggressor signals in the same I/O bank.

The following tests are performed to better understand crosstalk and the effect of power and/or ground noise on the victim clock inputs:

• Forward toggling pattern test—in this test each aggressor, starting from the closest to the farthest from the victim is switched on one by one, until an error occurs. The main influence of crosstalk on the victim clock input is measured, and the number of switched-on aggressors are noted.
• Reverse toggling pattern test—in this test each aggressor, starting from the farthest to the closest from the victim, is switched on one by one, until an error occurs. The primary influence of power and ground noise on the victim clock input is measured, and the number of switched-on aggressors are noted.

Reverse toggling pattern test confirms that a 2-layer substrate package is more susceptible to SSN than a 4-layer substrate package.

It is difficult to quantify the effect of SSN and crosstalk on the victim clock input separately.

You can prevent the PLL unlock issue or counter malfunction by using the potential aggressor signals with lower current strength and terminated I/O standard.

• You can put two single-ended clocks on any of the four dedicated pins.
  • Asynchronous input or output signals are not allowed on the two left most and right most pins.
• If you want to put three or four single-ended clocks on the four dedicated pins.
  • Check mutual inductance of these pins
  • Contact Intel FPGA mySupport if you cannot correlate the pad location and mutual inductance
• To avoid crosstalk, do not put the aggressor pin adjacent to the victim clock input pin.
  • Separate the aggressor pin and the victim pin by two or more pins
  • You can check the separation in Intel^® Quartus^® Prime Pad Viewer