AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
AN 702: Interfacing a USB PHY to the Hard Processor System USB 2.0 OTG Controller
The Arria® V Hard Processor System (HPS) and Cyclone® V HPS each provide two USB On-the-Go (OTG) controllers. Each USB 2.0 OTG controller supports a single USB port connected through a USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) compliant PHY.
When interfacing your design to a USB PHY, it is important to do timing analysis to ensure that the interface between the USB controller and USB PHY works reliably across a range of process, voltage and temperature (PVT) variations.
ULPI Signals
Signal |
Description |
---|---|
CLK |
Interface clock—All signals are synchronous to the clock. |
DATA[7:0] |
Data bus—Driven low by the controller during idle. The controller starts a transfer by sending a non-zero pattern. The PHY must assert DIR before using the data bus. Every time DIR toggles, DATA must be ignored for one clock cycle (the turnaround cycle). |
DIR |
Direction of the data bus—By default, DIR is low and the PHY listens for non-zero data from the controller. The PHY asserts DIR to get control of the data bus. |
NXT |
Next data—The PHY drives NXT high to throttle the data bus. |
STP |
Stop data—The controller drives STP high to signal the end of the data stream. The controller can also drive STP high to request data bus access from the PHY. |
HPS USB Controller Timing Characteristics
The Arria® V and Cyclone® V Hard Processor System USB controllers have been characterized across a range of PVT variations. Detailed USB timing information appears in the Arria® V and Cyclone® V datasheets.
USB Controller Timing Requirements
Symbol |
Description |
Min |
Typ |
Max |
Units |
---|---|---|---|---|---|
Tclk |
USB CLK clock period |
- |
16.67 |
- |
ns |
MAC Td |
CLK to USB_STP/USB_DATA[7:0] output delay |
4.4 | - |
11.0 |
ns |
MAC Tsu |
Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] |
2.0 |
- | - |
ns |
MAC Th |
Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] |
1.0 |
- | - |
ns |
USB Controller Setup and Hold Relationships
PHY Selection
The timing characteristic of ULPI PHYs vary across the spectrum of available devices.
Arria® V and Cyclone® V USB 2.0 OTG controllers support the following clock modes:
- Output clock mode—the PHY drives the clock to the controller
- Input clock mode—an external clock source on the board or a clock input sourced from the FPGA fabric drives the PHY.
All ULPI PHYs support output clock mode.
Newer ULPI PHYs support input clock mode. This mode compensates for timing mismatches between the PHY and the controller.
USB PHY Timing Characteristics
Before selecting a USB PHY and clock mode of operation, you should perform a timing analysis of the USB controller and PHY.
If the USB PHY supports input and output clock modes with different timing characteristics, perform a timing analysis of both modes before making a selection. This document includes a detailed timing analysis example of a MicroChip USB3300 PHY in output clock mode.
Symbol |
Description |
Min |
Typ |
Max |
Units |
---|---|---|---|---|---|
PHY Tsu | PHY setup time for USB_STP/USB_DATA[7:0] |
5.0 |
- | - |
ns |
PHY Th | PHY hold time for USB_STP/USB_DATA[7:0] | 0 | - | - |
ns |
PHY Td | Output delay for USB_DIR/USB_NXT/USB_DATA[7:0] |
2.0 |
- | 5.0 |
ns |
ClkTrace Td | Clock Trace delay |
0.05 |
- | 0.1 |
ns |
DTrace Td |
Data Trace delay |
0.05 |
- | 0.1 |
ns |
Clock Tu |
Clock Source Uncertainty |
- | 0.3 | - |
ns |
- For setup analysis, use Clock Tu to model period uncertainty in the launch-to-latch edge setup relationship.
- Do not use Clock Tu for hold analysis because the launch and latch edges are the same physical clock edge in time.
For this timing analysis example, assume the trace lengths of the DATA[7:0], STP and NXT signals are matched when verifying if the USB timing is met off-chip.
USB Setup and Hold Relationships
The diagram below shows the setup and hold relationships between the USB controller and PHY. The blue arrow represents the setup relationship. Data that launches from the rising edge of the PHY clock is latched on the rising edge of the next clock cycle.
The red arrow represents the hold relationship. Data must be held at least until the rising clock edge of where the data is latched.
USB Controller to PHY Setup and Hold Timing Arcs
USB Controller to PHY Setup Timing Analysis
Data Arrival ≤ Data Required Launch_Edge + ClkTrace Td_max + MAC Td_max + DTrace Td_max ≤ (Latch_Edge - Clock Tu)- PHY Tsu
If you assume that Launch_Edge= 0 ns and Latch_Edge= Tclk, then the equation can be simplified:
ClkTrace Td_max + MAC Td_max + DTrace Td_max ≤ (Tclk - Clock Tu)- PHY Tsu
Isolate PHY Tsu by moving parameter terms to one side of the inequality. Replace the parameters with specific timing characteristic values to determine if the worst case setup time for your configuration is greater than or equal to the minimum required setup time:
(Tclk - Clock Tu) - ClkTrace Td_max - MAC Td_max - DTrace Td_max ≥ PHY Tsu (16.67 - 0.3) - 0.1 - 11.0 - 0.1 ≥ 5.0 5.17 ns ≥ 5.0 ns
USB Controller to PHY Hold Timing Analysis
Data Arrival ≥ Data Required Launch_Edge + ClkTrace Td_min + MAC Td_min + DTrace Td_min ≥ Latch_Edge + PHY Th
If you assume that Launch_Edge= 0 ns and Latch_Edge= 0 ns, then the equation can be simplified and you can verify that the hold time is within limits:
ClkTrace Td_min + MAC Td_min + DTrace Td_min ≥ PHY Th 0.05 + 4.4 + 0.05 ≥ 0 4.5 ns ≥ 0 ns
USB PHY to Controller Setup and Hold Timing Arcs
USB PHY to Controller Setup Timing Analysis
Data Arrival ≤ Data Required Launch_Edge + PHY Td_max + DTrace Td_max ≤ (Latch_Edge – Clock Tu) + ClkTrace Td_min - MAC Tsu
If you assume that the Launch_Edge = 0 ns and the Latch_Edge = Tclk, then the equation can be simplified:
PHY Td_max + DTrace Td_max ≤ (Tclk – Clock Tu) + ClkTrace Td_min - MAC Tsu
By moving terms to one side, you can determine if the worst case setup time for your configuration is greater than or equal to the minimum required setup time:
(Tclk – Clock Tu) + ClkTrace Td_min - PHY Td_max - DTrace Td_max ≥ Mac Tsu (16.67 - 0.3) + 0.05 - 5.0 - 0.1 ≥ 5.0 11.32 ns ≥ 5.0 ns
USB PHY to Controller Hold Timing Analysis
Data Arrival ≥ Data Required LaunchEdge + PHY Td_min + DTrace Td_min ≥ LatchEdge + ClkTrace Td_max + MAC Th
If you assume that the LaunchEdge = 0 ns and the LatchEdge = 0 ns, then the equation can be simplified and you can verify that the hold time is within limits:
PHY Td_min + DTrace Td_min - ClkTrace Td_max ≥ MAC Th 2.0 + 0.05 - 0.1 ≥ 1.0 1.95 ns ≥ 1.0 ns
Output Clock Mode
In output clock mode, the clock is generated by the USB PHY. All signals are synchronized to this clock. To use this mode of operation, you must configure the USB Controller PHY interface mode for "SDR with PHY clock output mode" in the Peripheral Pins tab of HPS Parameters window in Platform Designer (Standard). This mode of operation configures the USB Controller clock pin to operate in an input mode.
Input Clock Mode
External Clock Source
Although the USB PHY is configured in input clock mode, the clock source is still driven into the USB controller as an input to the SoC device. As a result, you must configure the USB controller for "SDR with PHY clock output mode" in the Peripheral Pins tab of the HPS Parameters window of Platform Designer (Standard). This mode of operation configures the USB Controller clock pin to operate as an input.
FPGA Clock Source
When the FPGA fabric drives the USB Controller clock output the USB interface requires the use of a loan I/O pin instead of the typical USB clock input pin.
User logic in the FPGA drives a clock signal, typically derived from a PLL, into the loan I/O assigned to the USB controller. This clock signal routes into the USB controller and externally to the USB PHY. This configuration provides a common clock source for both the USB controller and PHY much like when the PHY is configured for input clock mode with an external clock source. Because this mode of operation differs from the previous examples, you must configure the USB controller for SDR with PHY clock input mode in the Peripheral Pins tab of the HPS Parameters window of Platform Designer (Standard).
Implementing Input Clock Mode with FPGA Clock Source
The following example details how to interface the FPGA to the HPS USB Controller and the external USB PHY by using a Loan I/O in the HPS.
Configuring the HPS USB 2.0 OTG Controller
- In the Peripheral Pins tab of the Hard Processor System parameter editor, select a USB controller by setting either USB0 pin or USB1 pin to one of the available HPS I/O pin sets.
-
Select the PHY
interface mode in the corresponding list,
USB0 PHY interface mode or
USB1 PHY interface mode. Set the mode to
SDR with PHY clock input mode.
Select the Controller Clock as Loan I/O
On the Peripheral Pins tab, scroll down to the Peripherals Mux Table to select the USB clock pin as loan I/O. This setting allows a clock from a PLL in the FPGA to connect to the USB controller.

Refer to the following table for the appropriate loan I/O for each USB option.
USB I/O Pin Set |
Loan I/O |
---|---|
USB0 I/O Set 0 | LOANIO44 |
USB1 I/O Set 0 | LOANIO10 |
USB1 I/O Set 1 | LOANIO29 |
Connecting the Clock in the Top Level Design
The following example shows how to connect the FPGA clock to a Loan I/O when the USB PHY operates in input clock mode using an FPGA clock source from the SoC.
Add the following code snippets to your top-level design file, to connect the clock outputs to the loan I/O:
// top level module pin defines // LOANIO10 = mac clock inout wire LOANIO10, // wire instances of the 3 loan IO buses from Platform Designer instance wire [66:0] loan_out; wire [66:0] loan_oe; // this synthesis keep directive is required in // order to connect PLL clock outputs to the Loan IO wire usb_mac_clk_from_pll /* synthesis keep */; // make assignment of the clocks to the appropriate loan IO assign loan_out[10] = usb_mac_clk_from_pll; assign loan_oe[10] = 1'b1; // snippet of Qsys instantiation signal assignments .hps_0_h2f_loan_io_in (), // hps_0_h2f_loan_io.in .hps_0_h2f_loan_io_out (loan_out), // .out .hps_0_h2f_loan_io_oe (loan_oe), // .oe .hps_io_0_hps_io_gpio_inst_LOANIO10 (LOANIO10), // hps_io_gpio_inst_LOANIO10
Revision History
Date | Version | Changes |
---|---|---|
September 2017 | 2017.09.22 |
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July 2014 | 2014.07.21 |
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July 2014 | 2014.07.16 |
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July 2014 | 2014.07.03 |
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