Introduction to Intel FPGA IP Cores
Version Information
Updated for: |
---|
Intel® Quartus® Prime Design Suite 20.3 |
1. Introduction to Intel FPGA IP Cores
The Intel® Quartus® Prime software installation includes the Intel® FPGA IP library. Integrate optimized and verified Intel® FPGA IP cores into your design to shorten design cycles and maximize performance. The Intel® Quartus® Prime software also supports integration of IP cores from other sources. Use the IP Catalog (Tools > IP Catalog) to efficiently parameterize and generate synthesis and simulation files for your custom IP variation. The Intel® FPGA IP library includes the following types of IP cores:
Basic functions | Interface protocols |
Bridges and adapters | Low power functions |
DSP functions | Memory interfaces and controllers |
Intel FPGA interconnect | Processors and peripherals |
This document provides basic information about parameterizing, generating, upgrading, and simulating stand-alone IP cores in the Intel® Quartus® Prime software.
1.1. IP Catalog and Parameter Editor
- Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.
- Type in the Search field to locate any full or partial IP core name in IP Catalog.
- Right-click an IP core name in IP Catalog to display details about supported devices, to open the IP core's installation folder, and for links to IP documentation.
- Click Search for Partner IP to access partner IP information on the web.
The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Intel® Quartus® Prime IP file (.ip) for an IP variation in Intel® Quartus® Prime Pro Edition projects. This file represents the IP variation in the project, and stores parameterization information.1
1.1.1. The Parameter Editor
- Use the Presets window to apply preset parameter values for specific applications (for select cores).
- Use the Details window to view port and parameter descriptions, and click links to documentation.
- Click Generate > Generate Testbench System to generate a testbench system (for select cores).
- Click Generate > Generate Example Design to generate an example design (for select cores).
- Click Validate System Integrity to validate a system's generic components against companion files. (Platform Designer systems only)
- Click Sync All System Info to validate a system's generic components against companion files. (Platform Designer systems only)
The IP Catalog is also available in Platform Designer (View > IP Catalog). The Platform Designer IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Intel® Quartus® Prime IP Catalog. Refer to Creating a System with Platform Designer or Creating a System with Platform Designer (Standard) for information on use of IP in Platform Designer (Standard) and Platform Designer, respectively.
1.2. Installing and Licensing Intel FPGA IP Cores
The Intel® Quartus® Prime software installs IP cores in the following locations by default:
Location | Software | Platform |
---|---|---|
<drive>:\intelFPGA_pro\quartus\ip\altera | Intel® Quartus® Prime Pro Edition | Windows* |
<drive>:\intelFPGA\quartus\ip\altera | Intel® Quartus® Prime Standard Edition | Windows |
<home directory>:/intelFPGA_pro/quartus/ip/altera | Intel® Quartus® Prime Pro Edition | Linux* |
<home directory>:/intelFPGA/quartus/ip/altera | Intel® Quartus® Prime Standard Edition | Linux |
1.2.1. Intel FPGA IP Evaluation Mode
- Simulate the behavior of a licensed Intel® FPGA IP core in your system.
- Verify the functionality, size, and speed of the IP core quickly and easily.
- Generate time-limited device programming files for designs that include IP cores.
- Program a device with your IP core and verify your design in hardware.
Intel® FPGA IP Evaluation Mode supports the following operation modes:
- Tethered—Allows running the design containing the licensed Intel® FPGA IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial joint test action group (JTAG) cable connected between the JTAG port on your board and the host computer, which is running the Intel® Quartus® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Intel® Quartus® Prime software, and requires no Intel® Quartus® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IP cores in the design support tethered mode, the evaluation time runs until any IP core evaluation expires. If all of the IP cores support unlimited evaluation time, the device does not time-out.
- Untethered—Allows running the design containing the licensed IP for a limited time. The IP core reverts to untethered mode if the device disconnects from the host computer running the Intel® Quartus® Prime software. The IP core also reverts to untethered mode if any other licensed IP core in the design does not support tethered mode.
When the evaluation time expires for any licensed Intel® FPGA IP in the design, the design stops functioning. All IP cores that use the Intel® FPGA IP Evaluation Mode time out simultaneously when any IP core in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP core for production, purchase a full production license for the IP core.
You must purchase the license and generate a full production license key before you can generate an unrestricted device programming file. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit.
Intel® licenses IP cores on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receive updates, bug fixes, and technical support beyond the first year. You must purchase a full production license for Intel® FPGA IP cores that require a production license, before generating programming files that you may use for an unlimited time. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit. To obtain your production license keys, visit the Self-Service Licensing Center.
The Intel® FPGA Software License Agreements govern the installation and use of licensed IP cores, the Intel® Quartus® Prime design software, and all unlicensed IP cores.
1.2.2. Checking the IP License Status
To generate and view the Assembler report in the GUI:
- Click Assembler on the Compilation Dashboard.
- When the Assembler (and any prerequisite stages of compilation) complete,
click the Report icon for the Assembler in
the Compilation Dashboard.Assembler Report Icon in Compilation Dashboard
- Click the Encrypted IP Cores
Summary report.Encrypted IP Cores Summary Report
To generate and view the Assembler report at the command line:
- Type the following
command:
quartus_asm <project name> -c <project revision>
- View the output report in
/output_files/<project_name>.asm.rpt.
+----------------------------------------------------------------------+ ; Assembler Encrypted IP Cores Summary ; +--------+----------------------------------------------+--------------+ ; Vendor ; IP Core Name ; License Type ; +--------+----------------------------------------------+--------------+ ; Intel ; PCIe SRIOV with 4-PFs and 2K-VFs (6AF7 00FB) ; Unlicensed ; ; Intel ; Signal Tap (6AF7 BCE1) ; Licensed ; ; Intel ; Signal Tap (6AF7 BCEC) ; Licensed ; +--------+----------------------------------------------+--------------+
1.2.3. Intel FPGA IP Versioning
Intel® FPGA IP versions match the Intel® Quartus® Prime Design Suite software versions until v19.1. Starting in Intel® Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Intel® Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Intel® Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
1.2.4. Adding IP to IP Catalog
Follow these steps to add custom or third-party IP to the IP Catalog:
- In the Intel® Quartus® Prime software, click Tools > Options > IP Search Path) to open the IP Search Path Options dialog box.
- Click Add or Remove to add/remove a location that contains IP.
-
To refresh the IP Catalog, click Refresh IP Catalog in the
Intel®
Quartus® Prime
Platform Designer (Standard), or click File > Refresh System in Platform Designer (Standard).
Figure 6. Refreshing IP Catalog
1.3. Best Practices for Intel FPGA IP
- Do not manually edit or write your own .qsys, .ip, or .qip file. Use the
Intel®
Quartus® Prime software tools to create and
edit these files.Note: When generating IP cores, do not generate files into a directory that has a space in the directory name or path. Spaces are not legal characters for IP core paths or names.
- When you generate an IP core using the IP Catalog, the Intel® Quartus® Prime software generates a .qsys (for Platform Designer (Standard)-generated IP cores) or a .ip file (for Intel® Quartus® Prime Pro Edition) or a .qip file. The Intel® Quartus® Prime Pro Edition software automatically adds the generated .ip to your project. In the Intel® Quartus® Prime Standard Edition software, add the .qip to your project. Do not add the parameter editor generated file (.v or .vhd) to your design without the .qsys or .qip file. Otherwise, you cannot use the IP upgrade or IP parameter editor feature.
- Plan your directory structure ahead of time. Do not change the relative path between a .qsys file and it's generation output directory. If you must move the .qsys file, ensure that the generation output directory remains with the .qsys file.
- Do not add IP core files directly from the /quartus/libraries/megafunctions directory in your project. Otherwise, you must update the files for each subsequent software release. Instead, use the IP Catalog and then add the .qip to your project.
- Do not use IP files that the Intel® Quartus® Prime software generates for RAM or FIFO blocks targeting older device families (even though the Intel® Quartus® Prime software does not issue an error). The RAM blocks that Intel® Quartus® Prime generates for older device families are not optimized for the latest device families.
- When generating a ROM function, save the resulting .mif or .hex file in the same folder as the corresponding IP core's .qsys or .qip file. For example, moving all of your project's .mif or .hex files to the same directory causes relative path problems after archiving the design.
- Always use the Intel® Quartus® Prime ip-setup-simulation and ip-make-simscript utilities to generate simulation scripts for each IP core or Platform Designer (Standard) system in your design. These utilities produce a single simulation script that does not require manual update for upgrades to Intel® Quartus® Prime software or IP versions, as Simulating Intel FPGA IP Cores describes.
1.4. IP General Settings
The following settings control how the Intel® Quartus® Prime software manages IP cores in a project:
Setting | Description | Location |
---|---|---|
Maximum Platform Designer memory usage size | Increase if you experience slow processing for large systems, or for out of memory errors. |
Tools > Options > IP Settings
Or Tasks pane > Settings > IP Settings |
IP generation HDL preference | The parameter editor generates the HDL you specify for IP variations. | |
IP Regeneration Policy | Controls when synthesis files regenerate for each IP variation. Typically, you Always regenerate synthesis files for IP cores after making changes to an IP variation. | |
Generate IP simulation model when generating IP | Enables automatic generation of simulation models every time you generate the IP. | |
Use available processors for parallel generation of Quartus project IPs | Directs Platform Designer to generate IPs in parallel, using the number of processors that you specify in the Compilation Process Settings pane of the Intel® Quartus® Prime project settings. | |
Additional project and global IP search locations. | The Intel® Quartus® Prime software searches for IP cores in the project directory, in the Intel® Quartus® Prime installation directory, and in the IP search path. |
Tools > Options > IP Catalog Search
Locations
Or Tasks pane > Settings > IP Catalog Search Locations |
1.5. Generating IP Cores ( Intel Quartus Prime Pro Edition)
Follow these steps to locate, instantiate, and customize an IP core in the parameter editor:
- Create or open an Intel® Quartus® Prime project (.qpf) to contain the instantiated IP variation.
- In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. To locate a specific component, type some or all of the component’s name in the IP Catalog search box. The New IP Variation window appears.
-
Specify a top-level name for your custom IP variation. Do not
include spaces in IP variation names or paths. The parameter editor saves the IP
variation settings in a file named
<your_ip>
.ip. Click OK. The parameter editor appears.
Figure 7. IP Parameter Editor ( Intel® Quartus® Prime Pro Edition)
-
Set the parameter values in the parameter editor and view the
block diagram for the component. The Parameterization Messages tab at the bottom displays any errors
in IP parameters:
- Optionally, select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications.
- Specify parameters defining the IP core functionality, port configurations, and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
Note: Refer to your IP core user guide for information about specific IP core parameters. - Click Generate HDL. The Generation dialog box appears.
- Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
- To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
- To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
- Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
-
After generating
and instantiating your IP variation, make appropriate pin assignments to
connect ports.
Note: Some IP cores generate different HDL implementations according to the IP core parameters. The underlying RTL of these IP cores contains a unique hash code that prevents module name collisions between different variations of the IP core. This unique code remains consistent, given the same IP settings and software version during IP generation. This unique code can change if you edit the IP core's parameters or upgrade the IP core version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script.
1.5.1. IP Core Generation Output ( Intel Quartus Prime Pro Edition)
File Name | Description |
---|---|
<your_ip>.ip | Top-level IP variation file that contains the parameterization of an IP core in your project. If the IP variation is part of a Platform Designer system, the parameter editor also generates a .qsys file. |
<your_ip>.cmp | The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you use in VHDL design files. |
<your_ip>_generation.rpt | IP or Platform Designer generation log file. Displays a summary of the messages during IP generation. |
<your_ip>.qgsimc (Platform Designer systems only) | Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. |
<your_ip>.qgsynth (Platform Designer systems only) | Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. |
<your_ip>.qip | Contains all information to integrate and compile the IP component. |
<your_ip>.csv | Contains information about the upgrade status of the IP component. |
<your_ip>.bsf | A symbol representation of the IP variation for use in Block Diagram Files (.bdf). |
<your_ip>.spd | Input file that ip-make-simscript requires to generate simulation scripts. The .spd file contains a list of files you generate for simulation, along with information about memories that you initialize. |
<your_ip>.ppf | The Pin Planner File (.ppf) stores the port and node assignments for IP components you create for use with the Pin Planner. |
<your_ip>_bb.v | Use the Verilog blackbox (_bb.v) file as an empty module declaration for use as a blackbox. |
<your_ip>_inst.v or _inst.vhd | HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation. |
<your_ip>.regmap | If the IP contains register information, the Intel® Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console. |
<your_ip>.svd |
Allows HPS System Debug tools to view the register maps of peripherals that connect to HPS within a Platform Designer system. During synthesis, the Intel® Quartus® Prime software stores the .svd files for slave interface visible to the System Console masters in the .sof file in the debug session. System Console reads this section, which Platform Designer queries for register map information. For system slaves, Platform Designer accesses the registers by name. |
<your_ip>.v <your_ip>.vhd |
HDL files that instantiate each submodule or child IP core for synthesis or simulation. |
mentor/ | Contains a msim_setup.tcl script to set up and run a simulation. |
aldec/ | Contains a script rivierapro_setup.tcl to setup and run a simulation. |
/synopsys/vcs /synopsys/vcsmx |
Contains a shell script vcs_setup.sh to set up and run a simulation. Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a simulation. |
/cadence | Contains a shell script ncsim_setup.sh and other setup files to set up and run an simulation. |
/xcelium | Contains an Parallel simulator shell script xcelium_setup.sh and other setup files to set up and run a simulation. |
/submodules | Contains HDL files for the IP core submodule. |
<IP submodule>/ | Platform Designer generates /synth and /sim sub-directories for each IP submodule directory that Platform Designer generates. |
1.5.2. Scripting IP Core Generation
-
Run qsys-script to start a Tcl script that instantiates the IP and sets parameters:
qsys-script --script=<script_file>.tcl
-
Run qsys-generate to generate the IP core variation:
qsys-generate <IP variation file>.qsys
1.6. Generating IP Cores ( Intel Quartus Prime Standard Edition)
- In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.
- Specify a top-level name and output HDL file type for your IP variation. This name identifies the IP core variation files in your project. Click OK. Do not include spaces in IP variation names or paths.
- Specify the parameters and options for your IP variation in the parameter editor. Refer to your IP core user guide for information about specific IP core parameters.
- Click Finish or Generate (depending on the parameter editor version). The parameter editor generates the files for your IP variation according to your specifications. Click Exit if prompted when generation is complete. The parameter editor adds the top-level .qip file to the current project automatically.
1.6.1. IP Core Generation Output ( Intel Quartus Prime Standard Edition)
1.7. Modifying an IP Variation
Menu Command | Action |
---|---|
File > Open | Select the top-level HDL (.v, or .vhd) IP variation file to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes. |
View > Utility Windows > Project Navigator > IP Components | Double-click the IP variation to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes. |
Project > Upgrade IP Components | Select the IP variation and click Upgrade in Editor to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes. |
1.8. Upgrading IP Cores
Icons in the Upgrade IP Components dialog box indicate when IP upgrade is required, optional, or unsupported for an IP variation in the project. Upgrade IP variations that require upgrade before compilation in the current version of the Intel® Quartus® Prime software.
IP Core Status | Description |
---|---|
IP Upgraded ![]() |
Indicates that your IP variation uses the latest version of the Intel® FPGA IP core. |
IP Component Outdated ![]() |
Indicates that your IP variation uses an outdated version of the IP core. |
IP Upgrade Optional ![]() |
Indicates that upgrade is optional for this IP variation in the current version of the Intel® Quartus® Prime software. You can upgrade this IP variation to take advantage of the latest development of this IP core. Alternatively, you can retain previous IP core characteristics by declining to upgrade. Refer to the Description for details about IP core version differences. If you do not upgrade the IP, the IP variation synthesis and simulation files are unchanged and you cannot modify parameters until upgrading. |
IP Upgrade Required ![]() |
Indicates that you must upgrade the IP variation before compiling in the current version of the Intel® Quartus® Prime software. Refer to the Description for details about IP core version differences. |
IP Upgrade Unsupported ![]() |
Indicates that upgrade of the IP variation is not supported in the current version of the Intel® Quartus® Prime software due to incompatibility with the current version of the Intel® Quartus® Prime software. The Intel® Quartus® Prime software prompts you to replace the unsupported IP core with a supported equivalent IP core from the IP Catalog. Refer to the Description for details about IP core version differences and links to Release Notes. |
IP End of Life ![]() |
Indicates that Intel designates the IP core as end-of-life status. You may or may not be able to edit the IP core in the parameter editor. Support for this IP core discontinues in future releases of the Intel® Quartus® Prime software. |
IP Upgrade Mismatch Warning ![]() |
Provides warning of non-critical IP core differences in migrating IP to another device family. |
IP has incompatible subcores![]() |
Indicates that the current version of the Intel® Quartus® Prime software does not support compilation of your IP variation, because the IP has incompatible subcores |
Compilation of IP Not Supported ![]() |
Indicates that the current version of the Intel® Quartus® Prime software does not support compilation of your IP variation. This can occur if another edition of the Intel® Quartus® Prime software, such as the Intel® Quartus® Prime Standard Edition, generated this IP. Replace this IP component with a compatible component in the current edition. |
Follow these steps to upgrade IP cores:
-
In the latest version of the
Intel®
Quartus® Prime software, open the
Intel®
Quartus® Prime project containing an outdated IP core variation. The
Upgrade IP Components dialog box
automatically displays the status of IP cores in your project, along with
instructions for upgrading each core. To access this dialog box manually, click
Project > Upgrade IP Components.
- To upgrade one or more IP cores that support automatic upgrade, ensure that you turn on the Auto Upgrade option for the IP cores, and click Auto Upgrade. The Status and Version columns update when upgrade is complete. Example designs that any Intel® FPGA IP core provides regenerate automatically whenever you upgrade an IP core.
-
To manually upgrade an individual IP core, select the IP core
and click Upgrade in Editor (or simply
double-click the IP core name). The parameter editor opens, allowing you to
adjust parameters and regenerate the latest version of the IP core.
Figure 13. Upgrading IP Cores ( Intel® Quartus® Prime Pro Edition Example)
Note: Intel® FPGA IP cores older than Intel® Quartus® Prime software version 12.0 do not support upgrade. Intel verifies that the current version of the Intel® Quartus® Prime software compiles the previous two versions of each IP core. The Intel® FPGA IP Core Release Notes reports any verification exceptions for Intel® FPGA IP cores. Intel does not verify compilation for IP cores older than the previous two releases.
1.8.1. Upgrading IP Cores at Command-Line
- To upgrade a single IP core at the command-line, type the following command:
quartus_sh –ip_upgrade –variation_files <my_ip>.<qsys,.v, .vhd> \ <quartus_project> Example: quartus_sh -ip_upgrade -variation_files mega/pll25.qsys hps_testx
- To simultaneously upgrade multiple IP cores at the command-line, type the
following command:
quartus_sh –ip_upgrade –variation_files “<my_ip1>.<qsys,.v, .vhd>> \ ; <my_ip_filepath/my_ip2>.<hdl>” <quartus_project> Example: quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.qsys;mega/pll3.qsys" hps_testx
1.8.2. Migrating IP Cores to a Different Device
- To display the IP cores that require migration, click Project > Upgrade IP Components. The Description field provides migration instructions and version differences.
- To migrate one or more IP cores that support automatic upgrade, ensure that the Auto Upgrade option is turned on for the IP cores, and click Perform Automatic Upgrade. The Status and Version columns update when upgrade is complete.
- To migrate an IP core that does not support automatic upgrade, double-click the IP core name, and click OK. The parameter editor appears. If the parameter editor specifies a Currently selected device family, turn off Match project/default, and then select the new target device family.
- Click Generate HDL, and confirm the Synthesis and Simulation file options. Verilog HDL is the default output file format. If you specify VHDL as the output format, select VHDL to retain the original output format.
- Click Finish to complete migration of the IP core. Click OK if the software prompts you to overwrite IP core files. The Device Family column displays the new target device name when migration is complete.
-
To ensure correctness, review the latest parameters in the
parameter editor or generated HDL.
Note: IP migration may change ports, parameters, or functionality of the IP variation. These changes may require you to modify your design or to re-parameterize your IP variant. During migration, the IP variation's HDL generates into a library that is different from the original output location of the IP core. Update any assignments that reference outdated locations. If a symbol in a supporting Block Design File schematic represents your upgraded IP core, replace the symbol with the newly generated <my_ip> .bsf. Migration of some IP cores requires installed support for the original and migration device families.
1.8.3. Troubleshooting IP or Platform Designer System Upgrade
Upgrade IP Components Field | Description |
---|---|
Status | Displays the "Success" or "Failed" status of each upgrade or migration. Click the status of any upgrade that fails to open the IP Upgrade Report. |
Version | Dynamically updates the version number when upgrade is successful. The text is red when the IP requires upgrade. |
Device Family | Dynamically updates to the new device family when migration is successful. The text is red when the IP core requires upgrade. |
Auto Upgrade | Runs automatic upgrade on all IP cores that support auto upgrade. Also, automatically generates a <Project Directory> /ip_upgrade_port_diff_reports report for IP cores or Platform Designer systems that fail upgrade. Review these reports to determine any port differences between the current and previous IP core version. |
- If the current version of the software does not support the IP variant, right-click the component and click Remove IP Component from Project. Replace this IP core or Platform Designer system with the one supported in the current version of the software.
- If the current target device does not support the IP variant, select a supported device family for the project, or replace the IP variant with a suitable replacement that supports your target device.
- If an upgrade or migration fails, click Failed in the Status field to display and review details of the IP Upgrade Report. Click the Release Notes link for the latest known issues about the IP core. Use this information to determine the nature of the upgrade or migration failure and make corrections before upgrade.
- Run Auto Upgrade to automatically generate an IP Ports Diff report for each IP core or Platform Designer system that you upgrade. Review the reports to determine any port differences between the current and previous IP core version. Click Upgrade in Editor to make specific port changes and regenerate your IP core or Platform Designer system.
- If your IP core or Platform Designer system does not support Auto Upgrade, click Upgrade in Editor to resolve errors and regenerate the component in the parameter editor.
1.9. Simulating Intel FPGA IP Cores
The Intel® Quartus® Prime software provides integration with many simulators and supports multiple simulation flows, including your own scripted and custom simulation flows. Whichever flow you choose, IP core simulation involves the following steps:
- Generate simulation model, testbench (or example design), and simulator setup script files.
- Set up your simulator environment and any simulation scripts.
- Compile simulation model libraries.
- Run your simulator.
1.9.1. Simulation Flows
Simulation Flow | Description |
---|---|
Scripted Simulation Flows | Scripted simulation supports custom control of all aspects of simulation, such as custom compilation commands, or multipass simulation flows. Use a version-independent top-level simulation script that "sources" Intel® Quartus® Prime-generated IP simulation setup scripts. The Intel® Quartus® Prime software generates a combined simulator setup script for all IP cores, for each supported simulator. |
NativeLink Simulation Flow | NativeLink
automates
Intel®
Quartus® Prime integration
with your EDA simulator. Setup NativeLink to generate simulation
scripts, compile simulation libraries, and automatically launch your
simulator following design compilation. Specify your own
compilation, elaboration, and simulation scripts for testbench and
simulation model files. Do not use NativeLink if you require direct
control over every aspect of simulation. Note: The
Intel®
Quartus® Prime
Pro Edition software does not support NativeLink
simulation.
|
Specialized Simulation Flows | Supports specialized simulation flows for specific design variations, including
the following:
|
1.9.2. Generating IP Simulation Files
- To specify your supported simulator and options for IP simulation file generation, click Assignment > Settings > EDA Tool Settings > Simulation.
- To parameterize a new IP variation, enable generation of simulation files, and generate the IP core synthesis and simulation files, click Tools > IP Catalog.
- To edit parameters and regenerate synthesis or simulation files for an existing IP core variation, click View > Project Navigator > IP Components.
- To edit parameters and regenerate synthesis or simulation files for an existing IP core variation, click View > Utility Windows > Project Navigator > IP Components.
File Type | Description | File Name |
---|---|---|
Simulator setup scripts | Vendor-specific scripts to compile, elaborate, and simulate Intel® FPGA IP models and simulation model library files. |
<my_dir>/aldec/riviera_setup.tcl <my_dir>/cadence/ncsim__setup.sh <my_dir>/xcelium/xcelium_setup.sh <my_dir>/mentor/msim_setup.tcl <my_dir>/synopsys/vcs/vcs_setup.sh <my_dir>/synopsys/vcsmx/vcsmx_setup.sh |
Simulation IP File ( Intel® Quartus® Prime Standard Edition) | Contains IP core simulation library mapping information. To use NativeLink, add the .qip and .sip files generated for IP to your project. | <design name>.sip |
IP functional simulation models ( Intel® Quartus® Prime Standard Edition) | IP functional simulation models are cycle-accurate VHDL or Verilog HDL models a that the Intel® Quartus® Prime software generates for some Intel FPGA IP cores. IP functional simulation models support fast functional simulation of IP using industry-standard VHDL and Verilog HDL simulators. |
<my_ip>.vho <my_ip>.vo |
IEEE encrypted models ( Intel® Quartus® Prime Standard Edition) | Intel provides Arria® V, Cyclone® V, Stratix® V, and newer simulation model libraries and IP simulation models in Verilog HDL and IEEE-encrypted Verilog HDL. Your simulator's co-simulation capabilities support VHDL simulation of these models. IEEE encrypted Verilog HDL models are significantly faster than IP functional simulation models. The Intel® Quartus® Prime Pro Edition software does not support these models. | <my_ip>.v |
1.9.3. Scripting IP Simulation
- Click Project > Upgrade IP Components > Generate Simulator Script for IP (or run the ip-setup-simulation utility) to generate or regenerate a combined simulator setup script for all IP for each simulator.
-
Use the templates in the generated script to source the
combined script in your top-level simulation script. Each simulator's combined
script file contains a rudimentary template that you adapt for integration of
the setup script into a top-level simulation script.
This technique eliminates manual update of simulation scripts if you modify or upgrade the IP variation.
1.9.3.1. Generating a Combined Simulator Setup Script ( Intel Quartus Prime Pro Edition)
Source this combined script from a top-level simulation script. Click Tools > Generate Simulator Setup Script for IP (or use of the ip-setup-simulation utility at the command-line) to generate or update the combined scripts, after any of the following occur:
- IP core initial generation or regeneration with new parameters
- Intel® Quartus® Prime software version upgrade
- IP core version upgrade
- Generate, regenerate, or upgrade one or more IP core. Refer to Generating IP Cores or Upgrading IP Cores.
- Click Tools > Generate Simulator Setup Script for IP (or run the ip-setup-simulation utility). Specify the Output Directory and library compilation options. Click OK to generate the file. By default, the files generate into the /<project directory>/<simulator>/ directory using relative paths.
-
To incorporate the generated simulator setup script into your top-level simulation script, refer to the template
section in the generated simulator setup script as a guide to creating a top-level script:
- Copy the specified template sections from the simulator-specific generated scripts and paste them into a new top-level file.
- Remove the comments at the beginning of each line from the copied template sections.
-
Specify the customizations you require to match your design simulation requirements, for example:
- Specify the TOP_LEVEL_NAME variable to the design’s simulation top-level file. The top-level entity of your simulation is often a testbench that instantiates your design. Then, your design instantiates IP cores or Platform Designer systems. Set the value of TOP_LEVEL_NAME to the top-level entity.
- If necessary, set the QSYS_SIMDIR variable to point to the location of the generated IP simulation files.
- Compile the top-level HDL file (for example, a test program) and all other files in the design.
- Specify any other changes, such as using the grep command-line utility to search a transcript file for error signatures, or e-mail a report.
-
Re-run Tools > Generate Simulator Setup Script for IP (or ip-setup-simulation) after regeneration of an IP variation.
Table 9. Simulation Script Utilities Utility Syntax ip-setup-simulation generates a combined, version-independent simulation script for all Intel® FPGA IP cores in your project. The command also automates regeneration of the script after upgrading software or IP versions. Use the compile-to-work option to compile all simulation files into a single work library if your simulation environment requires. Use the --use-relative-paths option to use relative paths whenever possible. ip-setup-simulation --quartus-project=<my proj> --output-directory=<my_dir> --use-relative-paths --compile-to-work
--use-relative-paths and --compile-to-work are optional. For command-line help listing all options for these executables, type: <utility name> --help.
ip-make-simscript generates a combined simulation script for all IP cores that you specify on the command line. Specify one or more .spd files and an output directory in the command. Running the script compiles IP simulation models into various simulation libraries. ip-make-simscript --spd=<ipA.spd,ipB.spd> --output-directory=<directory>
ip-make-simscript generates a combined simulation script for all IP cores and subsystems that you specify on the command line. ip-make-simscript --system-files=<ipA.ip, ipB.ip> --output-directory=<directory>
1.9.3.1.1. Sourcing Aldec ActiveHDL or Riviera Pro Simulator Setup Scripts
-
The generated simulation script contains the following template lines. Cut and paste these
lines into a new file. For example, sim_top.tcl.
# # Start of template # # If the copied and modified template file is "aldec.do", run it as: # # vsim -c -do aldec.do # # # # Source the generated sim script # source rivierapro_setup.tcl # # Compile eda/sim_lib contents first # dev_com # # Override the top-level name (so that elab is useful) # set TOP_LEVEL_NAME top # # Compile the standalone IP. # com # # Compile the top-level # vlog -sv2k5 ../../top.sv # # Elaborate the design. # elab # # Run the simulation # run # # Report success to the shell # exit -code 0 # # End of template
-
Delete the first two characters of each line (comment and space):
# Start of template # If the copied and modified template file is "aldec.do", run it as: # vsim -c -do aldec.do # # Source the generated sim script source rivierapro_setup.tcl # Compile eda/sim_lib contents first dev_com # Override the top-level name (so that elab is useful) set TOP_LEVEL_NAME top # Compile the standalone IP. com # Compile the top-level vlog -sv2k5 ../../top.sv # Elaborate the design. elab # Run the simulation run # Report success to the shell exit -code 0 # End of template
-
Modify the TOP_LEVEL_NAME and compilation step appropriately,
depending on the simulation’s top-level file. For example:
set TOP_LEVEL_NAME sim_top vlog –sv2k5 ../../sim_top.sv
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
-
Run the new top-level script from the generated simulation directory:
vsim –c –do <path to sim_top>.tcl
1.9.3.1.2. Sourcing Cadence Incisive Simulator Setup Scripts
-
The generated simulation script contains the following template lines. Cut and
paste these lines into a new file. For example,
ncsim.sh.
# # Start of template # # If the copied and modified template file is "ncsim.sh", run it as: # # ./ncsim.sh # # # # Do the file copy, dev_com and com steps # source ncsim_setup.sh # SKIP_ELAB=1 # SKIP_SIM=1 # # # Compile the top level module # ncvlog -sv "$QSYS_SIMDIR/../top.sv" # # # Do the elaboration and sim steps # # Override the top-level name # # Override the sim options, so the simulation # # runs forever (until $finish()). # source ncsim_setup.sh # SKIP_FILE_COPY=1 # SKIP_DEV_COM=1 # SKIP_COM=1 # TOP_LEVEL_NAME=top # USER_DEFINED_SIM_OPTIONS="" # # End of template
-
Delete the first two characters of each line (comment and space):
# Start of template # If the copied and modified template file is "ncsim.sh", run it as: # ./ncsim.sh # # Do the file copy, dev_com and com steps source ncsim_setup.sh SKIP_ELAB=1 SKIP_SIM=1 # Compile the top level module ncvlog -sv "$QSYS_SIMDIR/../top.sv" # Do the elaboration and sim steps # Override the top-level name # Override the sim options, so the simulation # runs forever (until $finish()). source ncsim_setup.sh SKIP_FILE_COPY=1 SKIP_DEV_COM=1 SKIP_COM=1 TOP_LEVEL_NAME=top USER_DEFINED_SIM_OPTIONS="" # End of template
-
Modify the TOP_LEVEL_NAME and
compilation step appropriately, depending on the simulation’s top-level file.
For example:
TOP_LEVEL_NAME=sim_top \ ncvlog -sv "$QSYS_SIMDIR/../top.sv"
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
- Run the resulting top-level script from the generated simulation directory by specifying the path to ncsim.sh.
1.9.3.1.3. Sourcing Cadence Simulator Setup Scripts
-
The generated simulation script contains the following template lines. Cut and paste these lines into a new file.
For example, xmsim.sh.
# #Start of template # # Xcelium Simulation Script. # # If the copied and modified template file is "xmsim.sh", run it as: # # ./xmsim.sh # # # # Do the file copy, dev_com and com steps # source <script generation output directory>/xcelium/xcelium_setup.sh \ # SKIP_ELAB=1 \ # SKIP_SIM=1 \ # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \ # USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your # design> \ # USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for # your design> \ # QSYS_SIMDIR=<script generation output directory> # # # # Compile all design files and testbench files, including the top level. # # (These are all the files required for simulation other than the files # # compiled by the IP script) # # # xmvlog <compilation options> <design and testbench files> # # # # TOP_LEVEL_NAME is used in this script to set the top-level simulation # # or testbench module/entity name. # # # # Run the IP script again to elaborate and simulate the top level: # # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS. # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run # # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="". # # # source <script generation output directory>/xcelium/xcelium_setup.sh \ # SKIP_FILE_COPY=1 \ # SKIP_DEV_COM=1 \ # SKIP_COM=1 \ # TOP_LEVEL_NAME=<simulation top> \ # USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \ # USER_DEFINED_SIM_OPTIONS=<simulation options for your design> # # End of template
-
Delete the first two characters of each line (comment and space):
# Start of template # Xcelium Simulation Script (Beta Version). # If the copied and modified template file is "xmsim.sh", run it as: # ./xmsim.sh # # Do the file copy, dev_com and com steps source <script generation output directory>/xcelium/xcelium_setup.sh \ SKIP_ELAB=1 \ SKIP_SIM=1 \ USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \ USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \ USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \ QSYS_SIMDIR=<script generation output directory> # # Compile all design files and testbench files, including the top level. # (These are all the files required for simulation other than the files # compiled by the IP script) # xmvlog <compilation options> <design and testbench files> # # TOP_LEVEL_NAME is used in this script to set the top-level simulation or # testbench module/entity name. # # Run the IP script again to elaborate and simulate the top level: # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS. # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="". # source <script generation output directory>/xcelium/xcelium_setup.sh \ SKIP_FILE_COPY=1 \ SKIP_DEV_COM=1 \ SKIP_COM=1 \ TOP_LEVEL_NAME=<simulation top> \ USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \ USER_DEFINED_SIM_OPTIONS=<simulation options for your design> # End of template
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
- Run the resulting top-level script from the generated simulation directory by specifying the path to xmsim.sh.
1.9.3.1.4. Sourcing Mentor Graphics ModelSim Simulator Setup Scripts
-
The generated simulation script contains the following template lines. Cut and
paste these lines into a new file. For example,
sim_top.tcl.
# # Start of template # # If the copied and modified template file is "mentor.do", run it # # as: vsim -c -do mentor.do # # # # Source the generated sim script # source msim_setup.tcl # # Compile eda/sim_lib contents first # dev_com # # Override the top-level name (so that elab is useful) # set TOP_LEVEL_NAME top # # Compile the standalone IP. # com # # Compile the top-level # vlog -sv ../../top.sv # # Elaborate the design. # elab # # Run the simulation # run -a # # Report success to the shell # exit -code 0 # # End of template
-
Delete the first two characters of each line (comment and space):
# Start of template # If the copied and modified template file is "mentor.do", run it # as: vsim -c -do mentor.do # # Source the generated sim script source msim_setup.tcl # Compile eda/sim_lib contents first dev_com # Override the top-level name (so that elab is useful) set TOP_LEVEL_NAME top # Compile the standalone IP. com # Compile the top-level vlog -sv ../../top.sv # Elaborate the design. elab # Run the simulation run -a # Report success to the shell exit -code 0 # End of template
-
Modify the TOP_LEVEL_NAME and compilation step appropriately,
depending on the simulation’s top-level file. For example:
set TOP_LEVEL_NAME sim_top vlog -sv ../../sim_top.sv
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
-
Run the resulting top-level script from the generated simulation
directory:
vsim –c –do <path to sim_top>.tcl
1.9.3.1.5. Sourcing Synopsys VCS Simulator Setup Scripts
-
The generated simulation script contains these template lines. Cut and paste
the lines preceding the “helper file” into a new executable file. For example,
synopsys_vcs.f.
# # Start of template # # If the copied and modified template file is "vcs_sim.sh", run it # # as: ./vcs_sim.sh # # # # Override the top-level name # # specify a command file containing elaboration options # # (system verilog extension, and compile the top-level). # # Override the sim options, so the simulation # # runs forever (until $finish()). # source vcs_setup.sh # TOP_LEVEL_NAME=top # USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'" # USER_DEFINED_SIM_OPTIONS="" # # # helper file: synopsys_vcs.f # +systemverilogext+.sv # ../../../top.sv # # End of template
-
Delete the first two characters of each line (comment and space) for the
vcs.sh file, as shown below:
# Start of template # If the copied and modified template file is "vcs_sim.sh", run it # as: ./vcs_sim.sh # # Override the top-level name # specify a command file containing elaboration options # (system verilog extension, and compile the top-level). # Override the sim options, so the simulation # runs forever (until $finish()). source vcs_setup.sh TOP_LEVEL_NAME=top USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'" USER_DEFINED_SIM_OPTIONS=""
-
Delete the first two characters of each line (comment and space) for the
synopsys_vcs.f file, as shown below:
# helper file: synopsys_vcs.f +systemverilogext+.sv ../../../top.sv # End of template
-
Modify the TOP_LEVEL_NAME and compilation step appropriately,
depending on the simulation’s top-level file. For example:
TOP_LEVEL_NAME=sim_top
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
- Run the resulting top-level script from the generated simulation directory by specifying the path to vcs_sim.sh.
1.9.3.1.6. Sourcing Synopsys VCS MX Simulator Setup Scripts
-
The generated simulation script contains these template lines. Cut and paste
the lines preceding the “helper file” into a new executable file. For example,
vcsmx.sh.
# # Start of template # # If the copied and modified template file is "vcsmx_sim.sh", run # # it as: ./vcsmx_sim.sh # # # # Do the file copy, dev_com and com steps # source vcsmx_setup.sh # SKIP_ELAB=1 # SKIP_SIM=1 # # # Compile the top level module vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv" # # Do the elaboration and sim steps # # Override the top-level name # # Override the sim options, so the simulation runs # # forever (until $finish()). # source vcsmx_setup.sh # SKIP_FILE_COPY=1 # SKIP_DEV_COM=1 # SKIP_COM=1 # TOP_LEVEL_NAME="'-top top'" # USER_DEFINED_SIM_OPTIONS="" # # End of template
-
Delete the first two characters of each line (comment and space), as shown
below:
# Start of template # If the copied and modified template file is "vcsmx_sim.sh", run # it as: ./vcsmx_sim.sh # # Do the file copy, dev_com and com steps source vcsmx_setup.sh SKIP_ELAB=1 SKIP_SIM=1 # Compile the top level module vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv" # Do the elaboration and sim steps # Override the top-level name # Override the sim options, so the simulation runs # forever (until $finish()). source vcsmx_setup.sh SKIP_FILE_COPY=1 SKIP_DEV_COM=1 SKIP_COM=1 TOP_LEVEL_NAME="'-top top'" USER_DEFINED_SIM_OPTIONS="" # End of template
-
Modify the TOP_LEVEL_NAME and compilation step appropriately,
depending on the simulation’s top-level file. For example:
TOP_LEVEL_NAME=”-top sim_top’”
-
Make the appropriate changes to the compilation of the your top-level file, for
example:
vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../sim_top.sv"
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
- Run the resulting top-level script from the generated simulation directory by specifying the path to vcsmx_sim.sh.
1.9.4. Using NativeLink Simulation ( Intel Quartus Prime Standard Edition)
- Generation of simulator-specific files and simulation scripts.
- Compilation of simulation libraries.
- Launches your simulator automatically following Intel® Quartus® Prime Analysis & Elaboration, Analysis & Synthesis, or after a full compilation.
1.9.4.1. Setting Up NativeLink Simulation ( Intel Quartus Prime Standard Edition)
- Open an Intel® Quartus® Prime Standard Edition project.
-
Click Tools > Options and specify the location
of your simulator executable file.
Table 10. Execution Paths for EDA Simulators Simulator Path Mentor Graphics ModelSim-AE <drive letter>:\<simulator install path>\win32aloem (Windows) /<simulator install path>/bin (Linux)
Mentor Graphics ModelSim Mentor Graphics QuestaSim <drive letter>:\<simulator install path>\win32 (Windows) <simulator install path>/bin (Linux)
Synopsys VCS/VCS MX <simulator install path>/bin (Linux) Cadence Incisive Enterprise <simulator install path>/tools/bin (Linux) Aldec Active-HDL Aldec Riviera-PRO <drive letter>:\<simulator install path>\bin (Windows) <simulator install path>/bin (Linux)
- Click Assignments > Settings and specify options on the Simulation page and the More NativeLink Settings dialog box. Specify default options for simulation library compilation, netlist and tool command script generation, and for launching RTL or gate-level simulation automatically following compilation.
- If your design includes a testbench, turn on Compile test bench. Click Test Benches to specify options for each testbench. Alternatively, turn on Use script to compile testbench and specify the script file.
- To use a script to setup a simulation, turn on Use script to setup simulation.
1.9.4.2. Generating IP Functional Simulation Models ( Intel Quartus Prime Standard Edition)
- Turn on the Generate Simulation Model option when parameterizing the IP core.
-
When you simulate your design, compile only the .vo or .vho for these IP cores
in your simulator. Do not compile the corresponding HDL file. The encrypted HDL
file supports synthesis by only the
Intel®
Quartus® Prime
software.
Note:
- Intel® FPGA IP cores that do not require IP functional simulation models for simulation, do not provide the Generate Simulation Model option in the IP core parameter editor.
- Many recently released Intel® FPGA IP cores support RTL simulation using IEEE Verilog HDL encryption. IEEE encrypted models are significantly faster than IP functional simulation models. Simulate the models in both Verilog HDL and VHDL designs.
1.10. Synthesizing IP Cores in Other EDA Tools
The area and timing estimation netlist describes the IP core connectivity and architecture, but does not include details about the true functionality. This information enables certain third-party synthesis tools to better report area and timing estimates. In addition, synthesis tools can use the timing information to achieve timing-driven optimizations and improve the quality of results.
The Intel® Quartus® Prime software generates the <variant name>_syn.v netlist file in Verilog HDL format, regardless of the output file format you specify. If you use this netlist for synthesis, you must include the IP core wrapper file <variant name> .v or <variant name> .vhd in your Intel® Quartus® Prime project.
1.10.1. Instantiating IP Cores in HDL
1.10.1.1. Accessing HDL Code Templates
- Open a file in the text editor.
- Click Edit > Insert template.
- In the Insert Template dialog box, click the + icon to expand either the Verilog HDL category or the VHDL category, depending on the HDL you prefer.
- Under Full Designs, expand the navigation tree to display the type of functions you want to infer.
- Select the function to display the code in the Preview pane and click Insert.
1.10.1.1.1. Example Top-Level Verilog HDL Module
module MF_top (a, b, sel, datab, clock, result); input [31:0] a, b, datab; input clock, sel; output [31:0] result; wire [31:0] wire_dataa; assign wire_dataa = (sel)? a : b; altfp_mult inst1 (.dataa(wire_dataa), .datab(datab), .clock(clock), .result(result)); defparam inst1.pipeline = 11, inst1.width_exp = 8, inst1.width_man = 23, inst1.exception_handling = "no"; endmodule
1.10.1.1.2. Example Top-Level VHDL Module
library ieee; use ieee.std_logic_1164.all; library altera_mf; use altera_mf.altera_mf_components.all; entity MF_top is port (clock, sel : in std_logic; a, b, datab : in std_logic_vector(31 downto 0); result : out std_logic_vector(31 downto 0)); end entity; architecture arch_MF_top of MF_top is signal wire_dataa : std_logic_vector(31 downto 0); begin wire_dataa <= a when (sel = '1') else b; inst1 : altfp_mult generic map ( pipeline => 11, width_exp => 8, width_man => 23, exception_handling => "no") port map ( dataa => wire_dataa, datab => datab, clock => clock, result => result); end arch_MF_top;
1.11. Support for the IEEE 1735 Encryption Standard
The encryption key is the same for Verilog HDL and VHDL. You can pass parameters to the instantiation of an encrypted module using the same method as a non-encrypted module.
Type encrypt_1735 --help at the Intel® Quartus® Prime command line to view syntax and all supported options for the encrypt_1735 utility.
encrypt_1735 [-h | --help[=<option|topic>] | -v] encrypt_1735 <other options> Options: -------- -? -f <argument file> -h --256_bit[=<value>] --help[=<option|topic>] --language=<verilog | systemverilog| vhdl> --lower_priority --of=<some_file> --quartus --simulation[=<aldec | cadence | mentor | synopsys (comma delimited)>] --tcl_jou_file=<[tcl_jou_filename=]on|off> --tcl_log_file=<[tcl_log_filename=]on|off>
Adding the following Verilog or VHDL pragma to your RTL, along with the public key, enables the Intel® Quartus® Prime software to use the key to decrypt IP core files.
Verilog/SystemVerilog Encryption Pragma (Third-Party Tools):
`pragma protect key_keyowner="Intel Corporation" `pragma protect data_method="aes128-cbc" `pragma protect key_method="rsa" `pragma protect key_keyname="Intel-FPGA-Quartus-RSA-1" `pragma protect key_public_key <encrypted session key> `pragma protect begin `pragma protect end
VHDL Encryption Pragma (Third-Party Tools):
`protect key_keyowner = “Intel Corporation” `protect data_method="aes128-cbc" `protect key_method = “rsa” `protect key_keyname = “Intel-FPGA-Quartus-RSA-1” `protect key_block <Encrypted session key>
Only file encryption with a third-party tool requires the public encryption key. File encryption with the Intel® Quartus® Prime Pro Edition software does not require the public encryption key.
Use one of the following methods to obtain the public encryption key:
- To obtain the encryption key, login or register for a My-Intel account, and then submit an Intel® Premier Support case requesting the encryption key.
- If you are ineligible for Intel® Premier Support, you can submit a question regarding the "IEEE 1735 Encryption Public Key" to the Intel® Community Forum for assistance.
1.12. Introduction to Intel FPGA IP Cores Archives
IP Core Version | User Guide |
---|---|
19.3 | Introduction to Intel FPGA IP Cores |
18.1 | Introduction to Intel FPGA IP Cores |
18.0 | Introduction to Intel FPGA IP Cores |
1.13. Introduction to Intel FPGA IP Cores Revision History
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2020.11.09 | 20.3 |
|
2019.09.30 | 19.3 |
|
2019.05.13 | 18.1 | Updated heading title in "Support for the IEEE 1735 Encryption Standard." |
2019.04.16 | 18.1 |
|
2018.10.24 | 18.1 |
|
2018.09.24 | 18.1 |
|
2018.05.07 | 18.0 |
|
Date |
Version |
Changes |
---|---|---|
2017.11.06 | 17.1 |
|
2017.05.08 | 17.0 |
|
2016.10.31 | 16.1 |
|
2016.08.07 | 16.0 |
|
2016.05.02 | 16.0 |
|
2016.02.05 | 15.1 |
|
2015.11.02 | 15.1 |
|
2015.05.04 | 15.0 |
|
2014.12.1 | 14.1 | Added information about new Assignments > Settings > IP Settings that control frequency of synthesis file regeneration and automatic addition of IP files to the project. |
2014.08.18 |
14.0a10 |
|
June 2014 |
14.0 |
|
May 2013 |
13.0 |
|