Intel Stratix 10 Device Datasheet
Stratix 10 Device Datasheet
Device Grade | Speed Grade Supported |
---|---|
Extended |
|
Industrial |
|
The suffix after the speed grade denotes the power options offered in Stratix® 10 devices.
- V—SmartVID with standard static power
- L—0.85 V fixed voltage with low static power
- X—0.80 V fixed voltage with lowest static power
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Stratix® 10 devices.
Operating Conditions
Stratix® 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Stratix® 10 devices, you must consider the operating requirements described in this section.
The Maximum Allowed Overshoot During Transitions specifications will be available in a future release of the Stratix® 10 Device Datasheet.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Stratix® 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.
Symbol | Description | Condition | Minimum | Maximum | Unit |
---|---|---|---|---|---|
VCC | Core voltage power supply | — | –0.50 | 1.26 | V |
VCCP | Periphery circuitry and transceiver fabric interface power supply | — | –0.50 | 1.26 | V |
VCCERAM | Embedded memory and digital transceiver power supply | — | –0.50 | 1.24 | V |
VCCPT | Power supply for programmable power technology and I/O pre-driver | — | –0.50 | 2.46 | V |
VCCBAT | Battery back-up power supply for design security volatile key register | — | –0.50 | 2.46 | V |
VCCIO_SDM | Configuration pins power supply | — | –0.50 | 2.46 | V |
VCCIO | I/O buffers power supply | 3 V I/O | –0.50 | 4.10 | V |
LVDS I/O 1 | –0.50 | 2.46 | V | ||
VCCA_PLL | Phase-locked loop (PLL) analog power supply | — | –0.50 | 2.46 | V |
VCCT_GXB | Transmitter analog power supply | — | –0.50 | 1.47 | V |
VCCR_GXB | Receiver analog power supply | — | –0.50 | 1.47 | V |
VCCH_GXB | Transmitter output buffer power supply | — | –0.50 | 2.46 | V |
VCCL_HPS | HPS core voltage and periphery circuitry power supply | — | –0.50 | 1.30 | V |
VCCIO_HPS | HPS I/O buffers power supply | LVDS I/O 1 | –0.50 | 2.46 | V |
VCCPLL_HPS | HPS PLL power supply | — | –0.50 | 2.46 | V |
IOUT | DC output current per pin | — | –25 | 40 | mA |
TJ | Operating junction temperature | — | –55 | 125 | °C |
TSTG | Storage temperature (no bias) | — | –65 | 150 | °C |
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.
For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device.
Symbol | Description | Condition (V) | Overshoot Duration as % at TJ = 100°C | Unit | |
---|---|---|---|---|---|
LVDS I/O 2 | 3 V I/O | ||||
Vi (AC) | AC input voltage | 2.50 | 3.80 | 100 | % |
2.55 | 3.85 | 42 | % | ||
2.60 | 3.90 | 18 | % | ||
2.65 | 3.95 | 9 | % | ||
2.70 | 4.00 | 4 | % | ||
> 2.70 | > 4.00 | No overshoot allowed | % |
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Stratix® 10 devices.
Recommended Operating Conditions
Symbol | Description | Condition | Minimum 3 | Typical | Maximum 3 | Unit |
---|---|---|---|---|---|---|
VCC | Core voltage power supply | –E1V, –I1V, –E2V, –I2V, –E3V, –I3V 4 | 0.77 – 0.91 | 0.8 – 0.94 | 0.83 – 0.97 | V |
–E2L, –I2L | 0.82 | 0.85 | 0.88 | V | ||
–E3X, –I3X | 0.77 | 0.8 | 0.83 | V | ||
VCCP | Periphery circuitry and transceiver fabric interface power supply | –E1V, –I1V, –E2V, –I2V, –E3V, –I3V 4 | 0.77 – 0.91 | 0.8 – 0.94 | 0.83 – 0.97 | V |
–E2L, –I2L | 0.82 | 0.85 | 0.88 | V | ||
–E3X, –I3X | 0.77 | 0.8 | 0.83 | V | ||
VCCIO_SDM | Configuration pins power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCPLLDIG_SDM | Secure Device Manager (SDM) block PLL digital power supply | — | 0.87 | 0.9 | 0.93 | V |
VCCPLL_SDM | SDM block PLL analog power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCFUSEWR_SDM | Fuse block writing power supply | — | 2.35 | 2.4 | 2.45 | V |
VCCADC | ADC voltage sensor power supply | — | 1.71 | 1.8 | 1.89 | V |
VCCERAM | Embedded memory and digital transceiver power supply | 0.9 V | 0.87 | 0.9 | 0.93 | V |
VCCBAT 5 | Battery back-up power supply (For design security volatile key register) | — | 1.14 | — | 1.89 | V |
VCCPT | Power supply for programmable power technology and I/O pre-driver | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCIO | I/O buffers power supply | 3.0 V (for 3 V I/O only) | 2.85 | 3 | 3.15 | V |
2.5 V (for 3 V I/O only) | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.7 | 1.8 | 1.9 | V | ||
1.5 V | 1.4 | 1.5 | 1.6 | V | ||
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
VCCIO_UIB | Power supply for the Universal Interface Bus between the core and embedded HBM2 memory | 1.2 V | 0.9 | 1.2 | 1.5 | V |
VCCM | Power supply for the embedded HBM2 memory | — | 2.375 | 2.5 | 2.625 | V |
VCCA_PLL | PLL analog voltage regulator power supply | — | 1.71 | 1.8 | 1.89 | V |
VREFP_ADC | Precision voltage reference for voltage sensor | — | 1.2475 | 1.25 | 1.2525 | V |
VI 6 | DC input voltage | 3 V I/O | –0.3 | — | 3.6 | V |
LVDS I/O | –0.3 | — | 2.46 | V | ||
VO | Output voltage | — | 0 | — | VCCIO | V |
TJ | Operating junction temperature | Extended | 0 | — | 100 | °C |
Industrial | –40 | — | 100 | °C | ||
tRAMP 7 8 9 10 | Power supply ramp time | Standard POR | 200 μs | — | 100 ms | — |
Transceiver Power Supply Operating Conditions
Symbol | Description | Condition 11 | Minimum 12 | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
VCCT_GXB[L,R] | Transmitter power supply | Chip-to-Chip
13 ≤ 17.4 Gbps
Or Backplane 14 ≤ 12.5 Gbps |
1.0 | 1.03 | 1.06 | V |
VCCR_GXB[L,R] | Receiver power supply | Chip-to-Chip 13
≤ 17.4 Gbps
Or Backplane 14 ≤ 12.5 Gbps |
1.0 | 1.03 | 1.06 | V |
VCCH_GXB[L,R] | Transceiver high voltage power | — | 1.710 | 1.8 | 1.890 | V |
Symbol | Description | Minimum 15 | Typical | Maximum 15 | Unit |
---|---|---|---|---|---|
VCCERT | Transceiver power supply | 0.87 | 0.9 | 0.93 | V |
VCCERT_PLL | Transceiver PLL power supply | 0.87 | 0.9 | 0.93 | V |
VCCEHT | Analog power supply 15 | 1.067 | 1.1 | 1.133 | V |
VCCL | Periphery circuitry power supply | 0.725 | 0.75 | 0.775 | V |
VCCN2P5V_IO | LVPECL REFCLK power supply | 2.375 | 2.5 | 2.625 | V |
VCCR | Transceiver high voltage power supply | 1.71 | 1.8 | 1.89 | V |
HPS Power Supply Operating Conditions
Symbol | Description | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|---|
VCCL_HPS | HPS core voltage and periphery circuitry power supply | –E2L, –I2L, –E3X, –I3X | 0.91 | 0.94 | 0.97 | V |
–E1V, –I1V, –E2V, –I2V, –E3V, –I3V 16 | 0.77 – 0.91 | 0.8 – 0.94 | 0.83 – 0.97 | V | ||
VCCPLLDIG_HPS | HPS PLL digital power supply | –E2L, –I2L, –E3X, –I3X | 0.91 | 0.94 | 0.97 | V |
–E1V, –I1V, –E2V, –I2V, –E3V, –I3V 16 | 0.77 – 0.91 | 0.8 – 0.94 | 0.83 – 0.97 | V | ||
VCCPLL_HPS | HPS PLL analog power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCIO_HPS | HPS I/O buffers power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
DC Characteristics
The pin capacitance specifications will be available in a future release of the Stratix® 10 Device Datasheet.
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.
The Intel® Quartus® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.
I/O Pin Leakage Current
Symbol | Description | Condition | Min | Max | Unit |
---|---|---|---|---|---|
II | Input pin | VI = 0 V to VCCIOMAX | –80 | 80 | µA |
IOZ | Tri-stated I/O pin | VO = 0 V to VCCIOMAX | –80 | 80 | µA |
Bus Hold Specifications
The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Parameter | Symbol | Condition | VCCIO (V) | Unit | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|
1.2 | 1.5 | 1.8 | 3.0 | ||||||||
Min | Max | Min | Max | Min | Max | Min | Max | ||||
Bus-hold, low, sustaining current | ISUSL | VIN > VIL (max) | 8 | — | 12 | — | 30 | — | 70 | — | µA |
Bus-hold, high, sustaining current | ISUSH | VIN < VIH (min) | –8 | — | –12 | — | –30 | — | –70 | — | µA |
Bus-hold, low, overdrive current | IODL | 0 V < VIN < VCCIO | — | 125 | — | 175 | — | 200 | — | 500 | µA |
Bus-hold, high, overdrive current | IODH | 0 V < VIN < VCCIO | — | –125 | — | –175 | — | –200 | — | –500 | µA |
Bus-hold trip point | VTRIP | — | 0.3 | 0.9 | 0.38 | 1.13 | 0.68 | 1.07 | 0.8 | 2 | V |
OCT Calibration Accuracy Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.
Symbol | Description | Condition (V) | Calibration Accuracy | Unit | ||
---|---|---|---|---|---|---|
–E1, –I1 | –E2, –I2 | –E3, –I3 | ||||
48-Ω, 60-Ω, 80-Ω, and 240-Ω RS | Internal series termination with calibration (48-Ω, 60-Ω, 80-Ω, and 240-Ω setting) | VCCIO = 1.2 | ±15 | ±15 | ±15 | % |
34-Ω and 40-Ω RS | Internal series termination with calibration (34-Ω and 40-Ω setting) | VCCIO = 1.5, 1.35, 1.25, 1.2 | ±15 | ±15 | ±15 | % |
25-Ω and 50-Ω RS | Internal series termination with calibration (25-Ω and 50-Ω setting) | VCCIO = 3.0, 1.8, 1.5, 1.2 | ±15 | ±15 | ±15 | % |
34-Ω, 40-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω RT | Internal parallel termination with calibration (34-Ω, 40-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω setting) | POD12 I/O standard,
VCCIO = 1.2 |
±15 | ±15 | ±15 | % |
34-Ω, 48-Ω, 80-Ω, and 240-Ω RT | Internal parallel termination with calibration (34-Ω, 48-Ω, 80-Ω, and 240-Ω setting) | VCCIO = 1.2 | –10 to +40 | –10 to +40 | –10 to +40 | % |
40-Ω, 60-Ω, and 120-Ω RT | Internal parallel termination with calibration (40-Ω, 60-Ω, and 120-Ω setting) | VCCIO = 1.5, 1.35, 1.25, 1.2 | –10 to +40 | –10 to +40 | –10 to +40 | % |
25-Ω RT | Internal parallel termination with calibration (25-Ω setting) | VCCIO = 1.5 | –10 to +40 | –10 to +40 | –10 to +40 | % |
50-Ω RT | Internal parallel termination with calibration (50-Ω setting) | VCCIO = 1.8, 1.5, 1.2 | –10 to +40 | –10 to +40 | –10 to +40 | % |
OCT Without Calibration Resistance Tolerance Specifications
Symbol | Description | Condition (V) | Resistance Tolerance | Unit | ||
---|---|---|---|---|---|---|
–E1, –I1 | –E2, –I2 | –E3, –I3 | ||||
25-Ω RS | Internal series termination without calibration (25-Ω setting) | VCCIO = 1.8, 1.5 | TBD | TBD | TBD | % |
VCCIO = 1.2 | TBD | TBD | TBD | % | ||
50-Ω RS | Internal series termination without calibration (50-Ω setting) | VCCIO = 1.8, 1.5 | TBD | TBD | TBD | % |
VCCIO = 1.2 | TBD | TBD | TBD | % | ||
100-Ω RD | Internal differential termination (100-Ω setting) | VCCIO = 1.8 | ±25 | ±35 | ±40 | % |
The definitions for the equation are as follows:
- The ROCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO.
- RSCAL is the OCT resistance value at power-up.
- ΔT is the variation of temperature with respect to the temperature at power up.
- ΔV is the variation of voltage with respect to the VCCIO at power up.
- dR/dT is the percentage change of RSCAL with temperature.
- dR/dV is the percentage change of RSCAL with voltage.
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. For SDM and HPS, the configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options.
Symbol | Description | Condition (V) | Nominal Value | Unit |
---|---|---|---|---|
RPU | Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. | VCCIO = 3.0 ±5% | 25 | kΩ |
VCCIO = 1.8 ±5% | 25 | kΩ | ||
VCCIO = 1.5 ±5% | 25 | kΩ | ||
VCCIO = 1.35 ±5% | 25 | kΩ | ||
VCCIO = 1.25 ±5% | 25 | kΩ | ||
VCCIO = 1.2 ±5% | 25 | kΩ |
I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Stratix® 10 devices.
For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Single-Ended I/O Standards Specifications
I/O Standard | VCCIO (V) | VIL(V) | VIH(V) | VOL (V) | VOH (V) | IOL 17 (mA) | IOH 17 (mA) | ||||
---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Max | Min | |||
3.0-V LVTTL | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 1.7 | 3.6 | 0.4 | 2.4 | 2 | –2 |
3.0-V LVCMOS | 2.85 | 3 | 3.15 | –0.3 | 0.8 | 1.7 | 3.6 | 0.2 | VCCIO – 0.2 | 0.1 | –0.1 |
1.8 V | 1.71 | 1.8 | 1.89 | -0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.45 | VCCIO – 0.45 | 2 | –2 |
1.5 V | 1.425 | 1.5 | 1.575 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 2 | –2 |
1.2 V | 1.14 | 1.2 | 1.26 | –0.3 | 0.35 × VCCIO | 0.65 × VCCIO | VCCIO + 0.3 | 0.25 × VCCIO | 0.75 × VCCIO | 2 | –2 |
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
I/O Standard | VCCIO (V) | VREF (V) | VTT (V) | ||||||
---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | |
SSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.833 | 0.9 | 0.969 | VREF - 0.04 | VREF | VREF + 0.04 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-135 Class I, II | 1.283 | 1.35 | 1.45 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
SSTL-125 Class I, II | 1.19 | 1.25 | 1.31 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO |
HSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.85 | 0.9 | 0.95 | — | VCCIO/2 | — |
HSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.68 | 0.75 | 0.9 | — | VCCIO/2 | — |
HSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.47 × VCCIO | 0.5 × VCCIO | 0.53 × VCCIO | — | VCCIO/2 | — |
HSUL-12 | 1.14 | 1.2 | 1.3 | 0.49 × VCCIO | 0.5 × VCCIO | 0.51 × VCCIO | — | — | — |
POD12 | 1.16 | 1.2 | 1.24 | — | Internally calibrated | — | — | VCCIO | — |
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
I/O Standard | VIL(DC) (V) | VIH(DC) (V) | VIL(AC) (V) | VIH(AC) (V) | VOL (V) | VOH (V) | IOL 18 (mA) | IOH 18 (mA) | ||
---|---|---|---|---|---|---|---|---|---|---|
Min | Max | Min | Max | Max | Min | Max | Min | |||
SSTL-18 Class I | –0.3 | VREF –0.125 | VREF + 0.125 | VCCIO + 0.3 | VREF – 0.25 | VREF + 0.25 | VTT – 0.603 | VTT + 0.603 | 6.7 | –6.7 |
SSTL-18 Class II | –0.3 | VREF –0.125 | VREF + 0.125 | VCCIO + 0.3 | VREF – 0.25 | VREF + 0.25 | 0.28 | VCCIO –0.28 | 13.4 | –13.4 |
SSTL-15 Class I | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.175 | VREF + 0.175 | 0.2 × VCCIO | 0.8 × VCCIO | 8 | –8 |
SSTL-15 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.175 | VREF + 0.175 | 0.2 × VCCIO | 0.8 × VCCIO | 16 | –16 |
SSTL-135 | — | VREF – 0.09 | VREF + 0.09 | — | VREF – 0.16 | VREF + 0.16 | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
SSTL-125 | — | VREF – 0.09 | VREF + 0.09 | — | VREF – 0.15 | VREF + 0.15 | 0.2 × VCCIO | 0.8 × VCCIO | — | — |
HSTL-18 Class I | — | VREF –0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 8 | –8 |
HSTL-18 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 16 | –16 |
HSTL-15 Class I | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO – 0.4 | 8 | –8 |
HSTL-15 Class II | — | VREF – 0.1 | VREF + 0.1 | — | VREF – 0.2 | VREF + 0.2 | 0.4 | VCCIO –0.4 | 16 | –16 |
HSTL-12 Class I | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | VREF – 0.15 | VREF + 0.15 | 0.25 × VCCIO | 0.75 × VCCIO | 8 | –8 |
HSTL-12 Class II | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | VREF – 0.15 | VREF + 0.15 | 0.25 × VCCIO | 0.75 × VCCIO | 16 | –16 |
HSUL-12 | — | VREF – 0.13 | VREF + 0.13 | — | VREF – 0.22 | VREF + 0.22 | 0.1 × VCCIO | 0.9 × VCCIO | — | — |
POD12 | –0.15 | VREF – 0.08 | VREF + 0.08 | VCCIO + 0.15 | VREF – 0.15 | VREF + 0.15 | (0.7 – 0.15) × VCCIO | (0.7 + 0.15) × VCCIO | — | — |
Differential SSTL I/O Standards Specifications
I/O Standard | VCCIO (V) | VSWING(DC) (V) | VSWING(AC) (V) | VX(AC) (V) | |||||
---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Min | Max | |
SSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.25 | VCCIO + 0.6 | 0.5 | VCCIO + 0.6 | VCCIO/2 – 0.175 | VCCIO/2 + 0.175 |
SSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | 19 | 2(VIH(AC) – VREF) | 2(VREF – VIL(AC)) | VCCIO/2 – 0.15 | VCCIO/2 + 0.15 |
SSTL-135 | 1.283 | 1.35 | 1.45 | 0.18 | 19 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VCCIO/2 – 0.15 | VCCIO/2 + 0.15 |
SSTL-125 | 1.19 | 1.25 | 1.31 | 0.18 | 19 | 2(VIH(AC) – VREF) | 2(VIL(AC) – VREF) | VCCIO/2 – 0.15 | VCCIO/2 + 0.15 |
Differential HSTL and HSUL I/O Standards Specifications
I/O Standard | VCCIO (V) | VDIF(DC) (V) | VDIF(AC) (V) | VX(AC) (V) | VCM(DC) (V) | ||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Max | Min | Typ | Max | Min | Typ | Max | |
HSTL-18 Class I, II | 1.71 | 1.8 | 1.89 | 0.2 | — | 0.4 | — | 0.78 | — | 1.12 | 0.78 | — | 1.12 |
HSTL-15 Class I, II | 1.425 | 1.5 | 1.575 | 0.2 | — | 0.4 | — | 0.68 | — | 0.9 | 0.68 | — | 0.9 |
HSTL-12 Class I, II | 1.14 | 1.2 | 1.26 | 0.16 | VCCIO + 0.3 | 0.3 | VCCIO + 0.48 | — | 0.5 × VCCIO | — | 0.4 × VCCIO | 0.5 × VCCIO | 0.6 × VCCIO |
HSUL-12 | 1.14 | 1.2 | 1.3 | 2(VIH(DC) – VREF) | 2(VREF – VIH(DC)) | 2(VIH(AC) – VREF) | 2(VREF – VIH(AC)) | 0.5 × VCCIO – 0.12 | 0.5 × VCCIO | 0.5 × VCCIO +0.12 | 0.4 × VCCIO | 0.5 × VCCIO | 0.6 × VCCIO |
Differential I/O Standards Specifications
I/O Standard | VCCIO (V) | VID (mV) 20 | VICM(DC) (V) | VOD (V) 21 22 | VOCM (V) 21 | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Max | Min | Condition | Max | Min | Typ | Max | Min | Typ | Max | |
LVDS 23 | 1.71 | 1.8 | 1.89 | 100 | — | 0.05 | Data rate ≤700 Mbps | 1.65 | 0.247 | — | 0.6 | 1.125 | 1.25 | 1.375 |
1 | Data rate >700 Mbps | 1.6 | ||||||||||||
RSDS 24 | 1.71 | 1.8 | 1.89 | 100 | — | 0.3 | — | 1.4 | 0.1 | 0.2 | 0.6 | 0.5 | 1.2 | 1.4 |
Mini-LVDS 25 | 1.71 | 1.8 | 1.89 | 200 | 600 | 0.4 | — | 1.325 | 0.25 | — | 0.6 | 1 | 1.2 | 1.4 |
LVPECL 26 | 1.71 | 1.8 | 1.89 | 300 | — | 0.6 | Data rate ≤700 Mbps | 1.7 | — | — | — | — | — | — |
1 | Data rate >700 Mbps | 1.6 |
Switching Characteristics
This section provides the performance characteristics of Stratix® 10 core and periphery blocks.
L-Tile Transceiver Performance Specifications
Transceiver Performance for Stratix 10 GX/SX L-Tile Devices
Symbol/Description | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
Chip-to-Chip 27 28 |
1 Gbps to 17.4 Gbps 29 |
1.0 | 1.03 | 1.06 | V |
Backplane 27 30 | 1 Gbps to 12.5 Gbps 29 | 1.0 | 1.03 | 1.06 | V |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit |
---|---|---|---|
Supported Output Frequency | Maximum Frequency | 8.7 | GHz |
Minimum Frequency | 500 | MHz |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit |
---|---|---|---|
Supported Output Frequency | Maximum Frequency | 6.25 | GHz |
Minimum Frequency | 500 | MHz |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit |
---|---|---|---|
Supported Output Frequency | Maximum Frequency | 5.15625 | GHz |
Minimum Frequency | 2.450 | GHz |
Transceiver Specifications for Stratix 10 GX/SX L-Tile Devices
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | Dedicated reference clock pin | CML, Differential LVPECL, LVDS, and HCSL | |||
RX reference clock pin | CML, Differential LVPECL, and LVDS | ||||
Input Reference Clock Frequency (CMU PLL) |
61 | — | 800 | MHz | |
Input Reference Clock Frequency (ATX PLL) |
100 | — | 800 | MHz | |
Input Reference Clock Frequency (fPLL PLL) |
50 31 | — | 800 | MHz | |
Rise time | 20% to 80% | — | — | 400 | ps |
Fall time | 80% to 20% | — | — | 400 | ps |
Duty cycle | — | 45 | — | 55 | % |
Spread-spectrum modulating clock frequency | PCIe | 30 | — | 33 | kHz |
Spread-spectrum downspread | PCIe | — | 0 to –0.5 | — | % |
On-chip termination resistors | — | — | 100 | — | Ω |
Absolute VMAX | Dedicated reference clock pin | — | — | 1.6 | V |
RX reference clock pin | — | — | 1.2 | V | |
Absolute VMIN | — | –0.4 | — | — | V |
Peak-to-peak differential input voltage | — | 200 | — | 1600 | mV |
VICM (AC coupled) | VCCR_GXB =1.03 V | — | 1.03 | — | V |
VICM (DC coupled) | HCSL I/O standard for PCIe reference clock | 250 | — | 550 | mV |
Transmitter REFCLK Phase Noise (622 MHz) 32 | 100 Hz | — | — | –70 | dBc/Hz |
1 kHz | — | — | –90 | dBc/Hz | |
10 kHz | — | — | –100 | dBc/Hz | |
100 kHz | — | — | –110 | dBc/Hz | |
≥ 1 MHz | — | — | –120 | dBc/Hz | |
Transmitter REFCLK Phase Jitter (100 MHz) | 1.5 MHz to 100 MHz (PCIe) | — | — | 4.2 | ps (rms) |
RREF | — | — | 2.0 k ±1% | — | Ω |
TSSC-MAX-PERIOD-SLEW | Max spread spectrum clocking (SSC) df/dt | 0.75 |
Clock Network | Maximum Performance 33 | Channel Span | Unit | ||
---|---|---|---|---|---|
ATX | fPLL | CMU | |||
x1 | 17.4 | 12.5 | 10.3125 | 6 channels | Gbps |
x6 | 17.4 | 12.5 | N/A | 6 channels | Gbps |
x24 | 16 | 12.5 | N/A | 2 banks up and 2 banks down | Gbps |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O, CML, Differential LVPECL, and LVDS | |||
Absolute VMAX for a receiver pin 34 | — | — | — | 1.2 | V |
Absolute VMIN for a receiver pin 34 | — | -0.4 | — | — | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration 35 | — | — | — | 1.6 | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration 35 | VCCR_GXB = 1.03 V 36 | — | — | 2.0 | V |
Minimum differential eye opening at receiver serial input pins 37 | — | 50 | — | — | mV |
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VICM (AC and DC coupled)
non-PCIe channels |
VCCR_GXB = 1.03 V | — | 700 | — | mV |
VCCR_GXB = 1.12 V | — | 750 | — | mV | |
VICM (AC and DC coupled)
PCIe channels |
VCCR_GXB = 1.03 V | — | 650 | — | mV |
VCCR_GXB = 1.12 V | — | 650 | — | mV | |
tLTR 38 | — | — | — | 1 | ms |
tLTD 39 | — | 4 | — | — | µs |
tLTD_manual 40 | — | 4 | — | — | µs |
tLTR_LTD_manual 41 | — | 15 | — | — | µs |
Run Length | — | — | — | 200 | UI |
CDR ppm tolerance | PCIe-only | -300 | — | 300 | ppm |
All other protocols | -1000 | — | 1000 | ppm |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O 42 | — | ||
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VOCM (AC coupled) | VCCT_GXB = 1.03 V | — | 515 | — | mV |
VOCM (DC coupled) | VCCT_GXB = 1.03 V | — | 515 | — | mV |
Rise time 43 | 20% to 80% | 20 | — | 130 | ps |
Fall time 43 | 80% to 20% | 20 | — | 130 | ps |
Intra-differential pair skew 44 | TX VCM = 0.5 V and slew rate of 15 ps | — | — | 15 | ps |
Symbol | VOD Setting | VOD/VCCT_GXB Ratio |
---|---|---|
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB | 31 | 1.00 |
30 | 0.97 | |
29 | 0.93 | |
28 | 0.90 | |
27 | 0.87 | |
26 | 0.83 | |
25 | 0.80 | |
24 | 0.77 | |
23 | 0.73 | |
22 | 0.70 | |
21 | 0.67 | |
20 | 0.63 | |
19 | 0.60 | |
18 | 0.57 | |
17 | 0.53 | |
16 | 0.50 | |
15 | 0.47 | |
14 | 0.43 | |
13 | 0.40 | |
12 | 0.37 |
|
Clock | Value | Unit |
---|---|---|
reconfig_clk | ≤ 125 | MHz |
fixed_clk for the RX detect circuit | 250 ± 20% | MHz |
For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.
H-Tile Transceiver Performance Specifications
Transceiver Performance for Stratix 10 GX/SX H-Tile Devices
Channel | Symbol/Description | Transceiver Speed Grades | Minimum | Typical | Maximum | |||
---|---|---|---|---|---|---|---|---|
-1 | -2 | -3 | Unit | |||||
GX 45 46 | Chip-to-Chip |
1 Gbps to 17.4 Gbps 47 |
1 Gbps to 17.4 Gbps 47 |
1 Gbps to 17.4 Gbps 47 |
1.0 | 1.03 | 1.06 | V |
Backplane |
1 Gbps to 17.4 Gbps 47 |
1 Gbps to 17.4 Gbps 47 |
1 Gbps to 17.4 Gbps 47 |
1.0 | 1.03 | 1.06 | V | |
GXT 48 | Chip-to-Chip |
1 Gbps to 28.3 Gbps 47 |
1 Gbps to 26 Gbps 47 |
1 Gbps to 17.4 Gbps 47 |
1.10 | 1.12 | 1.14 | V |
Backplane |
1 Gbps to 28.3 Gbps 47 |
1 Gbps to 26 Gbps 47 |
1 Gbps to 17.4 Gbps 47 |
1.10 | 1.12 | 1.14 | V |
Symbol/Description | Condition | Transceiver Speed Grade 1 | Transceiver Speed Grade 2 | Transceiver Speed Grade 3 | Unit |
---|---|---|---|---|---|
Supported Output Frequency | Maximum Frequency | 14.15 | 13 | 8.7 | GHz |
Minimum Frequency | 500 | MHz |
Symbol/Description | Condition | All Transceiver Speed Grades | Unit |
---|---|---|---|
Supported Output Frequency | Maximum Frequency | 6.25 | GHz |
Minimum Frequency | 500 | MHz |
Symbol/Description | Condition | All Transceiver Speed Grades | Unit |
---|---|---|---|
Supported Output Frequency | Maximum Frequency | 5.15625 | GHz |
Minimum Frequency | 2.450 | GHz |
Transceiver Specifications for GX/SX H-Tile Devices
Symbol/Description | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|
Supported I/O Standards | Dedicated reference clock pin | CML, Differential LVPECL, LVDS, and HCSL | |||
RX reference clock pin | CML, Differential LVPECL, and LVDS | ||||
Input Reference Clock Frequency (CMU PLL) |
61 | — | 800 | MHz | |
Input Reference Clock Frequency (ATX PLL) |
100 | — | 800 | MHz | |
Input Reference Clock Frequency (fPLL PLL) |
50 49 | — | 800 | MHz | |
Rise time | 20% to 80% | — | — | 400 | ps |
Fall time | 80% to 20% | — | — | 400 | ps |
Duty cycle | — | 45 | — | 55 | % |
Spread-spectrum modulating clock frequency | PCIe | 30 | — | 33 | kHz |
Spread-spectrum downspread | PCIe | — | 0 to –0.5 | — | % |
On-chip termination resistors | — | — | 100 | — | Ω |
Absolute VMAX | Dedicated reference clock pin | — | — | 1.6 | V |
RX reference clock pin | — | — | 1.2 | V | |
Absolute VMIN | — | –0.4 | — | — | V |
Peak-to-peak differential input voltage | — | 200 | — | 1600 | mV |
VICM (AC coupled) | VCCR_GXB =1.03 V | — | 1.03 | — | V |
VCCR_GXB = 1.12 V | — | 1.12 | — | V | |
VICM (DC coupled) | HCSL I/O standard for PCIe reference clock | 250 | — | 550 | mV |
Transmitter REFCLK Phase Noise (622 MHz) 50 | 100 Hz | — | — | –70 | dBc/Hz |
1 kHz | — | — | –90 | dBc/Hz | |
10 kHz | — | — | –100 | dBc/Hz | |
100 kHz | — | — | –110 | dBc/Hz | |
≥ 1 MHz | — | — | –120 | dBc/Hz | |
Transmitter REFCLK Phase Jitter (100 MHz) | 1.5 MHz to 100 MHz (PCIe) | — | — | 4.2 | ps (rms) |
RREF | — | — | 2.0 k ±1% | — | Ω |
TSSC-MAX-PERIOD-SLEW | Max SSC df/dt | 0.75 |
Clock Network | Maximum Performance 51 | Channel Span | Unit | ||
---|---|---|---|---|---|
ATX | fPLL | CMU | |||
x1 | 17.4 | 12.5 | 10.3125 | 6 channels | Gbps |
x6 | 17.4 | 12.5 | N/A | 6 channels | Gbps |
x24 | 16 | 12.5 | N/A | 2 banks up and 2 banks down | Gbps |
GXT clock lines | 28.3 | N/A | N/A | 4 GXT channels within the same transceiver bank and 2 from the bank above or 2 from the bank below. 52 | Gbps |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O, CML, Differential LVPECL, and LVDS | |||
Absolute VMAX for a receiver pin 53 | — | — | — | 1.2 | V |
Absolute VMIN for a receiver pin 53 | — | -0.4 | — | — | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration 54 | — | — | — | 1.6 | V |
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration 54 | VCCR_GXB = 1.03 V, 1.12 V 55, 58 | — | — | 2.0 | V |
Minimum differential eye opening at receiver serial input pins 56 | — | 50 | — | — | mV |
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VICM (AC and DC coupled) 57 | VCCR_GXB = 1.03 V 58 | — | 700 | — | mV |
VCCR_GXB = 1.12 V 58 | — | 750 | — | mV | |
tLTR 59 | — | — | — | 1 | ms |
tLTD 60 | — | 4 | — | — | µs |
tLTD_manual 61 | — | 4 | — | — | µs |
tLTR_LTD_manual 62 | — | 15 | — | — | µs |
Run Length | — | — | — | 200 | UI |
CDR ppm tolerance | PCIe-only | -300 | — | 300 | ppm |
All other protocols | -1000 | — | 1000 | ppm |
Symbol/Description | Condition | Transceiver Speed Grade 3 | Unit | ||
---|---|---|---|---|---|
Min | Typ | Max | |||
Supported I/O Standards | — | High Speed Differential I/O 63 | — | ||
Differential on-chip termination resistors | 85-Ω setting | — | 85 ± 20% | — | Ω |
100-Ω setting | — | 100 ± 20% | — | Ω | |
VOCM (AC coupled) | VCCT_GXB = 1.03 V 64 | — | 515 | — | mV |
VOCM (AC coupled) | VCCT_GXB = 1.12 V 64 | — | 560 | mV | |
VOCM (DC coupled) | VCCT_GXB = 1.03 V 64 | — | 515 | — | mV |
VOCM (DC coupled) | VCCT_GXB = 1.12 V 64 | — | 560 | — | mV |
Rise time 65 | 20% to 80% | 20 | — | 130 | ps |
Fall time 65 | 80% to 20% | 20 | — | 130 | ps |
Intra-differential pair skew | TX VCM = 0.5 V and slew rate of 15 ps | — | — | 15 | ps |
Symbol | VOD Setting | VOD/VCCT_GXB Ratio |
---|---|---|
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB | 31 | 1.00 |
30 | 0.97 | |
29 | 0.93 | |
28 | 0.90 | |
27 | 0.87 | |
26 | 0.83 | |
25 | 0.80 | |
24 | 0.77 | |
23 | 0.73 | |
22 | 0.70 | |
21 | 0.67 | |
20 | 0.63 | |
19 | 0.60 | |
18 | 0.57 | |
17 | 0.53 | |
16 | 0.50 | |
15 | 0.47 | |
14 | 0.43 | |
13 | 0.40 | |
12 | 0.37 |
|
Clock | Value | Unit |
---|---|---|
reconfig_clk | ≤ 125 | MHz |
fixed_clk for the RX detect circuit | 250 ± 20% | MHz |
For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.
E-Tile Transceiver Performance Specifications
Transceiver Performance for Stratix 10 E-Tile Devices
Transceiver Reference Clock Specifications
Symbol/Description | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
I/O standard | LVPECL | ||||
Termination voltage (Vtt) | 2.5 V compliant | 0.4 | 0.5 | 0.6 | V |
3.3 V tolerant | 1.04 | 1.3 | 1.56 | V | |
Termination resistor (Rtt) | 40 | 50 | 60 | ohm | |
Differential voltage (Vdiff) | 0.4 | 0.8 | 1.2 | V | |
Input common mode voltage (Vcm) | 2.5 V compliant, no internal termination resister | Vdiff/2 | VCCN2P5V_IO-Vdiff/2 | V | |
2.5 V compliant, internal termination resister | VCCN2P5V_IO-1.6 | VCCN2P5V_IO-1.3 | VCCN2P5V_IO-1 | V | |
3.3 V tolerant, no internal termination resister | Vdiff/2 | VCCN2P5V_IO-Vdiff/2 | V | ||
3.3 V tolerant, internal termination resister | 1.4 | 2 | 2.6 | V | |
Absolute voltage | -0.5 | 2.8 | V |
Transmitter Specifications for Stratix 10 E-Tile Devices
Symbol/Description | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
Transmitter differential output voltage peak-to-peak | No precursor/postcursor de-emphasis | 0.965 | V | ||
Transmiter commom mode voltage | VCCERT/2 | V |
Receiver Specifications for Stratix 10 E-Tile Devices
Symbol/Description | Condition | Minimum | Typical | Maximum | Unit |
---|---|---|---|---|---|
Receiver run length68 | 10069 | symbols | |||
DC input impedance | 40 | 60 | ohm | ||
DC differential input impedance | 80 | 100 | 120 | ohm | |
Powered down DC input impedance | Receiver pin impendance when the receiver termination is powered down | 100k | ohm | ||
Electrical Idle detection voltage | - | 65 | 175 | mV | |
Differential termination | From DC to 100 Mhz | 80 | 100 | 120 | ohm |
PPM tolerance | Allowed frequency mismatch between REFCLK and RX data | 750 | ppm |
Core Performance Specifications
Clock Tree Specifications
Parameter | Performance | Unit | ||
---|---|---|---|---|
–E1V, –I1V | –E2V, –E2L, –I2V, –I2L | –E3V, –E3X, –I3V, –I3X | ||
Programmable clock routing | 1,100 | 900 | 780 | MHz |
PLL Specifications
Fractional PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency | — | 29 | — | 800 70 | MHz |
fINPFD | Input clock frequency to the phase frequency detector (PFD) | — | 29 | — | 700 | MHz |
fVCO | PLL voltage-controlled oscillator (VCO) operating range for transceiver applications | — | 6 | — | 12.5 | GHz |
PLL voltage-controlled oscillator (VCO) operating range for core applications | — | 4.3 | — | 12.5 | GHz | |
tEINDUTY | Input clock duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal clock | — | — | — | 1 | GHz |
fDYCONFIGCLK | Dynamic configuration clock for reconfig_clk | — | — | — | 125 | MHz |
tLOCK | Time required to lock from end-of-device configuration or deassertion of pll_powerdown | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
fCLBW | PLL closed-loop bandwidth | — | 0.3 | — | 4 | MHz |
tPLL_PSERR | Accuracy of PLL phase shift | Non-SmartVID | — | — | ±50 | ps |
SmartVID | — | — | ±75 | ps | ||
tARESET | Minimum pulse width on the pll_powerdown signal | — | 10 | — | — | ns |
tINCCJ 71, 72 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.13 | UI (p-p) |
FREF < 100 MHz | — | — | ±650 | ps (p-p) | ||
tOUTPJ 73 | Period jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ 73 | Cycle-to-cycle jitter for clock output | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
dKBIT | Bit number of Delta Sigma Modulator (DSM) | — | — | 32 | — | bit |
I/O PLL Specifications
Symbol | Parameter | Condition | Min | Typ | Max | Unit |
---|---|---|---|---|---|---|
fIN | Input clock frequency | –1 speed grade | 10 | — | 1,100 74 | MHz |
–2 speed grade | 10 | — | 900 74 | MHz | ||
–3 speed grade | 10 | — | 750 74 | MHz | ||
fINPFD | Input clock frequency to the PFD | — | 10 | — | 325 | MHz |
fVCO | PLL VCO operating range | –1 speed grade | 600 | — | 1,600 | MHz |
–2 speed grade | 600 | — | 1,434 | MHz | ||
–3 speed grade | 600 | — | 1,250 | MHz | ||
fCLBW | PLL closed-loop bandwidth | — | 0.5 | — | 10 | MHz |
tEINDUTY | Input clock or external feedback clock input duty cycle | — | 40 | — | 60 | % |
fOUT | Output frequency for internal clock (C counter) | –1 speed grade | — | — | 1,100 | MHz |
–2 speed grade | — | — | 900 | MHz | ||
–3 speed grade | — | — | 750 | MHz | ||
fOUT_EXT | Output frequency for external clock output | –1 speed grade | — | — | 800 | MHz |
–2 speed grade | — | — | 720 | MHz | ||
–3 speed grade | — | — | 650 | MHz | ||
tOUTDUTY | Duty cycle for dedicated external clock output (when set to 50%) | Non-SmartVID | 45 | 50 | 55 | % |
SmartVID | 42 | 50 | 58 | % | ||
tFCOMP | External feedback clock compensation time | — | — | — | 5 | ns |
fDYCONFIGCLK | Dynamic configuration clock for mgmt_clk and scanclk | — | — | — | 200 | MHz |
tLOCK | Time required to lock from end-of-device configuration or deassertion of areset | — | — | — | 1 | ms |
tDLOCK | Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) | — | — | — | 1 | ms |
tPLL_PSERR | Accuracy of PLL phase shift | — | — | — | ±50 | ps |
tARESET | Minimum pulse width on the areset signal | — | 10 | — | — | ns |
tINCCJ 75 76 | Input clock cycle-to-cycle jitter | FREF ≥ 100 MHz | — | — | 0.15 | UI (p-p) |
FREF < 100 MHz | — | — | ±750 | ps (p-p) | ||
tOUTPJ_DC | Period jitter for dedicated clock output | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tOUTCCJ_DC | Cycle-to-cycle jitter for dedicated clock output | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) | ||
tOUTPJ_IO 77 | Period jitter for clock output on the regular I/O | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tOUTCCJ_IO 77 | Cycle-to-cycle jitter for clock output on the regular I/O | FOUT ≥ 100 MHz | — | — | 600 | ps (p-p) |
FOUT < 100 MHz | — | — | 60 | mUI (p-p) | ||
tCASC_OUTPJ_DC | Period jitter for dedicated clock output in cascaded PLLs | FOUT ≥ 100 MHz | — | — | 175 | ps (p-p) |
FOUT < 100 MHz | — | — | 17.5 | mUI (p-p) |
DSP Block Specifications
Mode | Performance | Unit | ||
---|---|---|---|---|
–E1V, –I1V | –E2V, –E2L, –I2V, –I2L | –E3V, –E3X, –I3V, –I3X | ||
Fixed-point 18 × 19 multiplication mode | 1,000 | 771 | 667 | MHz |
Fixed-point 27 × 27 multiplication mode 78 | 1,000 | 771 | 667 | MHz |
Fixed-point 18 × 18 multiplier adder mode 78 | 1,000 | 771 | 667 | MHz |
Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode 78 | 1,000 | 771 | 667 | MHz |
Fixed-point 18 × 19 systolic mode | 1,000 | 771 | 667 | MHz |
Complex 18 × 19 multiplication mode | 1,000 | 771 | 667 | MHz |
Floating point multiplication mode | 750 | 579 | 500 | MHz |
Floating point adder or subtract mode | 750 | 579 | 500 | MHz |
Floating point multiplier adder or subtract mode | 750 | 579 | 500 | MHz |
Floating point multiplier accumulate mode | 750 | 579 | 500 | MHz |
Floating point vector one mode | 750 | 579 | 500 | MHz |
Floating point vector two mode | 750 | 579 | 500 | MHz |
- –E1V and –I1V: 750 MHz
- –E2V, –E2L, –I2V, and –I2L: 578 MHz
- –E3V, –E3X, –I3V, and –I3X: 507 MHz
Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Memory | Mode | Performance | |||
---|---|---|---|---|---|
–E1V, –I1V | –E2V, –E2L, –I2V, –I2L | –E3V, –E3X, –I3V, –I3X | Unit | ||
MLAB | Single port, all supported widths (×16/×32) | 1,000 | 782 | 667 | MHz |
Simple dual-port, all supported widths (×16/×32) | 1,000 | 782 | 667 | MHz | |
Simple dual-port with read-during-write option | 550 | 450 | 400 | MHz | |
ROM, all supported width (×16/×32) | 1,000 | 782 | 667 | MHz | |
M20K Block | Single-port, all supported widths | 1,000 | 782 | 667 | MHz |
Simple dual-port, all supported widths | 1,000 | 782 | 667 | MHz | |
Simple dual-port, coherent read enabled | 1,000 | 782 | 667 | MHz | |
Simple dual-port with the read-during-write option set to Old Data, all supported widths | 800 | 640 | 560 | MHz | |
Simple dual-port with ECC enabled, 512 × 32 | 600 | 480 | 420 | MHz | |
Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32 | 1,000 | 782 | 667 | MHz | |
True dual port, all supported widths | 600 | 480 | 420 | MHz | |
Simple quad-port, all supported widths | 600 | 480 | 420 | MHz | |
ROM, all supported widths | 1,000 | 782 | 667 | MHz | |
eSRAM | Simple dual-port | 500–750 | 500–700 | 500–640 | MHz |
Internal Temperature Sensing Diode Specifications
Temperature Range | Accuracy | Offset Calibrated Option | Sampling Rate | Conversion Time | Resolution | Minimum Resolution with no Missing Codes |
---|---|---|---|---|---|---|
–40 to 125 °C | ±5 °C | No | 1 KSPS | < 5 ms | 11 bits | 11 bits |
Internal Voltage Sensor Specifications
Parameter | Minimum | Typical | Maximum | Unit | |
---|---|---|---|---|---|
Resolution | — | 8 | — | Bit | |
Sampling rate | — | — | 1.0 79 | KSPS | |
Differential non-linearity (DNL) | — | — | ±1 | LSB | |
Integral non-linearity (INL) | — | — | ±1 | LSB | |
Input capacitance | — | — | 40 | pF | |
Clock frequency | — | — | 550 | MHz | |
Unipolar Input Mode | Input signal range for Vsigp | 0 | — | 1.5 | V |
Common mode voltage on Vsign | 0 | — | 0.25 | V | |
Input signal range for Vsigp – Vsign | 0 | — | 1.25 | V |
Periphery Performance Specifications
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Symbol | Condition | –E1V, –I1V | –E2V, –E2L, –I2L, –I2V | –E3V, –E3X, –I3X, –I3V | Unit | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
Min | Typ | Max | Min | Typ | Max | Min | Typ | Max | ||||
fHSCLK_in (input clock frequency) True Differential I/O Standards | Clock boost factor W = 1 to 40 80 | 10 | — | 800 | 10 | — | 700 | 10 | — | 625 | MHz | |
fHSCLK_in (input clock frequency) Single-Ended I/O Standards | Clock boost factor W = 1 to 40 80 | 10 | — | 625 | 10 | — | 625 | 10 | — | 525 | MHz | |
fHSCLK_OUT (output clock frequency) | — | — | — | 800 81 | — | — | 700 81 | — | — | 625 81 | MHz | |
Transmitter | True Differential I/O Standards - fHSDR (data rate) 82 | SERDES factor J = 4 to 10 83 85 84 | 85 | — | 1600 86 | 85 | — | 1434 86 | 85 | — | 1250 86 | Mbps |
SERDES factor J = 3 83 85 84 | 85 | — | 86 | 85 | — | 86 | 85 | — | 86 | Mbps | ||
SERDES factor J = 2, uses DDR registers | 85 | — | 840 86 87 | 85 | — | 86 87 | 85 | — | 86 87 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 85 | — | 420 86 87 | 85 | — | 86 87 | 85 | — | 86 87 | Mbps | ||
tx Jitter - True Differential I/O Standards | Total jitter for data rate, 600 Mbps – 1.6 Gbps | — | — | 160 | — | — | 200 | — | — | 250 | ps | |
Total jitter for data rate, < 600 Mbps | — | — | 0.1 | — | — | 0.12 | — | — | 0.15 | UI | ||
tDUTY 88 | TX output clock duty cycle for Differential I/O Standards | 45 | 50 | 55 | 45 | 50 | 55 | 45 | 50 | 55 | % | |
tRISE & tFALL 84 89 | True Differential I/O Standards | — | — | 160 | — | — | 180 | — | — | 200 | ps | |
TCCS 88 82 | True Differential I/O Standards | — | — | 150 | — | — | 150 | — | — | 150 | ps | |
Receiver | True Differential I/O Standards - fHSDRDPA (data rate) | SERDES factor J = 4 to 10 83 85 84 | — | — | 1600 | — | — | 1434 | — | — | 1250 | Mbps |
SERDES factor J = 3 83 85 84 | — | — | 86 | — | — | 86 | — | — | 86 | Mbps | ||
fHSDR (data rate) (without DPA) 82 | SERDES factor J = 3 to 10 | 85 | — | 90 | 85 | — | 90 | 85 | — | 90 | Mbps | |
SERDES factor J = 2, uses DDR registers | 85 | — | 87 | 85 | — | 87 | 85 | — | 87 | Mbps | ||
SERDES factor J = 1, uses DDR registers | 85 | — | 87 | 85 | — | 87 | 85 | — | 87 | Mbps | ||
DPA (FIFO mode) | DPA run length | — | — | — | 10000 | — | — | 10000 | — | — | 10000 | UI |
DPA (soft CDR mode) | DPA run length | SGMII/GbE protocol | — | — | 5 | — | — | 5 | — | — | 5 | UI |
All other protocols | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | — | 50 data transition per 208 UI | — | ||
Soft CDR mode | Soft-CDR ppm tolerance | — | –300 | — | 300 | –300 | — | 300 | –300 | — | 300 | ppm |
Non DPA mode | Sampling Window | — | — | — | 300 | — | — | 300 | — | — | 300 | ps |
DPA Lock Time Specifications
Standard | Training Pattern | Number of Data Transitions in One Repetition of the Training Pattern | Number of Repetitions per 256 Data Transitions 91 | Maximum Data Transition |
---|---|---|---|---|
SPI-4 | 00000000001111111111 | 2 | 128 | 640 |
Parallel Rapid I/O | 00001111 | 2 | 128 | 640 |
10010000 | 4 | 64 | 640 | |
Miscellaneous | 10101010 | 8 | 32 | 640 |
01010101 | 8 | 32 | 640 |
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Jitter Frequency (Hz) | Sinusoidal Jitter (UI) | |
---|---|---|
F1 | 10,000 | 25.00 |
F2 | 17,565 | 25.00 |
F3 | 1,493,000 | 0.35 |
F4 | 50,000,000 | 0.35 |
DLL Range Specifications
Parameter | Performance (for All Speed Grades) | Unit |
---|---|---|
DLL operating frequency range | 600 – 1,333 92 |