Intel Stratix 10 Device Datasheet

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S10-DATASHEET | 2017.08.04

Stratix 10 Device Datasheet

This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Stratix^® 10 devices.

Table 1. Stratix^® 10 Device Grades and Speed Grades Supported
Device Grade	Speed Grade Supported
Extended	–E1V (fastest) –E2V –E2L –E3V –E3X
Industrial	–I1V –I2V –I2L –I3V –I3X

The suffix after the speed grade denotes the power options offered in Stratix^® 10 devices.

V—SmartVID with standard static power
L—0.85 V fixed voltage with low static power
X—0.80 V fixed voltage with lowest static power

Electrical Characteristics

The following sections describe the operating conditions and power consumption of Stratix^® 10 devices.

Operating Conditions

Stratix^® 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Stratix^® 10 devices, you must consider the operating requirements described in this section.

The Maximum Allowed Overshoot During Transitions specifications will be available in a future release of the Stratix^® 10 Device Datasheet.

Absolute Maximum Ratings

This section defines the maximum operating conditions for Stratix^® 10 devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions.

CAUTION:

Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.

Table 2. Absolute Maximum Ratings for Stratix^® 10 Devices—Preliminary
Symbol	Description	Condition	Minimum	Maximum	Unit
V_CC	Core voltage power supply	—	–0.50	1.26	V
V_CCP	Periphery circuitry and transceiver fabric interface power supply	—	–0.50	1.26	V
V_CCERAM	Embedded memory and digital transceiver power supply	—	–0.50	1.24	V
V_CCPT	Power supply for programmable power technology and I/O pre-driver	—	–0.50	2.46	V
V_CCBAT	Battery back-up power supply for design security volatile key register	—	–0.50	2.46	V
V_{CCIO_SDM}	Configuration pins power supply	—	–0.50	2.46	V
V_CCIO	I/O buffers power supply	3 V I/O	–0.50	4.10	V
V_CCIO	I/O buffers power supply	LVDS I/O ¹	–0.50	2.46	V
V_{CCA_PLL}	Phase-locked loop (PLL) analog power supply	—	–0.50	2.46	V
V_{CCT_GXB}	Transmitter analog power supply	—	–0.50	1.47	V
V_{CCR_GXB}	Receiver analog power supply	—	–0.50	1.47	V
V_{CCH_GXB}	Transmitter output buffer power supply	—	–0.50	2.46	V
V_{CCL_HPS}	HPS core voltage and periphery circuitry power supply	—	–0.50	1.30	V
V_{CCIO_HPS}	HPS I/O buffers power supply	LVDS I/O ¹	–0.50	2.46	V
V_{CCPLL_HPS}	HPS PLL power supply	—	–0.50	2.46	V
I_OUT	DC output current per pin	—	–25	40	mA
T_J	Operating junction temperature	—	–55	125	°C
T_STG	Storage temperature (no bias)	—	–65	150	°C

¹ The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.

The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device.

Table 3. Maximum Allowed Overshoot During Transitions for Stratix^® 10 Devices—Preliminary. This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. The LVDS I/O values are applicable to the `VREFP_ADC` and `VREFN_ADC` I/O pins.
Symbol	Description	Condition (V)		Overshoot Duration as % at T_J = 100°C	Unit
Symbol	Description	LVDS I/O ²	3 V I/O	Overshoot Duration as % at T_J = 100°C	Unit
Vi (AC)	AC input voltage	2.50	3.80	100	%
		2.55	3.85	42	%
		2.60	3.90	18	%
		2.65	3.95	9	%
		2.70	4.00	4	%
		> 2.70	> 4.00	No overshoot allowed	%

² The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

Recommended Operating Conditions

This section lists the functional operation limits for the AC and DC parameters for Stratix^® 10 devices.

Recommended Operating Conditions

Table 4. Recommended Operating Conditions for Stratix^® 10 Devices—Preliminary. This table lists the steady-state voltage values expected for Stratix^® 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.
Symbol	Description	Condition	Minimum ³	Typical	Maximum ³	Unit
V_CC	Core voltage power supply	–E1V, –I1V, –E2V, –I2V, –E3V, –I3V ⁴	0.77 – 0.91	0.8 – 0.94	0.83 – 0.97	V
		–E2L, –I2L	0.82	0.85	0.88	V
		–E3X, –I3X	0.77	0.8	0.83	V
V_CCP	Periphery circuitry and transceiver fabric interface power supply	–E1V, –I1V, –E2V, –I2V, –E3V, –I3V ⁴	0.77 – 0.91	0.8 – 0.94	0.83 – 0.97	V
		–E2L, –I2L	0.82	0.85	0.88	V
		–E3X, –I3X	0.77	0.8	0.83	V
V_{CCIO_SDM}	Configuration pins power supply	1.8 V	1.71	1.8	1.89	V
V_{CCPLLDIG_SDM}	Secure Device Manager (SDM) block PLL digital power supply	—	0.87	0.9	0.93	V
V_{CCPLL_SDM}	SDM block PLL analog power supply	—	1.71	1.8	1.89	V
V_{CCFUSEWR_SDM}	Fuse block writing power supply	—	2.35	2.4	2.45	V
V_CCADC	ADC voltage sensor power supply	—	1.71	1.8	1.89	V
V_CCERAM	Embedded memory and digital transceiver power supply	0.9 V	0.87	0.9	0.93	V
V_CCBAT ⁵	Battery back-up power supply (For design security volatile key register)	—	1.14	—	1.89	V
V_CCPT	Power supply for programmable power technology and I/O pre-driver	1.8 V	1.71	1.8	1.89	V
V_CCIO	I/O buffers power supply	3.0 V (for 3 V I/O only)	2.85	3	3.15	V
		2.5 V (for 3 V I/O only)	2.375	2.5	2.625	V
		1.8 V	1.7	1.8	1.9	V
		1.5 V	1.4	1.5	1.6	V
		1.2 V	1.14	1.2	1.26	V
V_{CCIO_UIB}	Power supply for the Universal Interface Bus between the core and embedded HBM2 memory	1.2 V	0.9	1.2	1.5	V
V_CCM	Power supply for the embedded HBM2 memory	—	2.375	2.5	2.625	V
V_{CCA_PLL}	PLL analog voltage regulator power supply	—	1.71	1.8	1.89	V
V_{REFP_ADC}	Precision voltage reference for voltage sensor	—	1.2475	1.25	1.2525	V
V_I ⁶	DC input voltage	3 V I/O	–0.3	—	3.6	V
V_I ⁶	DC input voltage	LVDS I/O	–0.3	—	2.46	V
V_O	Output voltage	—	0	—	V_CCIO	V
T_J	Operating junction temperature	Extended	0	—	100	°C
T_J	Operating junction temperature	Industrial	–40	—	100	°C
t_RAMP ⁷ ⁸ ⁹ ¹⁰	Power supply ramp time	Standard POR	200 μs	—	100 ms	—

³ This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the power distribution network (PDN) tool for the additional budget for the dynamic tolerance requirements.

⁴ SmartVID graded devices require the use of a configurable voltage regulator or system controller to receive the device’s settings through the Power Management Bus (PMBus™) or Pulse-Width Modulation (PWM) interface for proper performance.

⁵ If you do not use the design security feature in Stratix^® 10 devices, connect V_CCBAT to a 1.8 V power supply. Stratix^® 10 power-on reset (POR) circuitry monitors V_CCBAT.

⁶ The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.

⁷ This is also applicable to HPS power supply. For HPS power supply, refer to t_RAMP specifications for standard POR when HPS_PORSEL = 0 and t_RAMP specifications for fast POR when HPS_PORSEL = 1.

⁸ t_RAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.

⁹ To support AS fast mode, all power supplies to the Stratix^® 10 device must be fully ramped-up within 10 ms to the recommended operating conditions.

¹⁰ To support AS normal mode, V_{CCIO_SDM} of the Stratix^® 10 device must be fully ramped-up within 10 ms to the recommended operating condition.

Transceiver Power Supply Operating Conditions

Table 5. Transceiver Power Supply Operating Conditions for Stratix^® 10 GX/SX L- and H-Tile Devices—Preliminary
Symbol	Description	Condition ¹¹	Minimum ¹²	Typical	Maximum	Unit
V_{CCT_GXB[L,R]}	Transmitter power supply	Chip-to-Chip ¹³ ≤ 17.4 Gbps Or Backplane ¹⁴ ≤ 12.5 Gbps	1.0	1.03	1.06	V
V_{CCR_GXB[L,R]}	Receiver power supply	Chip-to-Chip ¹³ ≤ 17.4 Gbps Or Backplane ¹⁴ ≤ 12.5 Gbps	1.0	1.03	1.06	V
V_{CCH_GXB[L,R]}	Transceiver high voltage power	—	1.710	1.8	1.890	V

Table 6. Transceiver Power Supply Operating Conditions for Stratix^® 10 GX/SX/TX/MX E-Tile Devices—Preliminary
Symbol	Description	Minimum ¹⁵	Typical	Maximum ¹⁵	Unit
V_CCERT	Transceiver power supply	0.87	0.9	0.93	V
V_{CCERT_PLL}	Transceiver PLL power supply	0.87	0.9	0.93	V
V_CCEHT	Analog power supply ¹⁵	1.067	1.1	1.133	V
V_CCL	Periphery circuitry power supply	0.725	0.75	0.775	V
V_{CCN2P5V_IO}	LVPECL REFCLK power supply	2.375	2.5	2.625	V
V_CCR	Transceiver high voltage power supply	1.71	1.8	1.89	V

Note: Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-tile basis to minimize power consumption. Refer to the Stratix^® 10 GX, GT, and SX Device Family Pin Connection Guidelines and the Intel^® Quartus^® Prime pin report for information about pinning out the package to minimize power consumption for your specific design.

¹¹ These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Stratix^® 10 GX/SX Devices for exact data rate ranges.

¹² This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

¹³ Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same side of the device as the channels that required 1.12 V ± 20 mV, V_{CCR_GXB} and V_{CCT_GXB} = 1.12 V ± 20 mV.

¹⁴ Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require DFE.

¹⁵ This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.

HPS Power Supply Operating Conditions

Table 7. HPS Power Supply Operating Conditions for Stratix^® 10 Devices—Preliminary. This table lists the steady-state voltage and current values expected for Stratix^® 10 system-on-a-chip (SoC) devices with ARM^®-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Stratix^® 10 Devices table for the steady-state voltage values expected from the FPGA portion of the Stratix^® 10 SoC devices.
Symbol	Description	Condition	Minimum	Typical	Maximum	Unit
V_{CCL_HPS}	HPS core voltage and periphery circuitry power supply	–E2L, –I2L, –E3X, –I3X	0.91	0.94	0.97	V
V_{CCL_HPS}	HPS core voltage and periphery circuitry power supply	–E1V, –I1V, –E2V, –I2V, –E3V, –I3V ¹⁶	0.77 – 0.91	0.8 – 0.94	0.83 – 0.97	V
V_{CCPLLDIG_HPS}	HPS PLL digital power supply	–E2L, –I2L, –E3X, –I3X	0.91	0.94	0.97	V
V_{CCPLLDIG_HPS}	HPS PLL digital power supply	–E1V, –I1V, –E2V, –I2V, –E3V, –I3V ¹⁶	0.77 – 0.91	0.8 – 0.94	0.83 – 0.97	V
V_{CCPLL_HPS}	HPS PLL analog power supply	1.8 V	1.71	1.8	1.89	V
V_{CCIO_HPS}	HPS I/O buffers power supply	1.8 V	1.71	1.8	1.89	V

¹⁶ SmartVID graded devices require the use of a configurable voltage regulator or system controller to receive the device’s settings through PMBUS or PWM for proper performance.

DC Characteristics

The pin capacitance specifications will be available in a future release of the Stratix^® 10 Device Datasheet.

Supply Current and Power Consumption

Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel^® Quartus^® Prime Power Analyzer feature.

Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the usage of the resources.

The Intel^® Quartus^® Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yield very accurate power estimates.

I/O Pin Leakage Current

Table 8. I/O Pin Leakage Current for Stratix^® 10 Devices—Preliminary
Symbol	Description	Condition	Min	Max	Unit
I_I	Input pin	V_I = 0 V to V_CCIOMAX	–80	80	µA
I_OZ	Tri-stated I/O pin	V_O = 0 V to V_CCIOMAX	–80	80	µA

Bus Hold Specifications

The bus-hold trip points are based on calculated input voltages from the JEDEC standard.

Table 9. Bus Hold Parameters for Stratix^® 10 Devices—Preliminary
Parameter	Symbol	Condition	V_CCIO (V)								Unit
			1.2		1.5		1.8		3.0
			Min	Max	Min	Max	Min	Max	Min	Max
Bus-hold, low, sustaining current	I_SUSL	V_IN > V_IL (max)	8	—	12	—	30	—	70	—	µA
Bus-hold, high, sustaining current	I_SUSH	V_IN < V_IH (min)	–8	—	–12	—	–30	—	–70	—	µA
Bus-hold, low, overdrive current	I_ODL	0 V < V_IN < V_CCIO	—	125	—	175	—	200	—	500	µA
Bus-hold, high, overdrive current	I_ODH	0 V < V_IN < V_CCIO	—	–125	—	–175	—	–200	—	–500	µA
Bus-hold trip point	V_TRIP	—	0.3	0.9	0.38	1.13	0.68	1.07	0.8	2	V

OCT Calibration Accuracy Specifications

If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to the calibration block.

Table 10. OCT Calibration Accuracy Specifications for Stratix^® 10 Devices—Preliminary. Calibration accuracy for the calibrated on-chip series termination (R_S OCT) and on-chip parallel termination (R_T OCT) are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.
Symbol	Description	Condition (V)	Calibration Accuracy			Unit
Symbol	Description	Condition (V)	–E1, –I1	–E2, –I2	–E3, –I3	Unit
48-Ω, 60-Ω, 80-Ω, and 240-Ω R_S	Internal series termination with calibration (48-Ω, 60-Ω, 80-Ω, and 240-Ω setting)	V_CCIO = 1.2	±15	±15	±15	%
34-Ω and 40-Ω R_S	Internal series termination with calibration (34-Ω and 40-Ω setting)	V_CCIO = 1.5, 1.35, 1.25, 1.2	±15	±15	±15	%
25-Ω and 50-Ω R_S	Internal series termination with calibration (25-Ω and 50-Ω setting)	V_CCIO = 3.0, 1.8, 1.5, 1.2	±15	±15	±15	%
34-Ω, 40-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω R_T	Internal parallel termination with calibration (34-Ω, 40-Ω, 48-Ω, 60-Ω, 80-Ω, 120-Ω, and 240-Ω setting)	POD12 I/O standard, V_CCIO = 1.2	±15	±15	±15	%
34-Ω, 48-Ω, 80-Ω, and 240-Ω R_T	Internal parallel termination with calibration (34-Ω, 48-Ω, 80-Ω, and 240-Ω setting)	V_CCIO = 1.2	–10 to +40	–10 to +40	–10 to +40	%
40-Ω, 60-Ω, and 120-Ω R_T	Internal parallel termination with calibration (40-Ω, 60-Ω, and 120-Ω setting)	V_CCIO = 1.5, 1.35, 1.25, 1.2	–10 to +40	–10 to +40	–10 to +40	%
25-Ω R_T	Internal parallel termination with calibration (25-Ω setting)	V_CCIO = 1.5	–10 to +40	–10 to +40	–10 to +40	%
50-Ω R_T	Internal parallel termination with calibration (50-Ω setting)	V_CCIO = 1.8, 1.5, 1.2	–10 to +40	–10 to +40	–10 to +40	%

OCT Without Calibration Resistance Tolerance Specifications

Table 11. OCT Without Calibration Resistance Tolerance Specifications for Stratix^® 10 Devices—Preliminary. This table lists the Stratix^® 10 OCT without calibration resistance tolerance to PVT changes.
Symbol	Description	Condition (V)	Resistance Tolerance			Unit
Symbol	Description	Condition (V)	–E1, –I1	–E2, –I2	–E3, –I3	Unit
25-Ω R_S	Internal series termination without calibration (25-Ω setting)	V_CCIO = 1.8, 1.5	TBD	TBD	TBD	%
25-Ω R_S		V_CCIO = 1.2	TBD	TBD	TBD	%
50-Ω R_S	Internal series termination without calibration (50-Ω setting)	V_CCIO = 1.8, 1.5	TBD	TBD	TBD	%
50-Ω R_S		V_CCIO = 1.2	TBD	TBD	TBD	%
100-Ω R_D	Internal differential termination (100-Ω setting)	V_CCIO = 1.8	±25	±35	±40	%

Figure 1. Equation for OCT Variation Without Recalibration—Preliminary

The definitions for the equation are as follows:

The R_OCT value calculated shows the range of OCT resistance with the variation of temperature and V_CCIO.
R_SCAL is the OCT resistance value at power-up.
ΔT is the variation of temperature with respect to the temperature at power up.
ΔV is the variation of voltage with respect to the V_CCIO at power up.
dR/dT is the percentage change of R_SCAL with temperature.
dR/dV is the percentage change of R_SCAL with voltage.

Internal Weak Pull-Up Resistor

All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. For SDM and HPS, the configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options.

Table 12. Internal Weak Pull-Up Resistor Values for Stratix^® 10 Devices—Preliminary
Symbol	Description	Condition (V)	Nominal Value	Unit
R_PU	Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option.	V_CCIO = 3.0 ±5%	25	kΩ
		V_CCIO = 1.8 ±5%	25	kΩ
		V_CCIO = 1.5 ±5%	25	kΩ
		V_CCIO = 1.35 ±5%	25	kΩ
		V_CCIO = 1.25 ±5%	25	kΩ
		V_CCIO = 1.2 ±5%	25	kΩ

I/O Standard Specifications

Tables in this section list the input voltage (V_IH and V_IL), output voltage (V_OH and V_OL), and current drive characteristics (I_OH and I_OL) for various I/O standards supported by Stratix^® 10 devices.

For minimum voltage values, use the minimum V_CCIO values. For maximum voltage values, use the maximum V_CCIO values.

You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.

Single-Ended I/O Standards Specifications

Table 13. Single-Ended I/O Standards Specifications for Stratix^® 10 Devices—Preliminary
I/O Standard	V_CCIO(V)			V_IL(V)		V_IH(V)		V_OL(V)	V_OH(V)	I_OL ¹⁷ (mA)	I_OH ¹⁷ (mA)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Max	Min	I_OL ¹⁷ (mA)	I_OH ¹⁷ (mA)
3.0-V LVTTL	2.85	3	3.15	–0.3	0.8	1.7	3.6	0.4	2.4	2	–2
3.0-V LVCMOS	2.85	3	3.15	–0.3	0.8	1.7	3.6	0.2	V_CCIO – 0.2	0.1	–0.1
1.8 V	1.71	1.8	1.89	-0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.45	V_CCIO – 0.45	2	–2
1.5 V	1.425	1.5	1.575	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.25 × V_CCIO	0.75 × V_CCIO	2	–2
1.2 V	1.14	1.2	1.26	–0.3	0.35 × V_CCIO	0.65 × V_CCIO	V_CCIO + 0.3	0.25 × V_CCIO	0.75 × V_CCIO	2	–2

¹⁷ To meet the I_OL and I_OH specifications, you must set the current strength settings accordingly. For example, to meet the 1.8- V LVCMOS specification (4 mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet the I_OL and I_OH specifications in the datasheet.

Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications

Table 14. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Stratix^® 10 Devices—Preliminary
I/O Standard	V_CCIO (V)			V_REF (V)			V_TT (V)
I/O Standard	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max
SSTL-18  Class I, II	1.71	1.8	1.89	0.833	0.9	0.969	V_REF - 0.04	V_REF	V_REF + 0.04
SSTL-15  Class I, II	1.425	1.5	1.575	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-135  Class I, II	1.283	1.35	1.45	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
SSTL-125  Class I, II	1.19	1.25	1.31	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO
HSTL-18  Class I, II	1.71	1.8	1.89	0.85	0.9	0.95	—	V_CCIO/2	—
HSTL-15  Class I, II	1.425	1.5	1.575	0.68	0.75	0.9	—	V_CCIO/2	—
HSTL-12  Class I, II	1.14	1.2	1.26	0.47 × V_CCIO	0.5 × V_CCIO	0.53 × V_CCIO	—	V_CCIO/2	—
HSUL-12	1.14	1.2	1.3	0.49 × V_CCIO	0.5 × V_CCIO	0.51 × V_CCIO	—	—	—
POD12	1.16	1.2	1.24	—	Internally calibrated	—	—	V_CCIO	—

Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications

Table 15. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Stratix^® 10 Devices—Preliminary
I/O Standard	V_IL(DC)(V)		V_IH(DC) (V)		V_IL(AC) (V)	V_IH(AC) (V)	V_OL (V)	V_OH (V)	I_OL ¹⁸ (mA)	I_OH ¹⁸ (mA)
I/O Standard	Min	Max	Min	Max	Max	Min	Max	Min	I_OL ¹⁸ (mA)	I_OH ¹⁸ (mA)
SSTL-18 Class I	–0.3	V_REF –0.125	V_REF + 0.125	V_CCIO + 0.3	V_REF – 0.25	V_REF + 0.25	V_TT – 0.603	V_TT + 0.603	6.7	–6.7
SSTL-18 Class II	–0.3	V_REF –0.125	V_REF + 0.125	V_CCIO + 0.3	V_REF – 0.25	V_REF + 0.25	0.28	V_CCIO –0.28	13.4	–13.4
SSTL-15 Class I	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.175	V_REF + 0.175	0.2 × V_CCIO	0.8 × V_CCIO	8	–8
SSTL-15 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.175	V_REF + 0.175	0.2 × V_CCIO	0.8 × V_CCIO	16	–16
SSTL-135	—	V_REF – 0.09	V_REF + 0.09	—	V_REF – 0.16	V_REF + 0.16	0.2 × V_CCIO	0.8 × V_CCIO	—	—
SSTL-125	—	V_REF – 0.09	V_REF + 0.09	—	V_REF – 0.15	V_REF + 0.15	0.2 × V_CCIO	0.8 × V_CCIO	—	—
HSTL-18 Class I	—	V_REF –0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	8	–8
HSTL-18 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	16	–16
HSTL-15 Class I	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO – 0.4	8	–8
HSTL-15 Class II	—	V_REF – 0.1	V_REF + 0.1	—	V_REF – 0.2	V_REF + 0.2	0.4	V_CCIO –0.4	16	–16
HSTL-12 Class I	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	V_REF – 0.15	V_REF+ 0.15	0.25 × V_CCIO	0.75 × V_CCIO	8	–8
HSTL-12 Class II	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	V_REF – 0.15	V_REF+ 0.15	0.25 × V_CCIO	0.75 × V_CCIO	16	–16
HSUL-12	—	V_REF – 0.13	V_REF + 0.13	—	V_REF – 0.22	V_REF+ 0.22	0.1 × V_CCIO	0.9 × V_CCIO	—	—
POD12	–0.15	V_REF – 0.08	V_REF + 0.08	V_CCIO + 0.15	V_REF – 0.15	V_REF+ 0.15	(0.7 – 0.15) × V_CCIO	(0.7 + 0.15) × V_CCIO	—	—

¹⁸ To meet the I_OL and I_OH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the I_OL and I_OH specifications in the datasheet.

Differential SSTL I/O Standards Specifications

Table 16. Differential SSTL I/O Standards Specifications for Stratix^® 10 Devices—Preliminary
I/O Standard	V_CCIO (V)			V_SWING(DC) (V)		V_SWING(AC) (V)		V_X(AC) (V)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Min	Max
SSTL-18 Class I, II	1.71	1.8	1.89	0.25	V_CCIO+ 0.6	0.5	V_CCIO + 0.6	V_CCIO/2 – 0.175	V_CCIO/2 + 0.175
SSTL-15 Class I, II	1.425	1.5	1.575	0.2	¹⁹	2(V_IH(AC) – V_REF)	2(V_REF – V_IL(AC))	V_CCIO/2 – 0.15	V_CCIO/2 + 0.15
SSTL-135	1.283	1.35	1.45	0.18	¹⁹	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)	V_CCIO/2 – 0.15	V_CCIO/2 + 0.15
SSTL-125	1.19	1.25	1.31	0.18	¹⁹	2(V_IH(AC) – V_REF)	2(V_IL(AC) – V_REF)	V_CCIO/2 – 0.15	V_CCIO/2 + 0.15

¹⁹ The maximum value for V_SWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits (V_IH(DC) and V_IL(DC)).

Differential HSTL and HSUL I/O Standards Specifications

Table 17. Differential HSTL and HSUL I/O Standards Specifications for Stratix^® 10 Devices—Preliminary
I/O Standard	V_CCIO (V)			V_DIF(DC) (V)		V_DIF(AC) (V)		V_X(AC) (V)			V_CM(DC) (V)
I/O Standard	Min	Typ	Max	Min	Max	Min	Max	Min	Typ	Max	Min	Typ	Max
HSTL-18 Class I, II	1.71	1.8	1.89	0.2	—	0.4	—	0.78	—	1.12	0.78	—	1.12
HSTL-15 Class I, II	1.425	1.5	1.575	0.2	—	0.4	—	0.68	—	0.9	0.68	—	0.9
HSTL-12 Class I, II	1.14	1.2	1.26	0.16	V_CCIO+ 0.3	0.3	V_CCIO + 0.48	—	0.5 × V_CCIO	—	0.4 × V_CCIO	0.5 × V_CCIO	0.6 ×  V_CCIO
HSUL-12	1.14	1.2	1.3	2(V_IH(DC) – V_REF)	2(V_REF – V_IH(DC))	2(V_IH(AC) – V_REF)	2(V_REF – V_IH(AC))	0.5 × V_CCIO – 0.12	0.5 × V_CCIO	0.5 ×  V_CCIO +0.12	0.4 × V_CCIO	0.5 × V_CCIO	0.6 ×  V_CCIO

Differential I/O Standards Specifications

Table 18. Differential I/O Standards Specifications for Stratix^® 10 Devices—Preliminary
I/O Standard	V_CCIO (V)			V_ID (mV) ²⁰		V_ICM(DC) (V)			V_OD (V) ²¹ ²²			V_OCM (V) ²¹
I/O Standard	Min	Typ	Max	Min	Max	Min	Condition	Max	Min	Typ	Max	Min	Typ	Max
LVDS ²³	1.71	1.8	1.89	100	—	0.05	Data rate ≤700 Mbps	1.65	0.247	—	0.6	1.125	1.25	1.375
LVDS ²³	1.71	1.8	1.89	100	—	1	Data rate >700 Mbps	1.6	0.247	—	0.6	1.125	1.25	1.375
RSDS ²⁴	1.71	1.8	1.89	100	—	0.3	—	1.4	0.1	0.2	0.6	0.5	1.2	1.4
Mini-LVDS ²⁵	1.71	1.8	1.89	200	600	0.4	—	1.325	0.25	—	0.6	1	1.2	1.4
LVPECL ²⁶	1.71	1.8	1.89	300	—	0.6	Data rate ≤700 Mbps	1.7	—	—	—	—	—	—
LVPECL ²⁶	1.71	1.8	1.89	300	—	1	Data rate >700 Mbps	1.6	—	—	—	—	—	—

²⁰ The minimum V_ID value is applicable over the entire common mode range, V_CM.

²¹ R_L range: 90 ≤ R_L ≤ 110 Ω.

²² The specification is only applicable to default V_OD setting.

²³ For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700 Mbps and 0.05 V to 1.65 V for data rates below 700 Mbps.

²⁴ For optimized RSDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.4 V.

²⁵ For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.4 V to 1.325 V.

²⁶ For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps.

Switching Characteristics

This section provides the performance characteristics of Stratix^® 10 core and periphery blocks.

L-Tile Transceiver Performance Specifications

Transceiver Performance for Stratix 10 GX/SX L-Tile Devices

Table 19. L-Tile Transmitter and Receiver Data Rate Performance, VCCR_GXB and VCCT_GXB Specifications—Preliminary
Symbol/Description	Condition	Minimum	Typical	Maximum	Unit
Chip-to-Chip ²⁷ ²⁸	1 Gbps to 17.4 Gbps ²⁹	1.0	1.03	1.06	V
Backplane ²⁷ ³⁰	1 Gbps to 12.5 Gbps ²⁹	1.0	1.03	1.06	V

Table 20. L-Tile ATX PLL Performance—Preliminary
Symbol/Description	Condition	Transceiver Speed Grade 3	Unit
Supported Output Frequency	Maximum Frequency	8.7	GHz
Supported Output Frequency	Minimum Frequency	500	MHz

Table 21. L-Tile Fractional PLL Performance—Preliminary
Symbol/Description	Condition	Transceiver Speed Grade 3	Unit
Supported Output Frequency	Maximum Frequency	6.25	GHz
Supported Output Frequency	Minimum Frequency	500	MHz

Table 22. L-Tile CMU PLL Performance—Preliminary
Symbol/Description	Condition	Transceiver Speed Grade 3	Unit
Supported Output Frequency	Maximum Frequency	5.15625	GHz
Supported Output Frequency	Minimum Frequency	2.450	GHz

²⁷ Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same side of the device as the channels that required 1.12 V ± 20 mV, V_{CCR_GXB} and V_{CCT_GXB} = 1.12 V ± 20 mV.

²⁸ Chip-to-chip refers to transceiver links that are short reach and dont require advanced equalization such as decision feedback equalization (DFE).

²⁹ Stratix 10 transceivers can support data rates below 1 Gbps through over sampling.

³⁰ Backplane applications refer to ones which require advanced equalization, such as DFE enabled, to compensate for channel loss.

Transceiver Specifications for Stratix 10 GX/SX L-Tile Devices

Table 23. L-Tile Reference Clock Specifications—Preliminary
Symbol/Description	Condition	Transceiver Speed Grade 3			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	Dedicated reference clock pin	CML, Differential LVPECL, LVDS, and HCSL
Supported I/O Standards	RX reference clock pin	CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency (CMU PLL)		61	—	800	MHz
Input Reference Clock Frequency (ATX PLL)		100	—	800	MHz
Input Reference Clock Frequency (fPLL PLL)		50 ³¹	—	800	MHz
Rise time	20% to 80%	—	—	400	ps
Fall time	80% to 20%	—	—	400	ps
Duty cycle	—	45	—	55	%
Spread-spectrum modulating clock frequency	PCIe	30	—	33	kHz
Spread-spectrum downspread	PCIe	—	0 to –0.5	—	%
On-chip termination resistors	—	—	100	—	Ω
Absolute V_MAX	Dedicated reference clock pin	—	—	1.6	V
Absolute V_MAX	RX reference clock pin	—	—	1.2	V
Absolute V_MIN	—	–0.4	—	—	V
Peak-to-peak differential input voltage	—	200	—	1600	mV
V_ICM (AC coupled)	V_{CCR_GXB} =1.03 V	—	1.03	—	V
V_ICM (DC coupled)	HCSL I/O standard for PCIe reference clock	250	—	550	mV
Transmitter `REFCLK` Phase Noise (622 MHz) ³²	100 Hz	—	—	–70	dBc/Hz
	1 kHz	—	—	–90	dBc/Hz
	10 kHz	—	—	–100	dBc/Hz
	100 kHz	—	—	–110	dBc/Hz
	≥ 1 MHz	—	—	–120	dBc/Hz
Transmitter `REFCLK` Phase Jitter (100 MHz)	1.5 MHz to 100 MHz (PCIe)	—	—	4.2	ps (rms)
R_REF	—	—	2.0 k ±1%	—	Ω
T_{SSC-MAX-PERIOD-SLEW}	Max spread spectrum clocking (SSC) df/dt			0.75

Table 24. L-Tile Transceiver Clock Network Maximum Data Rate Specifications—Preliminary
Clock Network	Maximum Performance ³³			Channel Span	Unit
Clock Network	ATX	fPLL	CMU	Channel Span	Unit
x1	17.4	12.5	10.3125	6 channels	Gbps
x6	17.4	12.5	N/A	6 channels	Gbps
x24	16	12.5	N/A	2 banks up and 2 banks down	Gbps

Table 25. L-Tile Receiver Specifications—Preliminary
Symbol/Description	Condition	Transceiver Speed Grade 3			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	—	High Speed Differential I/O, CML, Differential LVPECL, and LVDS
Absolute V_MAX for a receiver pin ³⁴	—	—	—	1.2	V
Absolute V_MIN for a receiver pin ³⁴	—	-0.4	—	—	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) before device configuration ³⁵	—	—	—	1.6	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) after device configuration ³⁵	V_{CCR_GXB} = 1.03 V ³⁶	—	—	2.0	V
Minimum differential eye opening at receiver serial input pins ³⁷	—	50	—	—	mV
Differential on-chip termination resistors	85-Ω setting	—	85 ± 20%	—	Ω
Differential on-chip termination resistors	100-Ω setting	—	100 ± 20%	—	Ω
V_ICM (AC and DC coupled) non-PCIe channels	V_{CCR_GXB} = 1.03 V	—	700	—	mV
V_ICM (AC and DC coupled) non-PCIe channels	V_{CCR_GXB} = 1.12 V	—	750	—	mV
V_ICM (AC and DC coupled) PCIe channels	V_{CCR_GXB} = 1.03 V	—	650	—	mV
V_ICM (AC and DC coupled) PCIe channels	V_{CCR_GXB} = 1.12 V	—	650	—	mV
t_LTR ³⁸	—	—	—	1	ms
t_LTD ³⁹	—	4	—	—	µs
t_{LTD_manual} ⁴⁰	—	4	—	—	µs
t_{LTR_LTD_manual} ⁴¹	—	15	—	—	µs
Run Length	—	—	—	200	UI
CDR ppm tolerance	PCIe-only	-300	—	300	ppm
CDR ppm tolerance	All other protocols	-1000	—	1000	ppm

Table 26. L-Tile Transmitter Specifications—Preliminary
Symbol/Description	Condition	Transceiver Speed Grade 3			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	—	High Speed Differential I/O ⁴²			—
Differential on-chip termination resistors	85-Ω setting	—	85 ± 20%	—	Ω
Differential on-chip termination resistors	100-Ω setting	—	100 ± 20%	—	Ω
V_OCM (AC coupled)	V_{CCT_GXB} = 1.03 V	—	515	—	mV
V_OCM (DC coupled)	V_{CCT_GXB} = 1.03 V	—	515	—	mV
Rise time ⁴³	20% to 80%	20	—	130	ps
Fall time ⁴³	80% to 20%	20	—	130	ps
Intra-differential pair skew ⁴⁴	TX V_CM = 0.5 V and slew rate of 15 ps	—	—	15	ps

Table 27. L-Tile Typical Transmitter V_OD Settings—Preliminary
Symbol	V_OD Setting	V_OD/V_{CCT_GXB}Ratio
V_OD differential value = V_OD/V_{CCT_GXB} ratio x V_{CCT_GXB}	31	1.00
	30	0.97
	29	0.93
	28	0.90
	27	0.87
	26	0.83
	25	0.80
	24	0.77
	23	0.73
	22	0.70
	21	0.67
	20	0.63
	19	0.60
	18	0.57
	17	0.53
	16	0.50
	15	0.47
	14	0.43
	13	0.40
	12	0.37

Table 28. L-Tile Transmitter Channel-to-channel Skew Specifications—Preliminary
Mode	Channel Span	Maximum Skew	Unit
x6 Clock	Up to 6 channels in one bank	61	ps

Table 29. Transceiver Clocks Specifications for Stratix^® 10 GX/SX L-Tile Devices—Preliminary
Clock	Value	Unit
`reconfig_clk`	≤ 125	MHz
`fixed_clk` for the RX detect circuit	250 ± 20%	MHz

For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.

³¹ The f_MIN is 29 MHz when the fPLL is used as a core PLL.

³² To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622).

³³ The maximum data rate depends on speed grade.

³⁴ The device cannot tolerate prolonged operation at this absolute maximum.

³⁵ DC coupling specifications are pending silicon characterization.

³⁶ Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same side of the device as the channels that required 1.12 V ± 20 mV, V_{CCR_GXB} and V_{CCT_GXB} = 1.12 V ± 20 mV.

³⁷ The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.

³⁸ t_LTR is the time required for the receiver CDR to lock to the input reference clock frequency after coming out of reset.

³⁹ t_LTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.

⁴⁰ t_{LTD_manual} is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.

⁴¹ t_{LTR_LTD_manual} is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.

⁴² High Speed Differential I/O is the dedicated I/O standard for the transmitter in Stratix^® 10 transceivers.

⁴³ The Intel^® Quartus^® Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.

⁴⁴ In QPI mode, if V_CM < 0.17 V, the input Vid must be greater than 100 mV. If V_CM > 0.17 V, the input Vid must be greater than 70 mV.

H-Tile Transceiver Performance Specifications

Transceiver Performance for Stratix 10 GX/SX H-Tile Devices

Table 30. H-Tile Transmitter and Receiver Data Rate Performance, VCCR_GXB and VCCT_GXB Specifications—Preliminary
Channel	Symbol/Description	Transceiver Speed Grades			Minimum	Typical	Maximum
Channel	Symbol/Description	-1	-2	-3	Minimum	Typical	Maximum	Unit
GX ⁴⁵ ⁴⁶	Chip-to-Chip	1 Gbps to 17.4 Gbps ⁴⁷	1 Gbps to 17.4 Gbps ⁴⁷	1 Gbps to 17.4 Gbps ⁴⁷	1.0	1.03	1.06	V
GX ⁴⁵ ⁴⁶	Backplane	1 Gbps to 17.4 Gbps ⁴⁷	1 Gbps to 17.4 Gbps ⁴⁷	1 Gbps to 17.4 Gbps ⁴⁷	1.0	1.03	1.06	V
GXT ⁴⁸	Chip-to-Chip	1 Gbps to 28.3 Gbps ⁴⁷	1 Gbps to 26 Gbps ⁴⁷	1 Gbps to 17.4 Gbps ⁴⁷	1.10	1.12	1.14	V
GXT ⁴⁸	Backplane	1 Gbps to 28.3 Gbps ⁴⁷	1 Gbps to 26 Gbps ⁴⁷	1 Gbps to 17.4 Gbps ⁴⁷	1.10	1.12	1.14	V

Table 31. H-Tile ATX PLL Performance—Preliminary
Symbol/Description	Condition	Transceiver Speed Grade 1	Transceiver Speed Grade 2	Transceiver Speed Grade 3	Unit
Supported Output Frequency	Maximum Frequency	14.15	13	8.7	GHz
Supported Output Frequency	Minimum Frequency	500			MHz

Table 32. H-Tile Fractional PLL Performance—Preliminary
Symbol/Description	Condition	All Transceiver Speed Grades	Unit
Supported Output Frequency	Maximum Frequency	6.25	GHz
Supported Output Frequency	Minimum Frequency	500	MHz

Table 33. H-Tile CMU PLL Performance—Preliminary
Symbol/Description	Condition	All Transceiver Speed Grades	Unit
Supported Output Frequency	Maximum Frequency	5.15625	GHz
Supported Output Frequency	Minimum Frequency	2.450	GHz

⁴⁵ GX channels are the transceiver channels that run at datarates ≤ 17.4 Gbps.

⁴⁶ Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same side of the device as the channels that require 1.12 V ± 20 mV, VCCR_GXB and VCCT_GXB = 1.12 V ± 20 mV.

⁴⁷ Stratix^® 10 transceivers can support data rates below 1 Gbps through over sampling.

⁴⁸ GXT channels are the transceiver channels that run at datarates ≤ 28.3 Gbps.

Transceiver Specifications for GX/SX H-Tile Devices

Table 34. H-Tile Reference Clock Specifications—Preliminary
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	Dedicated reference clock pin	CML, Differential LVPECL, LVDS, and HCSL
Supported I/O Standards	RX reference clock pin	CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency (CMU PLL)		61	—	800	MHz
Input Reference Clock Frequency (ATX PLL)		100	—	800	MHz
Input Reference Clock Frequency (fPLL PLL)		50 ⁴⁹	—	800	MHz
Rise time	20% to 80%	—	—	400	ps
Fall time	80% to 20%	—	—	400	ps
Duty cycle	—	45	—	55	%
Spread-spectrum modulating clock frequency	PCIe	30	—	33	kHz
Spread-spectrum downspread	PCIe	—	0 to –0.5	—	%
On-chip termination resistors	—	—	100	—	Ω
Absolute V_MAX	Dedicated reference clock pin	—	—	1.6	V
Absolute V_MAX	RX reference clock pin	—	—	1.2	V
Absolute V_MIN	—	–0.4	—	—	V
Peak-to-peak differential input voltage	—	200	—	1600	mV
V_ICM (AC coupled)	V_{CCR_GXB} =1.03 V	—	1.03	—	V
V_ICM (AC coupled)	V_{CCR_GXB} = 1.12 V	—	1.12	—	V
V_ICM (DC coupled)	HCSL I/O standard for PCIe reference clock	250	—	550	mV
Transmitter `REFCLK` Phase Noise (622 MHz) ⁵⁰	100 Hz	—	—	–70	dBc/Hz
	1 kHz	—	—	–90	dBc/Hz
	10 kHz	—	—	–100	dBc/Hz
	100 kHz	—	—	–110	dBc/Hz
	≥ 1 MHz	—	—	–120	dBc/Hz
Transmitter `REFCLK` Phase Jitter (100 MHz)	1.5 MHz to 100 MHz (PCIe)	—	—	4.2	ps (rms)
R_REF	—	—	2.0 k ±1%	—	Ω
T_{SSC-MAX-PERIOD-SLEW}	Max SSC df/dt			0.75

Table 35. H-Tile Transceiver Clock Network Maximum Data Rate Specifications—Preliminary
Clock Network	Maximum Performance ⁵¹			Channel Span	Unit
Clock Network	ATX	fPLL	CMU	Channel Span	Unit
x1	17.4	12.5	10.3125	6 channels	Gbps
x6	17.4	12.5	N/A	6 channels	Gbps
x24	16	12.5	N/A	2 banks up and 2 banks down	Gbps
GXT clock lines	28.3	N/A	N/A	4 GXT channels within the same transceiver bank and 2 from the bank above or 2 from the bank below. ⁵²	Gbps

Table 36. H-Tile Receiver Specifications—Preliminary
Symbol/Description	Condition	Transceiver Speed Grade 3			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	—	High Speed Differential I/O, CML, Differential LVPECL, and LVDS
Absolute V_MAX for a receiver pin ⁵³	—	—	—	1.2	V
Absolute V_MIN for a receiver pin ⁵³	—	-0.4	—	—	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) before device configuration ⁵⁴	—	—	—	1.6	V
Maximum peak-to-peak differential input voltage V_ID (diff p-p) after device configuration ⁵⁴	V_{CCR_GXB} = 1.03 V, 1.12 V ⁵⁵, ⁵⁸	—	—	2.0	V
Minimum differential eye opening at receiver serial input pins ⁵⁶	—	50	—	—	mV
Differential on-chip termination resistors	85-Ω setting	—	85 ± 20%	—	Ω
Differential on-chip termination resistors	100-Ω setting	—	100 ± 20%	—	Ω
V_ICM (AC and DC coupled) ⁵⁷	V_{CCR_GXB} = 1.03 V ⁵⁸	—	700	—	mV
V_ICM (AC and DC coupled) ⁵⁷	V_{CCR_GXB} = 1.12 V ⁵⁸	—	750	—	mV
t_LTR ⁵⁹	—	—	—	1	ms
t_LTD ⁶⁰	—	4	—	—	µs
t_{LTD_manual} ⁶¹	—	4	—	—	µs
t_{LTR_LTD_manual} ⁶²	—	15	—	—	µs
Run Length	—	—	—	200	UI
CDR ppm tolerance	PCIe-only	-300	—	300	ppm
CDR ppm tolerance	All other protocols	-1000	—	1000	ppm

Table 37. H-Tile Transmitter Specifications—Preliminary
Symbol/Description	Condition	Transceiver Speed Grade 3			Unit
Symbol/Description	Condition	Min	Typ	Max	Unit
Supported I/O Standards	—	High Speed Differential I/O ⁶³			—
Differential on-chip termination resistors	85-Ω setting	—	85 ± 20%	—	Ω
Differential on-chip termination resistors	100-Ω setting	—	100 ± 20%	—	Ω
V_OCM (AC coupled)	V_{CCT_GXB} = 1.03 V ⁶⁴	—	515	—	mV
V_OCM (AC coupled)	V_{CCT_GXB} = 1.12 V ⁶⁴	—	560		mV
V_OCM (DC coupled)	V_{CCT_GXB} = 1.03 V ⁶⁴	—	515	—	mV
V_OCM (DC coupled)	V_{CCT_GXB} = 1.12 V ⁶⁴	—	560	—	mV
Rise time ⁶⁵	20% to 80%	20	—	130	ps
Fall time ⁶⁵	80% to 20%	20	—	130	ps
Intra-differential pair skew	TX V_CM = 0.5 V and slew rate of 15 ps	—	—	15	ps

Table 38. H-Tile Typical Transmitter V_OD Settings—Preliminary
Symbol	V_OD Setting	V_OD/V_{CCT_GXB}Ratio
V_OD differential value = V_OD/V_{CCT_GXB} ratio x V_{CCT_GXB}	31	1.00
	30	0.97
	29	0.93
	28	0.90
	27	0.87
	26	0.83
	25	0.80
	24	0.77
	23	0.73
	22	0.70
	21	0.67
	20	0.63
	19	0.60
	18	0.57
	17	0.53
	16	0.50
	15	0.47
	14	0.43
	13	0.40
	12	0.37

Table 39. H-Tile Transmitter Channel-to-channel Skew Specifications—Preliminary
Mode	Channel Span	Maximum Skew	Unit
x6 Clock	Up to 6 channels in one bank	61	ps

Table 40. Transceiver Clocks Specifications for Stratix^® 10 GX/SX H-Tile Devices—Preliminary
Clock	Value	Unit
`reconfig_clk`	≤ 125	MHz
`fixed_clk` for the RX detect circuit	250 ± 20%	MHz

For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.

⁴⁹ The f_MIN is 29 MHz when the fPLL is used as a core PLL.

⁵⁰ To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622).

⁵¹ The maximum data rate depends on speed grade.

⁵² If the upper ATX PLL in a bank is used, then the channel span includes two GXT channels from the bank above. If the lower ATX PLL in a bank is used, then the channel span includes two channels from the bank below.

⁵³ The device cannot tolerate prolonged operation at this absolute maximum.

⁵⁴ DC coupling specifications are pending silicon characterization.

⁵⁵ Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same side of the device as the channels that required 1.12 V ± 20 mV, V_{CCR_GXB} = 1.12 V ± 20 mV.

⁵⁶ The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.

⁵⁷ Stratix^® 10 devices support DC coupling to other Stratix^® 10 devices and other devices operating under the Hybrid Memory Cube (HMC) specifications.

⁵⁸ For GXT channels, V_{CCR_GXB} must be 1.12 V. For GX channels, V_{CCR_GXB} must be 1.03 V. V_{CCR_GXB} must be 1.12 V for the transceiver on the side of the device when using GX and GXT channels together.

⁵⁹ t_LTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.

⁶⁰ t_LTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.

⁶¹ t_{LTD_manual} is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.

⁶² t_{LTR_LTD_manual} is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.

⁶³ High Speed Differential I/O is the dedicated I/O standard for the transmitter in Stratix^® 10 transceivers.

⁶⁴ For GXT channels, V_{CCT_GXB} must be 1.12 V. For GX channels, V_{CCT_GXB} must be 1.03 V. V_{CCT_GXB} must be 1.12 V for the transceiver bank when using GX and GXT channels together within the same bank.

⁶⁵ The Intel^® Quartus^® Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.

E-Tile Transceiver Performance Specifications

Transceiver Performance for Stratix 10 E-Tile Devices

Table 41. E-Tile Transmitter and Receiver Data Rate Performance Specifications—Preliminary
Symbol/Description	Condition	Minimum	Typical	Maximum	Unit
Supported datarate⁶⁶	NRZ	1		30	Gbps
Supported datarate⁶⁶	PAM-4	2		56⁶⁷	Gbps

⁶⁶ The supported datarate is for chip-to-chip and backplane links.

⁶⁷ Two channels are combined to support up to 56 Gbps.

Transceiver Reference Clock Specifications

Table 42. E-Tile Reference Clock Specifications—Preliminary
Symbol/Description	Condition	Minimum	Typical	Maximum	Unit
I/O standard		LVPECL
Termination voltage (Vtt)	2.5 V compliant	0.4	0.5	0.6	V
Termination voltage (Vtt)	3.3 V tolerant	1.04	1.3	1.56	V
Termination resistor (Rtt)		40	50	60	ohm
Differential voltage (Vdiff)		0.4	0.8	1.2	V
Input common mode voltage (Vcm)	2.5 V compliant, no internal termination resister	Vdiff/2		VCCN2P5V_IO-Vdiff/2	V
	2.5 V compliant, internal termination resister	VCCN2P5V_IO-1.6	VCCN2P5V_IO-1.3	VCCN2P5V_IO-1	V
	3.3 V tolerant, no internal termination resister	Vdiff/2		VCCN2P5V_IO-Vdiff/2	V
	3.3 V tolerant, internal termination resister	1.4	2	2.6	V
Absolute voltage		-0.5		2.8	V

Transmitter Specifications for Stratix 10 E-Tile Devices

Table 43. E-Tile Transmitter Specifications—Preliminary
Symbol/Description	Condition	Minimum	Typical	Maximum	Unit
Transmitter differential output voltage peak-to-peak	No precursor/postcursor de-emphasis		0.965		V
Transmiter commom mode voltage			V_CCERT/2		V

Receiver Specifications for Stratix 10 E-Tile Devices

Table 44. E-Tile Receiver Specifications—Preliminary
Symbol/Description	Condition	Minimum	Typical	Maximum	Unit
Receiver run length⁶⁸				100⁶⁹	symbols
DC input impedance		40		60	ohm
DC differential input impedance		80	100	120	ohm
Powered down DC input impedance	Receiver pin impendance when the receiver termination is powered down	100k			ohm
Electrical Idle detection voltage	-	65		175	mV
Differential termination	From DC to 100 Mhz	80	100	120	ohm
PPM tolerance	Allowed frequency mismatch between REFCLK and RX data			750	ppm

⁶⁸ No additional transition density requirements apply.

⁶⁹ The incoming data must be statistically DC-balanced.

Core Performance Specifications

Clock Tree Specifications

Table 45. Clock Tree Performance for Stratix^® 10 Devices—Preliminary
Parameter	Performance			Unit
Parameter	–E1V, –I1V	–E2V, –E2L, –I2V, –I2L	–E3V, –E3X, –I3V, –I3X	Unit
Programmable clock routing	1,100	900	780	MHz

PLL Specifications

Fractional PLL Specifications

Table 46. Fractional PLL Specifications for Stratix^® 10 Devices—Preliminary. These specifications are applicable when fPLL is used in core mode.
Symbol	Parameter	Condition	Min	Typ	Max	Unit
f_IN	Input clock frequency	—	29	—	800 ⁷⁰	MHz
f_INPFD	Input clock frequency to the phase frequency detector (PFD)	—	29	—	700	MHz
f_VCO	PLL voltage-controlled oscillator (VCO) operating range for transceiver applications	—	6	—	12.5	GHz
f_VCO	PLL voltage-controlled oscillator (VCO) operating range for core applications	—	4.3	—	12.5	GHz
t_EINDUTY	Input clock duty cycle	—	40	—	60	%
f_OUT	Output frequency for internal clock	—	—	—	1	GHz
f_DYCONFIGCLK	Dynamic configuration clock for `reconfig_clk`	—	—	—	125	MHz
t_LOCK	Time required to lock from end-of-device configuration or deassertion of `pll_powerdown`	—	—	—	1	ms
t_DLOCK	Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays)	—	—	—	1	ms
f_CLBW	PLL closed-loop bandwidth	—	0.3	—	4	MHz
t_{PLL_PSERR}	Accuracy of PLL phase shift	Non-SmartVID	—	—	±50	ps
t_{PLL_PSERR}	Accuracy of PLL phase shift	SmartVID	—	—	±75	ps
t_ARESET	Minimum pulse width on the `pll_powerdown` signal	—	10	—	—	ns
t_INCCJ ⁷¹, ⁷²	Input clock cycle-to-cycle jitter	F_REF ≥ 100 MHz	—	—	0.13	UI (p-p)
t_INCCJ ⁷¹, ⁷²	Input clock cycle-to-cycle jitter	F_REF < 100 MHz	—	—	±650	ps (p-p)
t_OUTPJ ⁷³	Period jitter for clock output	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_OUTPJ ⁷³	Period jitter for clock output	F_OUT < 100 MHz	—	—	60	mUI (p-p)
t_OUTCCJ ⁷³	Cycle-to-cycle jitter for clock output	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_OUTCCJ ⁷³	Cycle-to-cycle jitter for clock output	F_OUT < 100 MHz	—	—	60	mUI (p-p)
dK_BIT	Bit number of Delta Sigma Modulator (DSM)	—	—	32	—	bit

⁷⁰ This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

⁷¹ A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.

⁷² F_REF is f_IN/N, specification applies when N = 1.

⁷³ External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specifications for Stratix^® 10 Devices table.

I/O PLL Specifications

Table 47. I/O PLL Specifications for Stratix^® 10 Devices—Preliminary
Symbol	Parameter	Condition	Min	Typ	Max	Unit
f_IN	Input clock frequency	–1 speed grade	10	—	1,100 ⁷⁴	MHz
		–2 speed grade	10	—	900 ⁷⁴	MHz
		–3 speed grade	10	—	750 ⁷⁴	MHz
f_INPFD	Input clock frequency to the PFD	—	10	—	325	MHz
f_VCO	PLL VCO operating range	–1 speed grade	600	—	1,600	MHz
		–2 speed grade	600	—	1,434	MHz
		–3 speed grade	600	—	1,250	MHz
f_CLBW	PLL closed-loop bandwidth	—	0.5	—	10	MHz
t_EINDUTY	Input clock or external feedback clock input duty cycle	—	40	—	60	%
f_OUT	Output frequency for internal clock (`C` counter)	–1 speed grade	—	—	1,100	MHz
		–2 speed grade	—	—	900	MHz
		–3 speed grade	—	—	750	MHz
f_{OUT_EXT}	Output frequency for external clock output	–1 speed grade	—	—	800	MHz
		–2 speed grade	—	—	720	MHz
		–3 speed grade	—	—	650	MHz
t_OUTDUTY	Duty cycle for dedicated external clock output (when set to 50%)	Non-SmartVID	45	50	55	%
t_OUTDUTY		SmartVID	42	50	58	%
t_FCOMP	External feedback clock compensation time	—	—	—	5	ns
f_DYCONFIGCLK	Dynamic configuration clock for `mgmt_clk` and `scanclk`	—	—	—	200	MHz
t_LOCK	Time required to lock from end-of-device configuration or deassertion of `areset`	—	—	—	1	ms
t_DLOCK	Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays)	—	—	—	1	ms
t_{PLL_PSERR}	Accuracy of PLL phase shift	—	—	—	±50	ps
t_ARESET	Minimum pulse width on the `areset` signal	—	10	—	—	ns
t_INCCJ ⁷⁵ ⁷⁶	Input clock cycle-to-cycle jitter	F_REF ≥ 100 MHz	—	—	0.15	UI (p-p)
t_INCCJ ⁷⁵ ⁷⁶	Input clock cycle-to-cycle jitter	F_REF < 100 MHz	—	—	±750	ps (p-p)
t_{OUTPJ_DC}	Period jitter for dedicated clock output	F_OUT ≥ 100 MHz	—	—	175	ps (p-p)
t_{OUTPJ_DC}	Period jitter for dedicated clock output	F_OUT < 100 MHz	—	—	17.5	mUI (p-p)
t_{OUTCCJ_DC}	Cycle-to-cycle jitter for dedicated clock output	F_OUT ≥ 100 MHz	—	—	175	ps (p-p)
t_{OUTCCJ_DC}	Cycle-to-cycle jitter for dedicated clock output	F_OUT < 100 MHz	—	—	17.5	mUI (p-p)
t_{OUTPJ_IO} ⁷⁷	Period jitter for clock output on the regular I/O	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_{OUTPJ_IO} ⁷⁷	Period jitter for clock output on the regular I/O	F_OUT < 100 MHz	—	—	60	mUI (p-p)
t_{OUTCCJ_IO} ⁷⁷	Cycle-to-cycle jitter for clock output on the regular I/O	F_OUT ≥ 100 MHz	—	—	600	ps (p-p)
t_{OUTCCJ_IO} ⁷⁷	Cycle-to-cycle jitter for clock output on the regular I/O	F_OUT < 100 MHz	—	—	60	mUI (p-p)
t_{CASC_OUTPJ_DC}	Period jitter for dedicated clock output in cascaded PLLs	F_OUT ≥ 100 MHz	—	—	175	ps (p-p)
t_{CASC_OUTPJ_DC}	Period jitter for dedicated clock output in cascaded PLLs	F_OUT < 100 MHz	—	—	17.5	mUI (p-p)

⁷⁴ This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

⁷⁵ A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.

⁷⁶ F_REF is f_IN/N, specification applies when N = 1.

⁷⁷ External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specifications for Stratix^® 10 Devices table.

DSP Block Specifications

Table 48. DSP Block Performance Specifications for Stratix^® 10 Devices—Preliminary
Mode	Performance			Unit
Mode	–E1V, –I1V	–E2V, –E2L, –I2V, –I2L	–E3V, –E3X, –I3V, –I3X	Unit
Fixed-point 18 × 19 multiplication mode	1,000	771	667	MHz
Fixed-point 27 × 27 multiplication mode ⁷⁸	1,000	771	667	MHz
Fixed-point 18 × 18 multiplier adder mode ⁷⁸	1,000	771	667	MHz
Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode ⁷⁸	1,000	771	667	MHz
Fixed-point 18 × 19 systolic mode	1,000	771	667	MHz
Complex 18 × 19 multiplication mode	1,000	771	667	MHz
Floating point multiplication mode	750	579	500	MHz
Floating point adder or subtract mode	750	579	500	MHz
Floating point multiplier adder or subtract mode	750	579	500	MHz
Floating point multiplier accumulate mode	750	579	500	MHz
Floating point vector one mode	750	579	500	MHz
Floating point vector two mode	750	579	500	MHz

⁷⁸ When chainin or chainout is enabled, the performance specifications for the following speed grades are as follows:

–E1V and –I1V: 750 MHz
–E2V, –E2L, –I2V, and –I2L: 578 MHz
–E3V, –E3X, –I3V, and –I3X: 507 MHz

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel^® Quartus^® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in f_MAX.

Table 49. Memory Block Performance Specifications for Stratix^® 10 Devices—Preliminary
Memory	Mode	Performance
Memory	Mode	–E1V, –I1V	–E2V, –E2L, –I2V, –I2L	–E3V, –E3X, –I3V, –I3X	Unit
MLAB	Single port, all supported widths (×16/×32)	1,000	782	667	MHz
	Simple dual-port, all supported widths (×16/×32)	1,000	782	667	MHz
	Simple dual-port with read-during-write option	550	450	400	MHz
	ROM, all supported width (×16/×32)	1,000	782	667	MHz
M20K Block	Single-port, all supported widths	1,000	782	667	MHz
	Simple dual-port, all supported widths	1,000	782	667	MHz
	Simple dual-port, coherent read enabled	1,000	782	667	MHz
	Simple dual-port with the read-during-write option set to Old Data, all supported widths	800	640	560	MHz
	Simple dual-port with ECC enabled, 512 × 32	600	480	420	MHz
	Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32	1,000	782	667	MHz
	True dual port, all supported widths	600	480	420	MHz
	Simple quad-port, all supported widths	600	480	420	MHz
	ROM, all supported widths	1,000	782	667	MHz
eSRAM	Simple dual-port	500–750	500–700	500–640	MHz

Internal Temperature Sensing Diode Specifications

Table 50. Internal Temperature Sensing Diode Specifications for Stratix^® 10 Devices—Preliminary
Temperature Range	Accuracy	Offset Calibrated Option	Sampling Rate	Conversion Time	Resolution	Minimum Resolution with no Missing Codes
–40 to 125 °C	±5 °C	No	1 KSPS	< 5 ms	11 bits	11 bits

Internal Voltage Sensor Specifications

Table 51. Internal Voltage Sensor Specifications for Stratix^® 10 Devices—Preliminary
Parameter		Minimum	Typical	Maximum	Unit
Resolution		—	8	—	Bit
Sampling rate		—	—	1.0 ⁷⁹	KSPS
Differential non-linearity (DNL)		—	—	±1	LSB
Integral non-linearity (INL)		—	—	±1	LSB
Input capacitance		—	—	40	pF
Clock frequency		—	—	550	MHz
Unipolar Input Mode	Input signal range for Vsigp	0	—	1.5	V
	Common mode voltage on Vsign	0	—	0.25	V
	Input signal range for Vsigp – Vsign	0	—	1.25	V

⁷⁹ Pending silicon characterization.

Periphery Performance Specifications

This section describes the periphery performance, high-speed I/O, and external memory interface.

Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.

High-Speed I/O Specifications

Table 52. High-Speed I/O Specifications for Stratix^® 10 Devices—Preliminary.
When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block.

For LVDS applications, you must use the PLLs in integer PLL mode.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
Symbol		Condition	–E1V, –I1V			–E2V, –E2L, –I2L, –I2V			–E3V, –E3X, –I3X, –I3V			Unit
Symbol		Condition	Min	Typ	Max	Min	Typ	Max	Min	Typ	Max	Unit
f_{HSCLK_in}(input clock frequency) True Differential I/O Standards		Clock boost factor  W = 1 to 40 ⁸⁰	10	—	800	10	—	700	10	—	625	MHz
f_{HSCLK_in}(input clock frequency) Single-Ended I/O Standards		Clock boost factor  W = 1 to 40 ⁸⁰	10	—	625	10	—	625	10	—	525	MHz
f_{HSCLK_OUT} (output clock frequency)		—	—	—	800 ⁸¹	—	—	700 ⁸¹	—	—	625 ⁸¹	MHz
Transmitter	True Differential I/O Standards - f_HSDR (data rate) ⁸²	SERDES factor J = 4 to 10 ⁸³ ⁸⁵ ⁸⁴	⁸⁵	—	1600 ⁸⁶	⁸⁵	—	1434 ⁸⁶	⁸⁵	—	1250 ⁸⁶	Mbps
		SERDES factor J = 3 ⁸³ ⁸⁵ ⁸⁴	⁸⁵	—	⁸⁶	⁸⁵	—	⁸⁶	⁸⁵	—	⁸⁶	Mbps
		SERDES factor J = 2, uses DDR registers	⁸⁵	—	840 ⁸⁶ ⁸⁷	⁸⁵	—	⁸⁶ ⁸⁷	⁸⁵	—	⁸⁶ ⁸⁷	Mbps
		SERDES factor J = 1, uses DDR registers	⁸⁵	—	420 ⁸⁶ ⁸⁷	⁸⁵	—	⁸⁶ ⁸⁷	⁸⁵	—	⁸⁶ ⁸⁷	Mbps
	t_{x Jitter}- True Differential I/O Standards	Total jitter for data rate, 600 Mbps – 1.6 Gbps	—	—	160	—	—	200	—	—	250	ps
	t_{x Jitter}- True Differential I/O Standards	Total jitter for data rate, < 600 Mbps	—	—	0.1	—	—	0.12	—	—	0.15	UI
	t_DUTY ⁸⁸	TX output clock duty cycle for Differential I/O Standards	45	50	55	45	50	55	45	50	55	%
	t_RISE & t_FALL ⁸⁴ ⁸⁹	True Differential I/O Standards	—	—	160	—	—	180	—	—	200	ps
	TCCS ⁸⁸ ⁸²	True Differential I/O Standards	—	—	150	—	—	150	—	—	150	ps
Receiver	True Differential I/O Standards - f_HSDRDPA (data rate)	SERDES factor J = 4 to 10 ⁸³ ⁸⁵ ⁸⁴	—	—	1600	—	—	1434	—	—	1250	Mbps
	True Differential I/O Standards - f_HSDRDPA (data rate)	SERDES factor J = 3 ⁸³ ⁸⁵ ⁸⁴	—	—	⁸⁶	—	—	⁸⁶	—	—	⁸⁶	Mbps
	f_HSDR (data rate) (without DPA) ⁸²	SERDES factor J = 3 to 10	⁸⁵	—	⁹⁰	⁸⁵	—	⁹⁰	⁸⁵	—	⁹⁰	Mbps
		SERDES factor J = 2, uses DDR registers	⁸⁵	—	⁸⁷	⁸⁵	—	⁸⁷	⁸⁵	—	⁸⁷	Mbps
		SERDES factor J = 1, uses DDR registers	⁸⁵	—	⁸⁷	⁸⁵	—	⁸⁷	⁸⁵	—	⁸⁷	Mbps
DPA (FIFO mode)	DPA run length	—	—	—	10000	—	—	10000	—	—	10000	UI
DPA (soft CDR mode)	DPA run length	SGMII/GbE protocol	—	—	5	—	—	5	—	—	5	UI
DPA (soft CDR mode)	DPA run length	All other protocols	—	—	50 data transition per 208 UI	—	—	50 data transition per 208 UI	—	—	50 data transition per 208 UI	—
Soft CDR mode	Soft-CDR ppm tolerance	—	–300	—	300	–300	—	300	–300	—	300	ppm
Non DPA mode	Sampling Window	—	—	—	300	—	—	300	—	—	300	ps

⁸⁰ Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.

⁸¹ This is achieved by using the PHY clock network.

⁸² Requires package skew compensation with PCB trace length.

⁸³ The F_max specification is based on the fast clock used for serial data. The interface F_max is also dependent on the parallel clock domain which is design dependent and requires timing analysis.

⁸⁴ The V_CC and V_CCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.

⁸⁵ The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.

⁸⁶ Pending silicon characterization.

⁸⁷ The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (f_OUT) provided you can close the design timing and the signal integrity meets the interface requirements.

⁸⁸ Not applicable for DIVCLK = 1.

⁸⁹ This applies to default pre-emphasis and V_OD settings only.

⁹⁰ You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.

DPA Lock Time Specifications

Figure 2. DPA Lock Time Specifications with DPA PLL Calibration Enabled

Table 53. DPA Lock Time Specifications for Stratix^® 10 Devices—Preliminary. The specifications are applicable to both commercial and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition.
Standard	Training Pattern	Number of Data Transitions in One Repetition of the Training Pattern	Number of Repetitions per 256 Data Transitions ⁹¹	Maximum Data Transition
SPI-4	00000000001111111111	2	128	640
Parallel Rapid I/O	00001111	2	128	640
Parallel Rapid I/O	10010000	4	64	640
Miscellaneous	10101010	8	32	640
Miscellaneous	01010101	8	32	640

⁹¹ This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.

LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications

Figure 3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps

Table 54. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps—Preliminary
Jitter Frequency (Hz)		Sinusoidal Jitter (UI)
F1	10,000	25.00
F2	17,565	25.00
F3	1,493,000	0.35
F4	50,000,000	0.35

Figure 4. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps

DLL Range Specifications

Table 55. DLL Frequency Range Specifications for Stratix^® 10 Devices—Preliminary.
Parameter