AN 899: Reducing Compile Time with Fast Preservation
Version Information
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 19.3 |
1. AN 899: Reducing Compile Time with Fast Preservation
Intel® Quartus® Prime Pro Edition allows you to preserve satisfactory compilation results for FPGA periphery or core logic design blocks, and then reuse the placement and routing of those blocks in subsequent compilations. You assign the hierarchical instance as a design partition, which you can then preserve and reuse following successful compilation.
Design Setup Requirements
The use of fast preservation requires one or more reserved core partitions, and a preserved .qdb functioning as the root partition. This design partitioning is similar to that required for the device periphery reuse or partial reconfiguration (PR) implementation flow. This tutorial includes a design example to demonstrate this setup.
1.1. Tutorial Design Overview
This tutorial includes a prepared design example to demonstrate use of fast preservation. You can download the design example to follow along with the tutorial steps in the Intel® Quartus® Prime Pro Edition software, as Downloading Tutorial Design Files describes.
The example top-level design instantiates a PLL that generates a 550 MHz fast clock (CLK1), and a 100 MHz slow clock (CLK2). The top-level design also instantiates 4 blinking LED modules that drive LED[3:0] every 2, 4, 8, and 16 seconds, respectively.
To increase the design size in the Intel® FPGA, the design example also instantiates 20 duplicate instances of an OpenCores* design.1
The duplicate OpenCores* design instances have the following characteristics:
- The design implements each instance in parallel.
- I/O wrapper logic is present to reduce the number of I/O pins that the larger design requires.
- No timing-critical paths exist between the instances and the wrapper logic.
1.2. Downloading Tutorial Design Files
- Download and extract the tutorial design files at:
- View the extracted tutorial design file directory structure.
| File Name | Description |
|---|---|
| top.sv |
Top-level file that instantiates iopll, big_partition1_top, blinking_led_2s, blinking_led_4s, blinking_led_8s, and blinking_led_16s. Also includes logic to drive LED[4:7] as a single, shifting bit. |
| top.qpf | Intel® Quartus® Prime project file that stores project name and revisions. |
| top.qsf | Intel® Quartus® Prime settings file containing project assignments and settings. |
| big_partition1_top.v | Design file that instantiates 20 instances of an OpenCores* design. |
| blinking_led_2s.sv | Logic to drive LED[0] every two seconds. |
| blinking_led_4s.sv | Logic to drive LED[1] every four seconds. |
| blinking_led_8s.sv | Logic to drive LED[2] every eight seconds. |
| blinking_led_16s.sv | Logic to drive LED[3] every 16 seconds. |
| blinking_led.sdc | A Synopsys Design Constraints file that defines the 50 MHz input reference clock. |
| iopll.ip | The IOPLL Intel® FPGA IP instantiated in top. The IP uses a 50 MHz reference clock frequency, and generates 100 MHz and 550 MHz clocks. |
| tx_dcfifo.ip | The dual clock FIFO Intel® FPGA IP instantiated in blinking_led_2s, blinking_led_4s, blinking_led_8s, and blinking_led_16s instances. Has a write clock of 550 MHz and read clock of 100 MHz. |
| report_timing.tcl | A tcl script with Timing Analyzer commands to generate summary of paths reports with least positive or worst slack in each partition, and commands to report timing for two nodes in the partitions that meet timing. |
1.3. Module 1: Analyze the Non-Partitioned Design
Process Description
Use of the Fast Preserve option requires that you partition your design, similar to the setup for partial reconfiguration. You first analyze the non-partitioned design to determine which blocks have satisfactory performance, and which blocks require further optimization. The Intel® Quartus® Prime Design Assistant helps you to identify areas for further optimization.
After partitioning the design, you preserve the partitions and enable Fast Preserve to focus compilation time on the non-optimized partitions.
Tutorial Files
The tutorial_flat directory contains the files for this tutorial module.
Tutorial Steps
This tutorial module includes the following steps:
1.3.1. Step 1: Compile the Flat Design
- In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and open the /tutorial_flat/top.qpf project file.
-
To compile the flat design, click Compile Design on the Compilation Dashboard. The flat
compilation can require 40 minutes or more, depending on your system.
Figure 3. Compilation Dashboard
-
To view the compile time in the Compilation Report, click the
Flow Elapsed Time report. Fast Preserve can reduce this compilation time
significantly.
Figure 4. Flow Elapsed Time Report
1.3.2. Step 2: Identify Timing-Critical Design Blocks
- To open the Timing Analyzer, click Tools > Timing Analyzer .
-
In the Timing Analyzer, on the
Tasks pane, double-click Update Timing
Netlist to load the final timing netlist generated during the
compilation.
Figure 5. Timing Analyzer Tasks Pane
-
To run the report_timing.tcl script to identify any failing paths in the
timing-critical design blocks, type the following command in the Console window.
If not already visible, click View > Console in the Timing Analyzer to
display the Console. The script runs commands to identify any failing
paths.
source report_timing.tcl
The tcl script runs the report_timing command, capturing timing for the top 100 paths with the worst slack. The script is also preconfigured to capture timing between specific nodes for some of the design blocks. You analyze timing for these nodes later in this tutorial.
Figure 6. Timing Analyzer Report FoldersTable 2. Timing Analysis Reports that report_timing.tcl Generates Timing Analysis Folder Generated For Timing Reports Show inst_big u_big_partition1_top Analysis of top 100 paths with worst slack inst_i1 u_blinking_led_i1 inst_i2 u_blinking_led_i2 inst_i3 u_blinking_led_i3 inst_i4 u_blinking_led_i4 inst_big_path1 u_big_partition1_top Analysis of timing between specific nodes inst_i1_path1 u_blinking_led_i1 inst_i2_path1 u_blinking_led_i2 - In the inst_big folder, right-click the Slow 900 mV 100C Model report, and then click Generate in All Corners. Repeat this step for the inst_i1, inst_i2, inst_i3, and inst_i4 folders.
- View the Multi Corner Summary report that generates under each folder in the Report pane. Reports in red text in the inst_i3 and inst_i4 folders indicate timing-critical design blocks with failing paths.
-
Open the Multi Corner
Summary report in the inst_i3 folder. Check the values in the From Node and To
Node fields. Analysis indicates that the failing paths in
u_blinking_led_i3 are in the 64-bit
counter. This counter counts the number of cycles equivalent to 8s, where each
cycle is of 1.818 ns.
Figure 7. Multi Corner Summary for u_blinking_led_i3Note: Placement and routing results can vary by processor, OS, and software version.
-
Open the Multi Corner
Summary report in the inst_i4 folder. Check the values in the From Node and To
Node fields. Analysis indicates that the failing paths in
u_blinking_led_i4 are in the 64-bit
counter. This counter counts the number of cycles equivalent to 16s, where each
cycle is of 1.818 ns.
Figure 8. Multi Corner Summary for u_blinking_led_i4The timing analysis identifies u_blinking_led_i3 and u_blinking_led_i4 as timing-critical design blocks for optimization.
1.3.3. Step 3: View Design Assistant Results
Follow these steps to run Design Assistant:
-
To view Design Assistant settings, click Assignments > Settings > Design Assistant Rule Settings. Design Assistant settings show that Design Assistant is enabled
automatically during compilation, and that rule HRR-10101
Asynchronous Clears is enabled. HRR-10101 identifies
asynchronous clear signals that prevent retiming of paths that could increase
design performance.
Figure 9. Design Assistant Settings
-
Under the Synthesis
folder of the Compilation Report, expand the Design Assistant
(Elaborated) folder. Design Assistant reports that the design
contains asynchronous clears that limit retiming.
Figure 10. Design Assistant Report
Module 2: Preserve Timing-Closed Design Partitions describes how to preserve the design partitions that don't require further optimization, allowing you to focus the Compiler's effort on areas requiring further optimization.
1.4. Module 2: Preserve Timing-Closed Design Partitions
Process Description
Design partitioning the design allows you to preserve individual logic blocks in your design. After partitioning the design, you can preserve the partitions for blocks that meet timing, and focus optimization on the other design blocks.
In this tutorial module, you preserve and reuse the root partition, which is the partition that includes the device periphery.
Tutorial Files
The tutorial_base directory contains the files for this tutorial module.
Tutorial Steps
This tutorial module includes the following steps:
1.4.1. Step 1: Create Design Partitions
- In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and open the /tutorial_base/top.qpf project file.
- Click Processing > Start > Start Analysis & Elaboration.
- In the Project Navigator, expand the u_blinking_led_top instance in the Hierarchy tab.
- Right-click the u_blinking_led_i3 instance,
point to Design Partition, and select the Reserved
Core partition Type. A
design partition icon appears next to each instance you assign.Figure 12. Create Design Partitions
- Repeat step 4 to create a partition for the u_blinking_led_i4 instance. You will export the remaining instances as part of the root partition.
- If the Design Partitions Window is not already open, click
Assignments > Design Partitions Window. The Design Partitions Window lists the partitions you define,
along with the root partition (|) the Compiler automatically creates for each
project.Figure 13. Design Partitions Window2
1.4.2. Step 2: Floorplan the Design Partitions
-
In the Design Partitions Window, right-click the blinking_led_8s instance in the Project Navigator and click
Logic Lock Region > Create New Logic Lock Region.
Figure 14. Create Logic Lock Region
- To modify the region properties, click Assignments > Logic Lock Regions Window.
- In the Origin column, specify X165_Y113.
- Change the Width to 14, and the Height to 34.
- Enable the Reserved and Core-Only options.
- Click the Routing Region cell. The Logic Lock Routing Region Settings dialog box appears.
- Specify Fixed with expansion with Expansion Length of 1 for the Routing Type. The actual size and location are arbitrary for this tutorial. However, you can view and adjust the Logic Lock Region shape in the Chip Planner.
-
Repeat steps 1 through 7 to define the following Logic Lock region for the
blinking_led_16s instance:
Figure 15. Logic Lock Regions
- Origin—X165_Y149
- Width—14
- Height—34
- Reserved—On
- Core Only—On
- Expansion Length—Fixed with expansion 1
This floorplanning ensures that the ref_clock_in meets timing because the placement location is not too far from output pins.
Figure 16. Logic Lock Region Placement
1.4.3. Step 3: Preserve the Timing-Closed Root Partition
- Click Assignments > Design Partitions Window.
-
For the root_partition row, specify
root_partition.qdb as the Post Final Export
File.
Figure 17. Post Final Export File
- To compile the design and export the partition, click Compile Design on the Compilation Dashboard.
1.5. Module 3: Optimize with Fast Preservation
Process Description
You can create a separate revision of your project that reuses the preserved root partition during optimization of the other partitions. When you enable the Fast Preserve option, the Compiler reduces the logic of the imported partition to only the interface logic between the partition boundary and the rest of the design, thereby reducing the compilation time the partition requires.
In this tutorial module, you reuse the root partition, which is the partition that includes the device periphery.
Tutorial Files
The tutorial_impl directory contains the files for this tutorial module.
Tutorial Steps
This tutorial module includes the following steps:
1.5.1. Step 1: Create a Project Revision
-
From the tutorial_base
directory, copy the following files into the tutorial_impl directory:
- top.qsf—to include the partition and Logic Lock settings in the new revision of the project.
- root_partition.qdb—to apply the final snapshot .qdb as the root partition of the new revision.
-
In top.qsf, remove the following
line:
set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL \ root_partition.qdb -to | -entity top - Save top.qsf.
1.5.2. Step 2: Enable Fast Preservation
- Click Assignments > Settings > Compiler Settings > Incremental Compile.
-
Turn on the Fast Preserve option.
Figure 18. Fast Preserve Option
- Click OK.
set_global_assignment -name FAST_PRESERVE AUTO
1.5.3. Step 3: Import the Root Partition
- If the Design Partitions Window is not already open, click Assignments > Design Partitions Window. The Design Partitions Window lists the blinking_led_8s and blinking_led_16s partitions that you create in Step 1: Create Design Partitions.
-
In the root_partition row, select
root_partition.qdb as the Partition Database
File. root_partition.qdb is now the source
for the root partition of this project.
Figure 19. Import the Root Partition
1.5.4. Step 4: Optimize the Reserved Core Partitions
-
Update the RTL for blinking_led_8s and blinking_led_16s to correct the timing violations and asynchronous
reset.
Note: To accelerate this step, you can simply copy the blinking_led_8s.sv and blinking_led_16s.sv from the golden_rtl directory, and paste the files into the tutorial_impl directory, overwriting the existing files.
-
Click Compile Design on
the Compilation Dashboard. The Compilation Dashboard displays the time spent in
each module of the Compiler and the total compilation time.
Figure 20. Fast Preserve Compilation Flow Time
1.5.5. Step 5: View Fast Preservation Results
-
To view the compile time in the Compilation Report, click the
Flow Elapsed Time report. The report
shows time savings in each module of the Compiler.
Figure 21. Compile Time Comparison
-
Under the Synthesis
folder, view the Design Assistant
(Elaborated) report. All Asynchronous Clear rule violations are
resolved.
Figure 22. Design Assistant Results
- To view the Timing Analyzer results, click Tools > Timing Analyzer.
- On the Tasks pane, double-click Update Timing Netlist.
- Under Reports, open the Slack folder.
-
Double-click Report Setup
Summary. The design meets all setup timing requirements.
Figure 23. Timing Analysis Results
1.6. AN 899: Reducing Compile Time with Fast Preservation Revision History
| Document Version | Intel® Quartus® Prime Version | Changes |
|---|---|---|
| 2019.11.06 | 19.3.0 |
|