Quartus® Prime, click Processing > Start Compilation to compile the reference design.
The following steps are to setup the
Arria® 10 FPGA development kit
before running the reference design.
Arria® 10 FPGA development board switches to according
to the following figure.
Arria® 10 FPGA Development Board Switch
Connect the loopback FPGA mezzanine (FMC) daughter card on the FMC loopback
Figure 7. Connection for Loopback FPGA Mezzanine (FMC) Daughter Card
Intel® FPGA Download Cable to the
FPGA development kit and your host machine.
Click Tools -> Programmer to
program the <project directory>
/master_image/top.sof file into the Arria 10 FPGA development
Generating Executable and Linking Format (.elf) Programming File
Follow the steps below to generate an executable and linking format (.elf) programming file. These steps are necessary if
you would like to modify the phylite_dynamic_reconfiguration.c, phylite_dynamic_reconfiguration.h and hello_world.c files.
Quartus® Prime software
version 16.0 select Tools > Nios II Software Build Tools for
Figure 8. Nios II Software Build Tools for Eclipse
Create a new workspace when the Select a workspace window prompt appears.
Figure 9. Create New Workspace
Select File > New > Nios II Application and BSP from
Template in the Nios II - Eclipse window.
Figure 10. Nios II Application and BSP from Template
In the SOPC Information File
name parameter, browse to the location of phylite_nios.sopcinfo file in your host machine.
Click OK to select the file and Eclipse automatically
loads all CPU settings.
The phylite_nios.sopcinfo is created when generating
In the Project name parameter, specify
your desired project name.
Choose Hello World as the project template.
Click Finish to generate the project.
Quartus® Prime software creates a new directory named
software in the specified project
Figure 11. Nios II Application and BSP from Template
Replace the following files from <project directory>/software reference design with the
files located in your new software directory.
In the Nios II - Eclipse window, press F5 to refresh the window and reload the
new files into the project.
Click Project > Build Project.
Make sure the <project_name>.elf file is generated in the new <project
Running the Hardware Reference Design
These steps are guidelines to run the dynamic calibration and begin the data transfer
for the reference design.
Remove all other connected device in the programming
device list during JTAG connection setup in Linux operating system.
Open two Nios II Command Shell prompts on your host machine:
In Windows operating system, go to Start > Programs > Altera > Nios II EDS and click on Nios II Command Shell (command prompt
In Linux operating system, go to <Quartus software
installation directory>\linux64\nios2ed directory and run
nios2_command_shell.sh to launch command prompt
Repeat the above step to launch second command prompt (command prompt
Command prompt A is to display the dynamic calibration result.
Command prompt B is used to run Nios II commands.
In the command prompt A , use the following command to run the
Nios II terminal application for result printouts.
In command prompt B, go to the project top directory.
Run the issp.tcl script once to reset
the system and clean up the instruction memory in the Nios II soft
quartus_stp -t issp.tcl top.qpf 1
In command prompt B, download the executable (<project_name>.elf) file into the FPGA and
start the dynamic calibration process with the following command:
This module takes the input from Si570 Programmable Oscillator and provides
reference clock to
internal PLL modules in each of the Intel FPGA PHYLite for Parallel
Interfaces IP cores.
FPGA PHYLite for Parallel Interfaces IP core transfers data from
ATSO_DYN_CFG_CTRL or traffic generator module to dut_INPUT module. During configuration and
calibration mode, this module takes data from ATSO_DYN_CFG_CTRL module and send to dut_INPUT
module. In normal operating mode, this module takes data from traffic generator and sends to
FPGA PHYLite for Parallel Interfaces IP core receives data from dut_OUTPUT
module. This module sends the received data to ATSO_DYN_CFG_CTRL module during configuration
and calibration mode, and to traffic generator during normal operating mode for data
The Avalon controller is responsible to perform address translation to retrieve the
physical address of the strobe and data pins and sends reconfiguration commands to
ATSO_DYN_CFG_CTRL with Nios II Processor Module
This module consist of Nios II processor and five parallel I/O modules. This is a
centralized controller to perform and manage dut_OUTPUT configuration. It also issues
control signals to the Avalon controller and verify data from dut_INPUT during calibration
Table 1. Parallel I/O Modules - Function and Address Map
Parallel I/O Module
Sends calibration test data to dut_OUTPUT module.
Asserts rdata_en signal during calibration mode.
Receives data from dut_INPUT module for comparison against test data.
Receives rdata_valid signal from dut_INPUT module.
Asserts cfg_done signal to exit calibration mode and
activates traffic generator module for data transfer for normal operating
Traffic Generator Module
Traffic Generator module is responsible for transmitting data to dut_OUTPUT and receiving
data from dut_INPUT during normal operating mode. The module uses Linear Feedback Shift
Register (LFSR) to generate random data for transmission. Traffic generator performs data
comparison to the received data to ensure the strobe enable delay setting is configured
The data word alignment algorithm starts by Nios II processor setting the
strobe enable delay and read valid enable delay of the dut_INPUT to the minimum read latency
based on the FPGA core clock rate and the VCO frequency multiplier factor.
Next, Nios II processor asserts oe_from_core signal to initiate data transmission to dut_OUTPUT and sends a set of
test data to the dut_OUTPUT.
The dut_OUTPUT transmit the test data to the dut_INPUT. The rcfg_data_from_core signals show the data value transmitted from
Next, the dut_INPUT sends the test data to Nios II processor for data
verification. Nios II asserts recfg_rdata_en signal to
dut_INPUT to capture the data transmitted from dut_OUTPUT. The dut_INPUT module asserts
recfg_rdata_valid signal to indicates the received data in
the dut_INPUT read FIFO is valid. If the received test data does not match the expected data,
Nios II processor increases the strobe enable delay and read valid enable delay of the
dut_INPUT module, and repeats the process of sending test data to dut_OUTPUT and verify the
received data from dut_INPUT.
Figure 16. Signal Tap Waveform for Mismatch Data during Dynamic
The algorithm stops when the received data matches the transmitted data or if
the strobe enable delay and read valid enable delay reach the maximum values. Nios II asserts
cfg_done signal to indicate reconfiguration completed and
allow traffic generator to start sending data.
Figure 17. Signal Tap Waveform for Match Data during Dynamic
Figure 18. Signal Tap Waveform for Reconfiguration Complete
The reference design uses the following timing analysis flow to obtain the accurate value for
Input Strobe Setup Delay, Input Strobe Hold Delay
Constraint, Output Strobe Setup Delay Constraint,, and
Output Strobe Hold Delay Constraint to perform timing closure for
both output and input interfaces.
Figure 19. Timing Analysis Flow
It is crucial to set the Input Strobe Setup Delay, Input
Strobe Hold Delay Constraint, Output Strobe Setup Delay
Constraint, and Output Strobe Hold Delay Constraint for
both dut_INPUT and dut_OUTPUT module to 0 initially to eliminate unnecessary interface
constraints. The phylite_interface_constraints.tcl script then
automatically calculates the TcoMax and TcoMin values for input interface delay constraints
and Tsu and Th values for output interface delay constraints.
The TimeQuest Analyzer generates a report based on the calculations performed by the
Figure 20. PHYLite Interface Constraints Report
Input Interface Delay Constraints
Use the TcoMax value to calculate the Input
Strobe Setup Delay Constraint and TcoMin value to calculate the Input Strobe Hold Delay Constraint. The input interface delay
constraints must include board skew to perform accurate timing analysis.
Use the Tsu value to calcuate the Output Strobe
Setup Delay Constraint and Th value to calculate Output Strobe Hold Delay Constraint. The output interface delay constraints
must include board skew to perform accurate timing analysis.