Stratix 10 TX Advance Information Brief
Stratix 10 TX Advance Information Brief
In addition to the 56 Gbps PAM4 / 30 Gbps NRZ dual-mode transceivers, Intel® Stratix® 10 TX devices feature several other breakthrough innovations. These include all new HyperFlex® core architecture, hardened floating point DSP blocks, hardened external memory controllers and advanced packaging technology based on Intel® 's Embedded Multi-die Interconnect Bridge (EMIB).
With an embedded quad-core 64-bit ARM® Cortex®-A53 hard processor system (HPS) available in select devices, Intel® Stratix® 10 TX FPGAs deliver power efficient, application-class processing, and allow designers to extend hardware virtualization into the FPGA fabric.
Intel® Stratix® 10 TX FPGAs integrate a monolithic 14-nm FPGA fabric die with multiple high-speed transceiver tiles, all inside a single flip-chip BGA package. This implementation, combined with the unmatched transceiver bandwidth and core fabric performance, demonstrates Intel® 's commitment to deliver high-performance programmable solutions to your most challenging system design problems.
Important innovations in Intel® Stratix® 10 TX devices include:
- All new HyperFlex core architecture delivering 2X the core performance compared to previous generation high-performance FPGAs
- Industry leading Intel 14-nm Tri-Gate (FinFET) technology
- Heterogeneous 3D System-in-Package (SiP) technology
- Monolithic core fabric with up to 2.8 million logic elements (LEs)
- Up to 144 full duplex transceiver channels on heterogeneous 3D SiP transceiver tiles
- Transceiver data rates up to 56 Gbps PAM4 and 30 Gbps NRZ for chip-to-chip, chip-to-module, and backplane applications
- Embedded eSRAM (45 Mbit) in select devices, and M20K (20 kbit) internal SRAM memory blocks
- Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops (PLLs)
- Hard PCI Express® Gen3 x16 intellectual property (IP) blocks
- Hard 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514)
- Hard memory controllers and PHY supporting DDR4 rates up to 2666 Mbps per pin
- Hard fixed-point and IEEE 754 compliant hard floating-point variable precision digital signal processing (DSP) blocks with over 9 TFLOPS compute performance with a power efficiency of 80 GFLOPS per Watt
- Quad-core 64-bit ARM Cortex-A53 embedded processor in select devices, running up to 1.5 GHz
- Programmable clock tree synthesis for flexible, low power, low skew clock trees
- Dedicated secure device manager (SDM) for:
- Enhanced device configuration and security
- AES-256, SHA-256/384 and ECDSA-256/384 encrypt/decrypt accelerators and authentication
- Multi-factor authentication
- Physically Unclonable Function (PUF) service and software programmable device configuration capability
- Advanced power saving features delivering up to 70% lower core power compared to previous generation high-performance FPGAs
With these capabilities, Stratix® 10 TX devices are ideally suited for the highest transceiver bandwidth applications in diverse markets such as:
- Compute and Storage—for custom servers, cloud computing and data center acceleration
- Networking—for Terabit, 400G and multi-100G bridging, aggregation, packet processing and traffic management
- Optical Transport Networks—for OTU4, 2xOTU4, 4xOTU4
- Broadcast—for high-end studio distribution, headend encoding/decoding, edge QAM
- Military—for radar, electronic warfare, and secure communications
- Medical—for diagnostic scanners and diagnostic imaging
- Test and Measurement—for protocol analyzers and application testers
- Wireless—for next-generation 5G networks
Stratix 10 TX Devices
In addition to delivering over 8 Tbps of transceiver bandwidth in a single package, Stratix® 10 TX devices offer up to 1 GHz core fabric performance and contain up to 2.8 million LEs in a monolithic fabric. They also feature up to 144 general purpose transceivers on separate transceiver tiles, and 2666 Mbps DDR4 external memory interface performance. The dual mode transceivers are capable of data rates up to 56 Gbps PAM4 / 30 Gbps NRZ for both short reach and backplane driving applications. Select devices contain an embedded hard processor system (HPS) based on an application-class quad-core 64-bit ARM® Cortex®-A53, running at clock rates up to 1.5 GHz.
These devices are optimized for FPGA applications that require the highest transceiver bandwidth, and the highest core fabric performance, with the power efficiency of Intel’s industry-leading 14-nm Tri-Gate process technology.
The high-performance monolithic FPGA fabric is based on the new HyperFlex core architecture that includes additional Hyper-Registers everywhere throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module (ALM) and a rich set of high performance building blocks including:
- eSRAM (45 Mbit) embedded memory blocks (available in select devices)
- M20K (20 kbit) embedded memory blocks
- Variable precision DSP blocks with IEEE 754 compliant hard floating-point
- Fractional synthesis and integer PLLs
- Hard memory controllers and PHY for external memory interfaces
- General purpose IO cells
To clock these building blocks, Stratix® 10 TX devices use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while it is operating. The high speed serial transceivers contain both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols. In addition to the hard PCS, Stratix® 10 TX devices contain hard PCI Express® IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane configurations, and 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514). The hard PCS, PCI Express IP and 10/25/100 Gbps Ethernet MAC and FEC IP free up valuable core logic resources, save power, and increase your productivity.
Innovations in Stratix 10 TX Devices
Stratix® 10 TX devices deliver many significant improvements over the previous generation high-performance Stratix V FPGAs.
| Feature | Stratix V FPGAs | Stratix® 10 TX Devices |
|---|---|---|
| Core fabric process technology | 28-nm TSMC (planar transistor) | 14 nm Intel Tri-Gate (FinFET) |
| Hard processor core | None | Quad-core 64-bit ARM Cortex-A53 (select devices) |
| Core architecture | Conventional core architecture with conventional interconnect | HyperFlex core architecture with Hyper-Registers in the interconnect |
| Core performance | 500 MHz | 1 GHz |
| Power dissipation | 1x | As low as 0.3x |
| Logic density | 952 KLE (monolithic) | 2,800 KLE (monolithic) |
| Embedded memory (eSRAM) | None | 90 Mbits (select devices) |
| Embedded memory (M20K) | 52 Mbits | 229 Mbits |
| 18x19 multipliers | 3,926
Note: Multiplier is 18x18
in Stratix V devices.
|
11,520
Note: Multiplier is 18x19 in
Stratix® 10 TX
devices.
|
| Floating point DSP capability | Up to 1 TFLOP, requires soft floating point adder and multiplier | Over 9 TFLOPS, hard IEEE 754 compliant single precision floating point adder and multiplier |
| Maximum transceivers | 66 | 144 |
| Maximum transceiver data rate (chip-to-chip) | 28.05 Gbps |
Dual mode 56 Gbps PAM4 / 30 Gbps NRZ |
| Maximum transceiver data rate (backplane) | 12.5 Gbps | Dual mode 56 Gbps PAM4 / 30 Gbps NRZ up to 30 dB insertion loss |
| Hard memory controller | None |
DDR4 @ 1333 MHz/2666 Mbps DDR3 @ 1067 MHz/2133 Mbps |
| Hard protocol IP | PCIe Gen3 x8 |
PCIe Gen3 x16 with SR-IOV 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) |
| Core clocking and PLLs | Global, quadrant and regional clocks supported by fractional-synthesis fPLLs | Programmable clock tree synthesis supported by fractional synthesis fPLLs and integer IO PLLs |
| Register state readback and writeback | Not available | Non-destructive register state readback and writeback for ASIC prototyping and other applications |
These innovations result in the following improvements:
- Improved Core Logic Performance: The HyperFlex core architecture combined with Intel’s 14-nm Tri-Gate technology allows Stratix® 10 TX devices to achieve 2X the core performance compared to the previous generation
- Lower Power: Stratix® 10 TX devices use up to 70% lower core power compared to the previous generation, enabled by 14-nm Intel Tri-Gate technology, the HyperFlex core architecture, and optional power savings features built into the architecture
- Higher Density: Stratix® 10 TX devices offer over two times the level of integration, with up to 2,800K logic elements (LEs) in a monolithic fabric, 90 Mbits of embedded eSRAM blocks in select devices, over 229 Mbits of embedded M20K memory blocks, and 11,520 18x19 multipliers
- Embedded Processing: Select Stratix® 10 TX devices feature a Quad-Core 64-bit ARM Cortex-A53 processor optimized for power efficiency and software compatible with previous generation Intel® SoCs
- Improved Transceiver Performance: With up to 144 transceiver channels implemented in heterogeneous 3D SiP transceiver tiles, Stratix® 10 TX devices support data rates up to 56 Gbps PAM4 and 30 Gbps NRZ for chip-to-chip and backplane driving with signal conditioning circuits capable of equalizing over 30 dB of system loss
- Improved DSP Performance: The variable precision DSP block in Stratix® 10 TX devices features hard fixed and floating point capability, with over 9 TeraFLOPS IEEE754 single-precision floating point performance
- Additional Hard IP: Stratix® 10 TX devices include many more hard IP blocks than previous generation devices, with a hard memory controller included in each bank of 48 general purpose IOs, hard PCS, PCIe Gen3x16 full protocol stack and 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) to support the transceivers
- Enhanced Core Clocking: Stratix® 10 TX devices feature programmable clock tree synthesis; clock trees are only synthesized where needed, increasing the flexibility and reducing the power dissipation of the clocking solution
- Additional Core PLLs: The core fabric in Stratix® 10 TX devices is supported by both integer IO PLLs and fractional synthesis fPLLs, resulting in a greater total number of PLLs than the previous generation
Stratix 10 TX Features Summary
|
Feature |
Description |
|---|---|
|
Core process technology |
|
|
Low power serial transceivers |
|
|
General purpose I/Os |
|
|
Embedded hard IP |
|
|
Transceiver hard IP |
|
|
Power management |
|
|
High performance monolithic core fabric |
|
|
Internal memory blocks |
|
|
Variable precision DSP blocks |
|
|
Phase locked loops (PLL) |
|
|
Core clock networks |
|
|
Configuration |
|
|
Packaging |
|
|
Software and tools |
|
| SoC Subsystem | Feature | Description |
|---|---|---|
| Hard Processor System | Multi-processor unit (MPU) core |
|
| System Controllers |
|
|
| Layer 1 Cache |
|
|
| Layer 2 Cache |
|
|
| On-Chip Memory |
|
|
| Direct memory access (DMA) controller |
|
|
| Ethernet media access controller (EMAC) |
|
|
| USB On-The-Go controller (OTG) |
|
|
| UART controller |
|
|
| Serial Peripheral Interface (SPI) controller |
|
|
| I2C controller |
|
|
| SD/SDIO/MMC controller |
|
|
| NAND flash controller |
|
|
| General-purpose I/O (GPIO) |
|
|
| Timers |
|
|
| Security |
|
|
| External Memory Interface | External Memory Interface |
|
Stratix 10 TX Block Diagram
Stratix 10 TX Family Plan
|
Stratix® 10 TX Device Name |
Logic Elements (KLE) |
eSRAM Blocks | eSRAM Mbits |
M20K Blocks |
M20K Mbits |
MLAB Counts |
MLAB Mbits |
18x19 Multi- pliers 1 |
HPS |
|---|---|---|---|---|---|---|---|---|---|
| TX 1650 | 1624 | 2 | 90 | 5,851 | 114 | 13,764 | 8 | 6,290 | - |
| TX 2100 | 2005 | 2 | 90 | 6,501 | 127 | 17,316 | 11 | 7,488 | - |
| TX 2500 | 2422 | 0 | 0 | 9,963 | 195 | 20,529 | 13 | 10,022 | Yes |
| TX 2800 | 2753 | 0 | 0 | 11,721 | 229 | 23,796 | 15 | 11,520 | Yes |
| Stratix 10 TX Device Name | Package | Interconnects | PLLs | Hard IP | ||||
|---|---|---|---|---|---|---|---|---|
| GPIOs | XCVR | fPLLs | I/O PLLs | PCIe Hard IP Blocks | 50/100 GbE MACs | 10/25/100 GbE MACs | ||
| TX 1650 | SF48 (F2112) | 544 | 72 | 24 | 14 | 2 | 2 | 4 |
| TX 1650 | UF50 (F2397) | 440 | 96 | 32 | 14 | 1 | 1 | 12 |
| TX 2100 | SF48 (F2112) | 544 | 72 | 24 | 14 | 2 | 2 | 4 |
| TX 2100 | UF50 (F2397) | 440 | 96 | 32 | 14 | 1 | 1 | 12 |
| TX 2500 | SF48 (F2112) | 544 | 72 | 24 | 24 | 2 | 2 | 4 |
| TX 2500 | UF50 (F2397) | 440 | 96 | 32 | 24 | 1 | 1 | 12 |
| TX 2500 | YF55 (F2912) | 296 | 144 | 48 | 24 | 1 | 1 | 20 |
| TX 2800 | SF48 (F2112) | 544 | 72 | 24 | 24 | 2 | 2 | 4 |
| TX 2800 | UF50 (F2397) | 440 | 96 | 32 | 24 | 1 | 1 | 12 |
| TX 2800 | YF55 (F2912) | 296 | 144 | 48 | 24 | 1 | 1 | 20 |
| Stratix 10 TX Device Name |
F2112 SF48 (47.5x47.5mm2) |
F2397 UF50 (50x50 mm2) |
F2912 YF55 (55x55 mm2) |
|---|---|---|---|
| TX 1650 | 544, 16, 264, 24, 48 | 440, 8, 216, 72, 24 | N/A |
| TX 2100 | 544, 16, 264, 24, 48 | 440, 8, 216, 72, 24 | N/A |
| TX 2500 | 544, 16, 264, 24, 48 | 440, 8, 216, 72, 24 | 296, 8, 144, 120, 24 |
| TX 2800 | 544, 16, 264, 24, 48 | 440, 8, 216, 72, 24 | 296, 8, 144, 120, 24 |
HyperFlex Core Architecture
Stratix® 10 TX devices are based on a monolithic core fabric featuring the new HyperFlex core architecture. The HyperFlex core architecture delivers 2X the clock frequency performance and up to 70% lower power compared to previous generation high-end FPGAs. Along with this performance breakthrough, the HyperFlex core architecture delivers a number of advantages including:
- Higher Throughput—Leverages 2X core clock frequency performance to obtain throughput breakthroughs
- Improved Power Efficiency—Uses reduced IP size, enabled by HyperFlex, to consolidate designs which previously spanned multiple devices into a single device, thereby reducing power by up to 70% versus previous generation devices
- Greater Design Functionality—Uses faster clock frequency to reduce bus widths and reduce IP size, freeing up additional FPGA resources to add greater functionality
- Increased Designer Productivity—Boosts performance with less routing congestion and fewer design iterations using Hyper-Aware design tools, obtaining greater timing margin for more rapid timing closure
In addition to the traditional user registers found in the Adaptive Logic Modules (ALM), the HyperFlex core architecture introduces additional bypassable registers everywhere throughout the fabric of the FPGA. These additional registers, called Hyper-Registers are available on every interconnect routing segment and at the inputs of all functional blocks.
The Hyper-Registers enable the following key design techniques to achieve the 2X core performance increases:
- Fine grain Hyper-Retiming to eliminate critical paths
- Zero latency Hyper-Pipelining to eliminate routing delays
- Flexible Hyper-Optimization for best-in-class performance
By implementing these techniques in your design, the Hyper-Aware design tools automatically make use of the Hyper-Registers to achieve maximum core clock frequency.
Heterogeneous 3D SiP Transceiver Tiles
Stratix® 10 TX devices feature power efficient, high bandwidth, low latency transceivers. The transceivers are implemented on heterogeneous 3D System-in-Package (SiP) transceiver tiles, each containing 24 full-duplex transceiver channels. In addition to providing a high-performance transceiver solution to meet current connectivity needs, this allows for future flexibility and scalability as data rates, modulation schemes, and protocol IPs evolve.
Each transceiver tile contains:
- 24 full-duplex transceiver channels (PMA and PCS)
- Reference clock distribution network
- Transmit PLLs
- High-speed clocking and bonding networks
- PCI Express and 100G Ethernet MAC hard IP, or 100G Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514)
Stratix 10 TX Transceivers
Stratix® 10 TX devices offer up to 144 total full-duplex transceiver channels. These channels provide continuous data rates from 1 Gbps to 30 Gbps in NRZ mode and 2 Gbps to 56 Gbps in PAM4 mode for chip-to-chip, chip-to-module, and backplane applications. For longer-reach backplane driving applications, advanced adaptive equalization circuits are used to equalize over 30 dB of system loss.
All transceiver channels feature a dedicated Physical Medium Attachment (PMA) and a hardened Physical Coding Sublayer (PCS).
- The PMA provides primary interfacing capabilities to physical channels.
- The PCS typically handles encoding/decoding, word alignment, and other pre-processing functions before transferring data to the FPGA core fabric.
Within each transceiver tile, the transceivers are arranged in four banks of six PMA-PCS groups. A wide variety of bonded and non-bonded data rate configurations are possible within each bank, and within each tile, using a highly configurable clock distribution network.
PMA Features
The transmit features deliver exceptional signal integrity at data rates up to 56 Gbps PAM4 / 30 Gbps NRZ. Clocking options include ultra-low jitter LC tank-based (ATX) PLLs with optional fractional synthesis capability, channel PLLs operating as clock multiplier units (CMUs), and fractional synthesis PLLs (fPLLs).
- ATX PLL—can be configured in integer mode, or optionally, in a new fractional synthesis mode. Each ATX PLL spans the full frequency range of the supported data rate range providing a stable, flexible clock source with the lowest jitter.
- CMU PLL—when not being used as a transceiver, select PMA channels can be configured as channel PLLs operating as CMUs to provide an additional master clock source within the transceiver bank.
- fPLL—In addition, dedicated fPLLs are available with precision frequency synthesis capabilities. fPLLs can be used to synthesize multiple clock frequencies from a single reference clock source and replace multiple reference oscillators for multi-protocol and multi-rate applications.
On the receiver side, each PMA has an independent channel PLL that allows analog tracking for clock-data recovery. Each PMA also has advanced equalization circuits that compensate for transmission losses across a wide frequency spectrum.
- Variable Gain Amplifier (VGA)—to optimize the receiver's dynamic range
- Continuous Time Linear Equalizer (CTLE)—to compensate for channel losses with lowest power dissipation
- Decision Feedback Equalizer (DFE)—to provide additional equalization capability on backplanes even in the presence of crosstalk and reflections
- On-Die Instrumentation (ODI)—to provide on-chip eye monitoring capabilities (Eye Viewer). This capability helps to optimize link equalization parameters during board bring-up and supports in-system link diagnostics and equalization margin testing
All link equalization parameters feature automatic adaptation using the new Advanced Digital Adaptive Parametric Tuning (ADAPT) circuit. This circuit is used to dynamically set DFE tap weights, adjust CTLE parameters, and optimize VGA gain and threshold voltage. Finally, optimal and consistent signal integrity is ensured by using the new hardened Precision Signal Integrity Calibration Engine (PreSICE) to automatically calibrate all transceiver circuit blocks on power-up. This gives the most link margin and ensures robust, reliable, and error-free operation.
|
Feature |
Capability |
|---|---|
|
Chip-to-Chip Data Rates |
|
|
Backplane Support |
Drive backplanes at data rates up to 56 Gbps PAM4 / 30 Gbps NRZ, including 10GBASE-KR, KP4, CR4, CR2, CEI 56G-LR compliance |
|
Optical Module Support |
SFP+/SFP, XFP, CXP, QSFP/QSFP28, QSFPDD, CFP/CFP2/CFP4 |
|
Cable Driving Support |
SFP+ Direct Attach, PCI Express over cable, eSATA |
|
Transmit Pre-Emphasis |
5-tap transmit pre-emphasis and de-emphasis to compensate for system channel loss |
|
Continuous Time Linear Equalizer (CTLE) |
Equalization to compensate for system channel loss |
|
Decision Feedback Equalizer (DFE) |
DFE to equalize backplane channel loss in the presence of crosstalk and noisy environments |
|
Advanced Digital Adaptive Parametric Tuning (ADAPT) |
Fully digital adaptation engine to automatically adjust all link equalization parameters—including CTLE, DFE, and VGA blocks—that provide optimal link margin without intervention from user logic |
|
Precision Signal Integrity Calibration Engine (PreSICE) |
Hardened calibration controller to quickly calibrate all transceiver control parameters on power-up, which provides the optimal signal integrity and jitter performance |
|
ATX Transmit PLLs |
Low jitter ATX (inductor-capacitor) transmit PLLs with continuous tuning range to cover a wide range of standard and proprietary protocols, with optional fractional frequency synthesis capability |
|
Fractional PLLs |
On-chip fractional frequency synthesizers to replace on-board crystal oscillators and reduce system cost |
|
Digitally Assisted Analog CDR |
Superior jitter tolerance with fast lock time |
|
On-Die Instrumentation— Eye Viewer and Jitter Margin Tool |
Simplify board bring-up, debug, and diagnostics with non-intrusive, high-resolution eye monitoring (Eye Viewer). Also inject jitter from transmitter to test link margin in system. |
|
Dynamic Reconfiguration |
Allows for independent control of each transceiver channel Avalon memory-mapped interface for the most transceiver flexibility. |
|
Multiple PCS-PMA and PCS-Core to FPGA fabric interface widths |
8-, 10-, 16-, 20-, 32-, 40-, or 64-bit interface widths for flexibility of deserialization width, encoding, and reduced latency |
PCS Features
Stratix® 10 TX PMA channels interface with core logic through configurable and bypassable PCS interface layers.
The PCS contains multiple gearbox implementations to decouple the PMA and PCS interface widths. This feature provides the flexibility to implement a wide range of applications with 8, 10, 16, 20, 32, 40, or 64-bit interface width between each transceiver and the core logic.
The PCS also contains hard IP to support a variety of standard and proprietary protocols across a wide range of data rates and encoding schemes. The Standard PCS mode provides support for 8B/10B encoded applications up to 12.5 Gbps. The Enhanced PCS mode supports 64B/66B and 64B/67B encoded applications up to 17.4 Gbps. The enhanced PCS mode also includes an integrated 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) circuit. For highly customized implementations, a PCS Direct mode provides an interface up to 64 bits wide to allow for custom encoding and support for data rates up to 30 Gbps.
For more information about the PCS-Core interface or the double rate transfer mode, refer to the Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide, and the Intel Stratix 10 E-Tile Transceiver PHY User Guide.
|
PCS Protocol Support |
Data Rate (Gbps) |
Transmitter Data Path |
Receiver Data Path |
|---|---|---|---|
|
Standard PCS |
0.125 to 12.5 |
Phase compensation FIFO, byte serializer, 8B/10B encoder, bit-slipper, channel bonding |
Rate match FIFO, word-aligner, 8B/10B decoder, byte deserializer, byte ordering |
|
PCI Express Gen1/Gen2 x1, x2, x4, x8, x16 |
2.5 and 5.0 |
Same as Standard PCS plus PIPE 2.0 interface to core |
Same as Standard PCS plus PIPE 2.0 interface to core |
|
PCI Express Gen3 x1, x2, x4, x8, x16 |
8.0 |
Phase compensation FIFO, byte serializer, encoder, scrambler, bit-slipper, gear box, channel bonding, and PIPE 3.0 interface to core, auto speed negotiation |
Rate match FIFO (0-600 ppm mode), word-aligner, decoder, descrambler, phase compensation FIFO, block sync, byte deserializer, byte ordering, PIPE 3.0 interface to core, auto speed negotiation |
|
CPRI |
0.6144 to 9.8 |
Same as Standard PCS plus deterministic latency serialization |
Same as Standard PCS plus deterministic latency deserialization |
|
Enhanced PCS |
2.5 to 17.4 |
FIFO, channel bonding, bit-slipper, and gear box |
FIFO, block sync, bit-slipper, and gear box |
|
10GBASE-R |
10.3125 |
FIFO, 64B/66B encoder, scrambler, FEC, and gear box |
FIFO, 64B/66B decoder, descrambler, block sync, FEC, and gear box |
|
Interlaken |
4.9 to 17.4 |
FIFO, channel bonding, frame generator, CRC-32 generator, scrambler, disparity generator, bit-slipper, and gear box |
FIFO, CRC-32 checker, frame sync, descrambler, disparity checker, block sync, and gear box |
|
SFI-S/SFI-5.2 |
11.3 |
FIFO, channel bonding, bit-slipper, and gear box |
FIFO, bit-slipper, and gear box |
|
IEEE 1588 |
1.25 to 10.3125 |
FIFO (fixed latency), 64B/66B encoder, scrambler, and gear box |
FIFO (fixed latency), 64B/66B decoder, descrambler, block sync, and gear box |
|
SDI |
up to 12.5 |
FIFO and gear box |
FIFO, bit-slipper, and gear box |
|
GigE |
1.25 |
Same as Standard PCS plus GigE state machine |
Same as Standard PCS plus GigE state machine |
| PCS Direct | up to 30 | Custom | Custom |
PCI Express Gen1/Gen2/Gen3 Hard IP
Stratix® 10 TX devices contain embedded PCI Express hard IP designed for performance, ease-of-use, increased functionality, and designer productivity.
The PCI Express hard IP consists of the PHY, Data Link, and Transaction layers. It also supports PCI Express Gen1/Gen2/Gen3 end point and root port, in x1/x2/x4/x8/x16 lane configurations. The PCI Express hard IP is capable of operating independently from the core logic (autonomous mode). This feature allows the PCI Express link to power up and complete link training in less than 100 ms, while the rest of the device is still in the process of being configured. The hard IP also provides added functionality, which makes it easier to support emerging features such as Single Root I/O Virtualization (SR-IOV) and optional protocol extensions.
The PCI Express hard IP has improved end-to-end data path protection using Error Checking and Correction (ECC). In addition, the hard IP supports configuration of the device via protocol (CvP) across the PCI Express bus at Gen1/Gen2/Gen3 rates.
Ethernet MAC, Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514)
10G Ethernet Hard IP
Stratix® 10 TX devices include IEEE 802.3 10-Gbps Ethernet (10GbE) compliant 10GBASE-R PCS and PMA hard IP. The scalable 10GbE hard IP supports multiple independent 10GbE ports while using a single PLL for all the 10GBASE-R PCS instantiations, which saves on core logic resources and clock networks.
The integrated serial transceivers simplify multi-port 10GbE systems compared to 10 GbE Attachment Unit Interface (XAUI) interfaces that require an external XAUI-to-10G PHY. Furthermore, the integrated transceivers incorporate signal conditioning circuits, which enable direct connection to standard 10G XFP and SFP+ pluggable optical modules. The transceivers also support backplane Ethernet applications and include a hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) circuit that can be used for both 10G and 40G applications. The integrated 10G Ethernet hard IP and 10G transceivers save external PHY cost, board space and system power. The 10G Ethernet PCS hard IP and 10GBASE-KR FEC are present in every transceiver channel.
Interlaken PCS Hard IP
Stratix® 10 TX devices have integrated Interlaken PCS hard IP supporting rates up to 17.4 Gbps per lane.
The Interlaken PCS hard IP is based on the proven functionality of the PCS developed for Intel’s previous generation FPGAs, which has demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers. The Interlaken PCS hard IP is present in every transceiver channel in Stratix® 10 TX devices.
External Memory and General Purpose I/O
Stratix® 10 TX devices offer substantial external memory bandwidth, supporting DDR4 memory interfaces running at up to 2666 Mbps.
This bandwidth is provided along with the ease of design, lower power, and resource efficiencies of hardened high-performance memory controllers. The external memory interfaces can be configured up to a maximum width of 144 bits when using either hard or soft memory controllers.
Each I/O bank contains 48 general purpose I/Os and a high-efficiency hard memory controller capable of supporting many different memory types, each with different performance capabilities. The hard memory controller is also capable of being bypassed and replaced by a soft controller implemented in the user logic. The I/Os each have a hardened double data rate (DDR) read/write path (PHY) capable of performing key memory interface functionality such as:
- Read/write leveling
- FIFO buffering to lower latency and improve margin
- Timing calibration
- On-chip termination
The timing calibration is aided by the inclusion of hard microcontrollers based on Intel’s Nios® II technology, specifically tailored to control the calibration of multiple memory interfaces. This calibration allows the Stratix® 10 TX device to compensate for any changes in process, voltage, or temperature either within the device itself, or within the external memory device. The advanced calibration algorithms ensure maximum bandwidth and robust timing margin across all operating conditions.
|
Interface |
Controller Type |
Performance |
|---|---|---|
|
DDR4 |
Hard |
2666 Mbps |
|
DDR3 |
Hard |
2133 Mbps |
|
QDR II+ / II+ Xtreme |
Soft |
550 MTps |
|
RLDRAM III |
Soft |
2400 Mbps |
|
RLDRAM II |
Soft |
533 Mbps |
In addition to parallel memory interfaces, Stratix® 10 TX devices support serial memory technologies such as the Hybrid Memory Cube (HMC). The HMC is supported by the high-speed serial transceivers, which connect up to four HMC links, with each link running at data rates of 15 Gbps (HMC short reach specification) or 30 Gbps (HMC very short reach specification).
Stratix® 10 TX devices also feature general purpose I/Os capable of supporting a wide range of single-ended and differential I/O interfaces. LVDS rates up to 1.6 Gbps are supported, with each pair of pins having both a differential driver and a differential input buffer. This enables configurable direction for each LVDS pair.
Adaptive Logic Module (ALM)
Stratix® 10 TX devices use a similar adaptive logic module (ALM) as the previous generation Arria 10 and Stratix V FPGAs, allowing for efficient implementation of logic functions and easy conversion of IP between the devices.
The ALM block diagram shown in the following figure has eight inputs with a fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated registers.
Key features and capabilities of the ALM include:
- High register count with 4 registers per 8-input fracturable LUT, operating in conjunction with the new HyperFlex architecture, enables Stratix® 10 TX devices to maximize core performance at very high core logic utilization
- Implements select 7-input logic functions, all 6-input logic functions, and two independent functions consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core logic utilization
The Intel® Quartus® Prime software leverages the ALM logic structure to deliver the highest performance, optimal logic utilization, and lowest compile times. The Intel® Quartus® Prime software simplifies design reuse as it automatically maps legacy designs into the Stratix® 10 TX ALM architecture.
Core Clocking
Core clocking in Stratix® 10 TX devices makes use of programmable clock tree synthesis.
This technique uses dedicated clock tree routing and switching circuits, and allows the Intel® Quartus® Prime software to create the exact clock trees required for your design. Clock tree synthesis minimizes clock tree insertion delay, reduces dynamic power dissipation in the clock tree and allows greater clocking flexibility in the core while still maintaining backwards compatibility with legacy global and regional clocking schemes.
The core clock network in Stratix® 10 TX devices supports the new HyperFlex core architecture at clock rates up to 1 GHz. It also supports the hard memory controllers up to 2666 Mbps with a quarter rate transfer to the core. The core clock network is supported by dedicated clock input pins, fractional clock synthesis PLLs, and integer I/O PLLs.
Fractional Synthesis PLLs and I/O PLLs
Stratix® 10 TX devices have up to 48 fractional synthesis PLLs (fPLL) available for use with transceivers or in the core fabric.
The fPLLs are located in the 3D SiP transceiver tiles, eight per tile, adjacent to the transceiver channels. The fPLLs can be used to reduce both the number of oscillators required on the board and the number of clock pins required, by synthesizing multiple clock frequencies from a single reference clock source. In addition to synthesizing reference clock frequencies for the transceiver transmit PLLs, the fPLLs can also be used directly for transmit clocking. Each fPLL can be independently configured for conventional integer mode, or enhanced fractional synthesis mode with third-order delta-sigma modulation.
In addition to the fPLLs, Stratix® 10 TX devices contain up to 24 integer I/O PLLs (IOPLLs) available for general purpose use in the core fabric and for simplifying the design of external memory interfaces and high-speed LVDS interfaces. The IOPLLs are located in each bank of 48 general purpose I/O, one per I/O bank, adjacent to the hard memory controllers and LVDS SerDes in each I/O bank. This makes it easier to close timing because the IOPLLs are tightly coupled with the I/Os that need to use them. The IOPLLs can be used for general purpose applications in the core such as clock network delay compensation and zero-delay clock buffering.
Internal Embedded Memory
Stratix® 10 TX devices contain three types of embedded memory blocks: eSRAM (45-Mbit) in select devices, M20K (20-Kbit), and MLAB (640-bit). This variety of on-chip memory provides fast access times and low latency for applications such as wide and deep FIFOs and variable buffers.
The eSRAM blocks are a new innovation in Stratix® 10 TX devices. These large embedded SRAM blocks are tightly coupled to the core fabric and are directly accessible with no need for a separate memory controller. Each eSRAM block is arranged as 8 channels, 40 banks per channel, with a total capacity of 45-Mbits running at clock rates up to 750 MHz. Within the eSRAM block, each channel has a bus width of 72 bit read and 72 bit write, and has one READ and one WRITE per channel. This allows each eSRAM block to support a total aggregate bandwidth (read + write) of up to 864 Gbps.
The eSRAM block is implemented as a simple dual port memory with concurrent read and write access per channel, and includes integrated hard ECC generation and checking. Compared to an off-chip SRAM solution, the eSRAM block allows you to reduce system power and save board space and cost.
The M20K and MLAB blocks are familiar block sizes carried over from previous Intel device families. The MLAB blocks are ideal for wide and shallow memories, while the M20K blocks are intended to support larger memory configurations and include hard ECC. Both M20K and MLAB embedded memory blocks can be configured as a single-port or dual-port RAM, FIFO, ROM, or shift register. These memory blocks are highly flexible and support a number of memory configurations as shown in the below Table 1.
|
MLAB (640 bits) |
M20K (20 Kbits) |
|---|---|
|
64 x 10 (supported through emulation) 32 x 20 |
2K x 10 (or x8) 1K x 20 (or x16) 512 x 40 (or x32) |
Variable Precision DSP Block
The Stratix® 10 TX DSP blocks are based upon the Variable Precision DSP Architecture used in Intel’s previous generation devices. They feature hard fixed point and IEEE-754 compliant floating point capability.
The DSP blocks can be configured to support signal processing with precision ranging from 18x19 up to 54x54. A pipeline register has been added to increase the maximum operating frequency of the DSP block and reduce power consumption.
Each DSP block can be independently configured at compile time as either dual 18x19 or a single 27x27 multiply accumulate. With a dedicated 64-bit cascade bus, multiple variable precision DSP blocks can be cascaded to implement even higher precision DSP functions efficiently.
In floating point mode, each DSP block provides one single precision floating point multiplier and adder. Floating point additions, multiplications, mult-adds and mult-accumulates are supported.
The following table shows how different precisions are accommodated within a DSP block, or by utilizing multiple blocks.
|
Multiplier Size |
DSP Block Resources |
Expected Usage |
|---|---|---|
|
18x19 bits |
1/2 of Variable Precision DSP Block |
Medium precision fixed point |
|
27x27 bits |
1 Variable Precision DSP Block |
High precision fixed point |
|
19x36 bits |
1 Variable Precision DSP Block with external adder |
Fixed point FFTs |
|
36x36 bits |
2 Variable Precision DSP Blocks with external adder |
Very high precision fixed point |
|
54x54 bits |
4 Variable Precision DSP Blocks with external adder |
Double Precision floating point |
| Single Precision floating point | 1 Single Precision floating point adder, 1 Single Precision floating point multiplier | Floating point |
Complex multiplication is very common in DSP algorithms. One of the most popular applications of complex multipliers is the FFT algorithm. This algorithm has the characteristic of increasing precision requirements on only one side of the multiplier. The Variable Precision DSP block supports the FFT algorithm with proportional increase in DSP resources as the precision grows.
|
Complex Multiplier Size |
DSP Block Resources |
FFT Usage |
|---|---|---|
|
18x19 bits |
2 Variable Precision DSP Blocks |
Resource optimized FFT |
|
27x27 bits |
4 Variable Precision DSP Blocks |
Highest precision FFT |
For FFT applications with high dynamic range requirements, the Intel FFT IP Core offers an option of single precision floating point implementation with resource usage and performance similar to high precision fixed point implementations.
Other features of the DSP block include:
- Hard 18-bit and 25-bit pre-adders
- Hard floating point multipliers and adders
- 64-bit dual accumulator (for separate I, Q product accumulations)
- Cascaded output adder chains for 18- and 27-bit FIR filters
- Embedded coefficient registers for 18- and 27-bit coefficients
- Fully independent multiplier outputs
- Inferability using HDL templates supplied by the Intel® Quartus® Prime software for most modes
The Variable Precision DSP block is ideal to support the growing trend towards higher bit precision in high performance DSP applications. At the same time, it can efficiently support the many existing 18-bit DSP applications, such as high definition video processing and remote radio heads. With the Variable Precision DSP block architecture and hard floating point multipliers and adders, Stratix® 10 TX devices can efficiently support many different precision levels up to and including floating point implementations. This flexibility can result in increased system performance, reduced power consumption, and reduce architecture constraints on system algorithm designers.
Hard Processor System (HPS)
The Hard Processor System (HPS) in select Stratix® 10 TX devices is Intel’s industry leading third generation HPS. Leveraging the performance of Intel’s 14-nm Tri-Gate technology, the HPS provides more than double the performance of previous generation devices with an integrated quad-core 64-bit ARM Cortex-A53. The HPS also enables system-wide hardware virtualization capabilities by adding a system memory management unit. These architecture improvements ensure that Stratix® 10 TX devices will meet the requirements of current and future embedded markets, including wireless and wireline communications, data center acceleration, and numerous military applications.
Key Features of the Stratix 10 TX HPS
|
Feature |
Description |
|---|---|
| Quad-core ARM Cortex-A53 MPCore processor unit |
|
| System Memory Management Unit |
|
| Cache Coherency unit |
|
| Cache |
|
| On-Chip Memory |
|
| External SDRAM and Flash Memory Interfaces for HPS |
|
| Communication Interface Controllers |
|
| Timers and I/O |
|
| Interconnect to Logic Core |
|
Power Management
Stratix® 10 TX devices leverage the advanced Intel 14-nm Tri-Gate process technology, the all new HyperFlex core architecture to enable Hyper-Folding, power gating, and optional power reduction techniques to reduce total power consumption by as much as 70% compared to previous generation high-performance Stratix V devices.
SmartVoltage ID control over VCC is the standard option for the core power supply; a code is programmed into each device during manufacturing that allows a smart voltage regulator to operate the device at lower VCC while maintaining performance.
With the new HyperFlex core architecture, designs can run 2X faster than previous generation FPGAs. With 2X performance and same required throughput, architects can cut the data path width in half to save power. This optimization is called Hyper-Folding. Additionally, power gating reduces static power of unused resources in the FPGA by powering them down. The Intel® Quartus® Prime software automatically powers down specific unused resource blocks such as DSP and M20K blocks, at configuration time.
Furthermore, Stratix® 10 TX devices feature Intel’s industry-leading low power transceivers and include a number of hard IP blocks that not only reduce logic resources but also deliver substantial power savings compared to soft implementations. In general, hard IP blocks consume up to 50% less power than the equivalent soft logic implementations.
Device Configuration and Secure Device Manager (SDM)
All Stratix® 10 TX devices contain a Secure Device Manager (SDM), which is a dedicated triple-redundant processor that serves as the point of entry into the device for all JTAG and configuration commands. The SDM also bootstraps the HPS, ensuring that the HPS can boot using the same security features as the rest of the FPGA.
During configuration, Stratix® 10 TX devices are divided into logical sectors, each of which is managed by a local sector manager (LSM). The SDM passes configuration data to each of the LSMs across the on-chip configuration network. This allows the sectors to be configured independently, one at a time, or in parallel. This approach achieves simplified sector configuration and reconfiguration, as well as reduced overall configuration time due to the inherent parallelism. The same sector-based approach is used to respond to single-event upsets and security attacks.
While the sectors provide a logical separation for device configuration and reconfiguration, they overlay the normal rows and columns of FPGA logic and routing. This means there is no impact to the Intel® Quartus® Prime software place and route, and no impact to the timing of logic signals that cross the sector boundaries.
The SDM enables robust, secure, fully-authenticated device configuration. It also allows for customization of the configuration scheme, which can enhance device security. For configuration and reconfiguration, this approach offers a variety of advantages:
- Dedicated secure configuration manager
- Reduced device configuration time, because sectors are configured in parallel
- Updateable configuration process
- Reconfiguration of one or more sectors independent of all other sectors
- Zeroization of individual sectors or the complete device
The SDM also provides additional capabilities such as register state readback and writeback to support ASIC prototyping and other applications.
Device Security
Building on top of the robust security features present in the previous generation devices, Stratix® 10 TX devices include a number of new and innovative security enhancements. These features are also managed by the SDM, tightly coupling device configuration and reconfiguration with encryption, authentication, key storage and anti-tamper services.
Security services provided by the SDM include:
- Bitstream encryption
- Multi-factor authentication
- Hard encryption and authentication acceleration; AES-256, SHA-256/384, ECDSA-256/384
- Volatile and non-volatile encryption key storage and management
- Boot code authentication for the HPS
- Physically Unclonable Function (PUF) service
- Updateable configuration process
- Secure device maintenance and upgrade functions
- Side channel attack protection
- Scripted response to sensor inputs and security attacks, including selective sector zeroization
- Readback, JTAG and test mode disable
- Enhanced response to single-event upsets (SEU)
The SDM and associated security services provide a robust, multi-layered security solution for your Stratix® 10 TX design.
Configuration via Protocol Using PCI Express
Configuration via protocol using PCI Express allows the FPGA to be configured across the PCI Express bus, simplifying the board layout and increasing system integration. Making use of the embedded PCI Express hard IP operating in autonomous mode before the FPGA is configured, this technique allows the PCI Express bus to be powered up and active within the 100 ms time allowed by the PCI Express specification. Stratix® 10 TX devices also support partial reconfiguration across the PCI Express bus which reduces system down time by keeping the PCI Express link active while the device is being reconfigured.
Partial and Dynamic Reconfiguration
In addition to lowering power and cost, partial reconfiguration also increases the effective logic density by removing the necessity to place in the FPGA those functions that do not operate simultaneously. Instead, these functions can be stored in external memory and loaded as needed. This reduces the size of the required FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power. The partial reconfiguration process is built on top of the proven incremental compile design flow in the Intel® Quartus® Prime design software
Dynamic reconfiguration in Stratix® 10 TX devices allows transceiver data rates, protocols and analog settings to be changed dynamically on a channel-by-channel basis while maintaining data transfer on adjacent transceiver channels. Dynamic reconfiguration is ideal for applications that require on-the-fly multiprotocol or multi-rate support. Both the PMA and PCS blocks within the transceiver can be reconfigured using this technique. Dynamic reconfiguration of the transceivers can be used in conjunction with partial reconfiguration of the FPGA to enable partial reconfiguration of both core and transceivers simultaneously.
Fast Forward Compile
The innovative Fast Forward Compile feature in the Intel® Quartus® Prime software identifies performance bottlenecks in your design and provides detailed, step-by-step performance improvement recommendations that you can then implement. The Compiler reports estimates of the maximum operating frequency that can be achieved by applying the recommendations. As part of the new Hyper-Aware design flow, Fast Forward Compile maximizes the performance of your Stratix® 10 TX design and achieves rapid timing closure.
Previously, this type of optimization required multiple time-consuming design iterations, including full design re-compilation to determine the effectiveness of the changes. Fast Forward Compile enables you to make better decisions about where to focus your optimization efforts, and how to increase your design performance and throughput. This technique removes much of the guesswork of performance exploration, resulting in fewer design iterations and as much as 2X core performance gains for Stratix® 10 designs.
Single Event Upset (SEU) Error Detection and Correction
Stratix® 10 TX devices offer robust SEU error detection and correction circuitry. The detection and correction circuitry includes protection for Configuration RAM (CRAM) programming bits and user memories. The CRAM is protected by a continuously running parity checker circuit with integrated ECC that automatically corrects one or two bit errors and detects higher order multibit errors.
The physical layout of the CRAM array is optimized to make the majority of multi-bit upsets appear as independent single-bit or double-bit errors which are automatically corrected by the integrated CRAM ECC circuitry. In addition to the CRAM protection, the user memories also include integrated ECC circuitry and are layout optimized for error detection and correction.
The SEU error detection and correction hardware is supported by both soft IP and the Intel® Quartus® Prime software to provide a complete SEU mitigation solution. The components of the complete solution include:
- Hard error detection and correction for CRAM and user eSRAM and M20K memory blocks
- Optimized physical layout of memory cells to minimize probability of SEU
- Sensitivity processing soft IP that reports if CRAM upset affects a used or unused bit
- Fault injection soft IP with the Intel® Quartus® Prime software support that changes state of CRAM bits for testing purposes
- Hierarchy tagging in the Intel® Quartus® Prime software
- Triple Mode Redundancy (TMR) used for the Secure Device Manager and critical on-chip state machines
In addition to the SEU mitigation features listed above, the Intel 14-nm Tri-Gate process technology used for Stratix® 10 TX devices is based on FinFET transistors which have reduced SEU susceptibility versus conventional planar transistors.
Document Revision History
| Date | Version | Changes |
|---|---|---|
| August 2017 | 2017.08.02 | Made the following changes:
|
| October 2016 | 2016.10.31 | Initial release. |