The Intel^® Arria^® 10 family is designed to provide higher performance than the fastest FPGAs of the prior generation, and offers significant power advantages. Additionally, Smart Voltage ID (SmartVID) allows further reduction in both static and dynamic power consumption.

The Intel^® Arria^® 10 family operates at higher performance levels than prior generation 28-nm FPGAs. With 20-nm design rules, you can achieve significant power savings compared to 28-nm FPGAs. You can achieve even more power savings by applying additional power reduction techniques on the core voltage.

Smaller geometries and changes to the basic architecture provide the initial power savings of up to 15% over prior generation Arria^® V devices. Any static power increases are offset by reductions in dynamic power for an overall total power reduction. You can achieve up to 40% additional power savings through static power binning, and by controlling the core voltage. You can control the core voltage through SmartVID.

During manufacturing testing, Intel determines the optimum operating conditions for the core performance. A set of voltage values corresponding to those conditions are then programmed into nonvolatile registers in the device. The contents of these registers, and information about the silicon temperature, control the output of the voltage regulators, minimizing power consumption.

SmartVID has a large number of very small voltage reduction steps. Using SmartVID, the Intel^® Arria^® 10 device operates at the lowest possible voltage for a given speed grade. This enables power savings without sacrificing performance. SmartVID is offered as device-specific features. If you want to use either of these features, ensure that you order the correct product corresponding to the feature. For more information, refer to the " Intel^® Arria^® 10 Device Variants and Packages" section of the Intel^® Arria^® 10 Device Overview.

Intel^® Arria^® 10 SmartVID devices power up at default voltage (0.9 V). After the power-up sequence and device configuration, lower voltage is applied. This reduces V_CC SmartVID voltage to a value between 0.9 V and 0.85 V. When the junction temperature of the device is below 0° C, the voltage is increased to the original value.

The system is comprised of four main sections.

The VID register, temperature sensor, and VID soft controller are unchangeable. Intel provides the VID soft controller as a SmartVID Controller IP to customers. The remainder of the system may have many different solutions.

The voltage regulator controller interface can be implemented as:

• A parallel output to drive a digitally adjustable voltage regulator directly
• A multi-wire serial interface such as I2C, SMBus*, PMBus*, or similar interface hereafter referred to as PMBus
• A one-wire pulse width modulated (PWM) output to be used with a circuit to adjust the output of an adjustable voltage regulator

Intel provides reference designs for some of these functions. Contact your sales representative to find out what is available at this time.

The Voltage Regulator System can be implemented as:

• A parallel input digital voltage converter, such as the EC7401QI PWM controller from Intel^® Intel^® Enpirion^® portfolio.
• A multi-wire serial voltage converter that supports the PMBus standard such as the Intel^® Intel^® Enpirion^® Digital PowerSoC family. Example solutions include the EM2260, EM2140, EM2130, and EM2120.
• An adjustable voltage regulator with an analog circuit that converts the PWM signal to some means that controls the regulator output, allowing the use of standard analog voltage regulator controllers.

Sense lines from the die power rail to the ball accurately account for the voltage drop in the package at high currents. The power supply uses the sense lines as the feedback reference to avoid having the wrong voltage level under load. You must use the power sense lines in this fashion when using the SmartVID features.

The power sense lines are dedicated pins on the FPGA. Refer to the Intel^® Arria^® 10 GX, GT, and SX Device Family Pin Connection Guidelines for details.

All SmartVID systems start with the SmartVID soft controller. This controller reads data from a fuse register containing data obtained during production tests. This data is used with the temperature reading for the FPGA to create a value for the optimal voltage level.

The vidctl_vid_code port is the VID output code, which represents the 6-bit VID code. This value is also stored in the control and status register (CSR) and can be accessed via the Avalon^® Memory-Mapped interface.

When interfacing between the IP and your system, you should read the output when vidctl_vid_code_avail is asserted. This means that a new valid VID code is ready to be read. After the VID code is read, assert vidctl_vid_ack to let the SmartVID Controller IP Core know that the VID code is taken and a new value can be computed.

The first VID code output will be the default value, which is 0.9 V. How often the value will change depends on the temperature. If the temperature change causes the value to be updated, the VID code reduces to the targeted VID value with the decrement of VID_STEP per update. Likewise, it increases from the targeted VID value to 0.9 V with the increment of VID_STEP per update. VID code is only updated after you acknowledge that the current value is being read by asserting the vidctl_vid_ack input port.

For the SmartVID supported voltage range, refer to the Intel^® Arria^® 10 Device Datasheet.

There are many other ports on the SmartVID controller that need to be connected and used to configure the core. Please refer to the SmartVID Controller IP Core User Guide for more details.

The parallel output configuration uses an on-FPGA VID soft controller and parallel voltage regulator controller system. Together they create a value necessary to drive the correct data to the voltage regulator. The regulator decodes the parallel data and adjusts the voltage level to the FPGA. At power up, the bias network,which consists of weak pull-up and pull-down resistors, establishes the code for the default V_CC voltage for the FPGA. When the SmartVID Controller IP takes control and is done with initializations, it outputs the voltage code. It then enables the tri-state buffer, taking control of the V_CC level. Intel recommends that the enable signal originate from a specific pin (RZQ_2A) on the FPGA. Refer to the Intel^® Arria^® 10 GX, GT, and SX Device Family Pin Connection Guidelines for more information about pin assignments.

Intel will provide a reference design for a parallel control system with the release of the Intel^® Arria^® 10 PCIe* development kit. Contact your sales representative about the availability of intellectual property for this interface.

Using the EC7401QI 4-phase PWM controller with Parallel VID interface is one example solution for implementing the SmartVID capability of the Intel^® Arria^® 10 family. The EC7401QI drives up to four high current powertrain devices. The EC7401QI supports a wide range of Intel^® Arria^® 10 core power requirements. This solution easily enables system power reduction by leveraging the SmartVID capability via an Intel^® Arria^® 10 family parallel VID interface.

• The boot voltage must be in default value (0.9 V) before VID is applied.
• The regulator must accept parallel VID logic signals with a maximum logic voltage of 1.8 V. If you need a higher voltage for the signals to the regulator, then a level shifter may be inserted between the FPGA and the regulator if necessary.
• The 8-bit parallel VID code must be similar to the lowest 6 bits of the Intel VRM 11 8-bit VID code. The exception is that the voltage least significant bit (LSB) step size is 5 mV instead of 6.25 mV. The range of adjustment must include 0.83 V to 0.95 V. The Parallel VID code only uses even codes (10 mV steps); thus the LSB can be omitted. The VID code will change by no more than 10 mV per step. See Table 5.
• The regulator must accept a VID update rate of 10 ms. Additionally, the voltage must reach within the tolerance envelope (±5 mV of the new VID value) within 10 ms of the last transition on the VID signals.
• If you require multiple parallel regulators to achieve the output current target, then the group of regulators must behave in the same way as a single regulator with respect to the VID functions.
• The regulator(s) must meet the static and ripple (±30 mV) and dynamic (±5%) power tolerances during all phases of power delivery after the boot voltage is reached. Refer to the specifications described in the Intel^® Arria^® 10 GX, GT, and SX Device Family Pin Connection Guidelines.

In a PMBus system, the Intel^® Arria^® 10 device acts as either a PMBus master or a PMBus slave, according to your design choice. The following figure illustrates the simplest PMBus system for SmartVID support. In this case, the Intel^® Arria^® 10 device acts as a PMBus master and communicates the SmartVID information to the voltage regulator system directly through the PMBus.

In other PMBus systems, you may choose to have an external PMBus master separate from the Intel^® Arria^® 10 device. In this case, the Intel^® Arria^® 10 device may act as either a PMBus slave, or as a PMBus master in multi-master mode.

In this system, the VID soft controller feeds data to a PMBus Master interface on the FPGA. Other devices on the PMBus may require level shifters to translate the FPGA IO voltage to other voltage levels. PMBus systems can contain more than one regulator.

PMBus interface support is planned for release with Intel^® Quartus^® Prime software version 15.1. Contact your sales representative concerning the availability of PMBus interface support ahead of Intel^® Quartus^® Prime software version 15.1.

None of the pins on the FPGA are tied to any specific function for the PMBus interface.

Voltage converter systems that include the PMBus interface can help you implement the SmartVID capability of the Intel^® Arria^® 10 family.

Intel^® recommends using an Intel^® Intel^® Enpirion^® Digital Power Solution, such as the EM2260, EM2140, EM2130, or EM2120 devices, for new Intel^® Arria^® 10 designs. These devices are highly integrated, high current power modules with PMBus-compliant interfaces. This family of devices provides a single-chip solution for the programmable voltage regulator system needed to implement SmartVID and reduce system power. This maximizes power density while simplifying design.

• The regulator must support a default boot voltage prior to the issuing any VID commands.
• The regulator must support PMBus logic voltages no higher than 1.8 V (nominal). If the regulator logic levels are greater than 1.8 V, then some form of voltage level shifter is required for at least SCL and SDA signals.
• The regulator must support the PMBus Slave role with clock rates up to 400 kHz.
• The regulator must support the PMBus VOUT_MODE(0x20, R) command. The PMBus Master uses the VOUT_MODE command to interrogate the regulator to discover the data format for the VOUT_COMMAND values. The PMBus Master can be the FPGA or a system power manager.
• The regulator must support the PMBus VOUT_COMMAND (0x21, R/W) command. The PMBus Master uses the VOUT_COMMAND instruction in the data format retrieved from VOUT_MODE to write VID values to the regulator. The PMBus Master can be the FPGA or a system power manager. The VID voltage will change by no more than 10 mV per step.
• If you require multiple parallel regulators to achieve the output current target, then the group of regulators must behave as a single regulator with respect to the VID functions. This implies having distinct addresses for each of the regulators, and for the regulators to respond to VOUT_COMMAND using the SMBus Group Command Protocol. The SMBus Group Command Protocol writes to each address using repeated starts, with all devices simultaneously executing the command on the last STOP symbol.
• The regulator must accept a VID update rate of 10 ms, and the voltage must reach within the ±30 mV tolerance envelope within 10 ms of the last STOP symbol for transmitting VOUT_COMMAND. Voltage change for 10 mv should be between 20 µs and 45 µs for each step.
• The regulator(s) must meet the static and ripple and dynamic power tolerances listed in the Intel^® Arria^® 10 GX, GT, and SX Device Family Pin Connection Guidelines during all phases of power delivery after the boot voltage is reached.

The single-wire interface control system uses the PWM of a single signal. An analog process translates that signal into a current that is added to the voltage feedback node of the power supply module. Voltage sense lines and an accurate voltage reference provide the analog-to-digital converter on the FPGA with the resulting voltage level.

The single-wire interface is scheduled for release with Intel^® Quartus^® Prime software version 16.0. Please contact your sales representative for availability of single-wire interface support ahead of Intel^® Quartus^® Prime software version 16.0.

PWM VID feature has the following implementation requirements:

• General purpose I/O (GPIO) VDD must be held to 1.8 V+/-1% (tighter than pin connection guideline requirements).
• Slew rates of GPIO edges must be held to < 2 ns.
• GPIO output driver configuration must be push-pull with Rds < 25 Ω for both p-channel field effect transistor (pFET) and negative channel field effect transistor (nFET), such as 1.8 V SSTL Class II driver.
• Resistor insertion network must be scaled for suitable insertion values for the 10 mV/LSB VID steps.
• Resistor insertion network impedance must be high enough that 25-Ω driver resistance results in < 1% voltage error (about 30 kΩ).
• Slew rate of the VID changes must be limited to a maximum of 10 mV/20 µs by the regulator settings or the time constant of the resistor VID insertion network.
• The sense line current of the regulator(s) must not cause a voltage setting error of more than 1 mV with the VID resistor insertion network.
• An external reference for the voltage ADC must be used which has an accuracy over all causes of ±0.2% as shown in Figure 12.

The Intel^® Arria^® 10 device family Early Power Estimator (EPE) includes options for analyzing the possible power savings using SmartVID.

Figure 14. Example Early Power Estimator for Intel^® Arria^® 10 Devices

Intel^® Arria^® 10 FPGAs can inform its core V_CC Voltage Regulator Module (VRM) of its required voltage and have the VRM re-adjust its output voltage automatically to match. The Intel^® Arria^® 10 FPGA supports this Voltage ID (or VID) feature in three forms—parallel VID, serial VID, and PWM VID.

In parallel VID, the VRM is initially set to output a default voltage required by the FPGA device at power-on. Once the FPGA device is successfully powered on and configured, the FPGA outputs an 7-bit VID code (VID[6:0]) to the VRM. In a system using a VRM that uses 8 bits, the LSB is grounded. This informs the VRM that a voltage change is requested. Based on this unique code, the VRM re-adjusts (raises or lowers) its output voltage automatically to meet the new voltage required by the FPGA. This reduces the V_CC core power by the square of the voltage multiplied by the current.

An implementation of this feature requires both hardware and software (IP) support. For the hardware portion, the selected VRM for the V_CC core must support a parallel VID interface capable of supporting the VID voltage levels required by the Intel^® Arria^® 10 FPGA. Additionally, because the V_CC core can sink over 100 A of current, you must account for the DC IR drop of the PCB V_CC plane and device package. This compensation requires the VRM to support remote sensing. One solution that supports both VID and remote sensing is the EC7401QI 4-phase pulse-width modulation (PWM) controller with a 40A powertrain. This solution directly powers the V_CC core power of the Intel^® Arria^® 10 FPGA while supporting its VID requirements.

In PMBus SmartVID, the VRM is initially set to output a default voltage (0.9 V) required by the FPGA device at power-on. Once the FPGA device is successfully powered-on and configured, the FPGA uses PMBus to inform the VRM that a voltage change is requested. Based on the new configuration, the VRM re-adjusts (raises or lowers) its output voltage automatically to meet the new voltage required by the FPGA. In turn, the Intel^® Arria^® 10 device’s V_CC core power can be reduced by the square of the voltage multiplied by the current.

Implementing this feature requires both hardware and software (IP) support. For the hardware portion, the selected VRM for the V_CC core must support the PMBus interface and remote sensing. One solution that supports both the PMBus and remote sensing is the Intel^® Intel^® Enpirion^® EM2130xQI Digital PowerSoC DC–DC step-down converter with PMBus interface.. This solution is designed to directly power the V_CC core power of the Intel^® Arria^® 10 SoC FPGA while supporting its VID requirements. The following figure shows the block diagram of the PMBus implementation using the EM2130xQI solution to deliver up to 30A of V_CC core current. This solution is also footprint scalable with the Intel^® Intel^® Enpirion^® EM2120xQI and EM2140xQI solutions, which can deliver up to 20A and 40A V_CC core current respectively.

Intel recommends that you follow these guidelines to ensure VID system robustness.

• Power regulator ramp time for 10-mV changes:
  • Minimum = 20 µs
  • Maximum = 45 µs
  Note: The maximum ramp time is bounded by the configuration via protocol (CvP) requirement. This is only required if it is linked to T_RISE of VCC_core.
• 10 ms interval for every 10 mV step changes on top of the ramp time requirement above.
  Figure 19. Power Regulator Behavior Based on Ramp Time and 10-ms IntervalThis example shows a 20-µs ramp time and a VID voltage of 0.86 V.

  Table 6.  Operating Recommendations for VID Device Based on Temperature Grade

  Device Temperature Grade	Implementation Scheme
  Extended temperature (0° C to 100° C)	User mode temperature dependency control scheme: Disabled VID voltage changes immediately following user mode and before any user activity begins.
  Industrial temperature (-40° C to 100° C)	User mode temperature dependency control scheme: Enabled