AN 770: Partially Reconfiguring a Design on Intel Arria 10 SoC Development Board
Partially Reconfiguring a Design on Intel Arria 10 SoC Development Board
Partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. Create multiple personas for a particular region in your design, without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA device resources.
- Allows run-time design reconfiguration
- Increases scalability of the design
- Reduces system down-time
- Supports dynamic time-multiplexing functions in the design
- Lowers cost and power consumption through efficient use of board space
- Implementation of this reference design requires basic familiarity with the Intel® Quartus® Prime FPGA implementation flow and knowledge of the primary Intel® Quartus® Prime project files.
Reference Design Requirements
This reference design requires the following:
- Installation and basic familiarity with the Intel® Quartus® Prime Pro Edition version 17.1 design flow and project files for the design implementation.
- Connection with Intel® Arria® 10 SoC development kit for the FPGA implementation.
Reference Design Overview
Reference Design Files
The partial reconfiguration tutorial is available in the following location:
https://github.com/intel/fpga-partial-reconfig
- Click Clone or download.
- Click Download ZIP. Unzip the fpga-partial-reconfig-master.zip file.
- Navigate to the tutorials/a10_soc_devkit_blinking_led sub-folder to access the reference design.
The flat folder consists of the following files:
File Name | Description |
---|---|
top.sv |
Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module. |
top_counter.sv | Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and also powers LED[2] and LED[3] via the blinking_led module. |
blinking_led.sdc |
Defines the timing constraints for the project. |
blinking_led.sv | This module acts as the PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3]. |
blinking_led.qpf |
Intel® Quartus® Prime project file containing the list of all the revisions in the project. |
blinking_led.qsf |
Intel® Quartus® Prime settings file containing the assignments and settings for the project. |
The pr folder contains the complete set of files you create using this application note. Reference these files at any point during the walkthrough.
Reference Design Walkthrough
- Step 1: Getting Started
- Step 2: Creating a Design Partition
- Step 3: Allocating Placement and Routing Region for a PR Partition
- Step 4: Adding the Intel Arria 10 Partial Reconfiguration Controller IP Core
- Step 5: Defining Personas
- Step 6: Creating Revisions
- Step 7: Generating the Partial Reconfiguration Flow Script
- Step 8: Running the Partial Reconfiguration Flow Script
- Step 9: Programming the Board
Step 1: Getting Started
- Create a directory in your working environment, a10_soc_devkit_blinking_led_pr.
- Copy the downloaded tutorials/a10_soc_devkit_blinking_led/flat sub-folder to the directory, a10_soc_devkit_blinking_led_pr.
- In the Intel® Quartus® Prime Pro Edition software, click File > Open Project and select blinking_led.qpf.
- To compile the flat design, click Processing > Start Compilation.
Step 2: Creating a Design Partition
- Right-click the u_blinking_led instance
in the Project Navigator and click Design Partition > Set as Design Partition. A design partition icon appears next to each instance that is set as a
partition.
Figure 3. Creating Design Partitions from Project Navigator
- To define the partition Type,
right-click the u_blinking_led instance in the Hierarchy tab, click Design Partition > Reconfigurable. You can only define the partition Type after setting the instance as a partition.
The design partition appears on the Assignments View tab of the Design Partitions Window.Figure 4. Design Partitions Window
- Edit the partition name in the Design Partitions Window by
double-clicking the name. For this reference design, rename the partition name to pr_partition.
Note: When you create a partition, the Intel® Quartus® Prime software automatically generates a partition name, based on the instance name and hierarchy path. This default partition name can vary with each instance.
set_instance_assignment -name PARTITION pr_partition -to u_blinking_led set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON \ -to u_blinking_led
Step 3: Allocating Placement and Routing Region for a PR Partition
- Right-click the u_blinking_led instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region. The region appears on the Logic Lock Regions Window.
- Your placement region must enclose the blinking_led logic. Select the placement region by locating the node in Chip
Planner. Right-click the u_blinking_led region name in
the Logic Lock Regions Window and click
Locate Node > Locate in Chip Planner.
The u_blinking_led region is color-coded.
Figure 5. Chip Planner Node Location for blinking_led - In the Logic Lock Regions window,
specify the placement region co-ordinates in the Origin column. The origin corresponds to the lower-left corner of the
region. For example, to set a placement region with (X1
Y1) co-ordinates as (69 10), specify the
Origin as
X69_Y10. The
Intel®
Quartus® Prime software automatically
calculates the (X2 Y2) co-ordinates (top-right) for the
placement region, based on the height and width you specify.
Note: This tutorial uses the (X1 Y1) co-ordinates - (69 10), and a height and width of 20 for the placement region. Define any value for the placement region, as long as the region covers the blinking_led logic.
- Enable the Reserved and Core-Only options.
- Double-click the Routing Region option. The Logic Lock Routing Region Settings dialog box appears.
- Select Fixed with expansion for
the Routing type. Selecting this option
automatically assigns an expansion length of 1.
Note: The routing region must be larger than the placement region, to provide extra flexibility for the Fitter when the engine routes different personas.Figure 6. Logic Lock Regions Window
set_instance_assignment -name PLACE_REGION "69 10 88 29" -to u_blinking_led set_instance_assignment -name RESERVE_PLACE_REGION ON -to u_blinking_led set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to u_blinking_led set_instance_assignment -name ROUTE_REGION "68 9 89 30" -to u_blinking_led
Step 4: Adding the Intel Arria 10 Partial Reconfiguration Controller IP Core
- Type Partial Reconfiguration in the IP Catalog (Tools > IP Catalog).
- Double-click the Intel® Arria® 10 Partial Reconfiguration Controller IP core.
-
In the Create IP
Variant dialog box, type pr_ip
as the file name, and then click Create.
Use the default parameterization for pr_ip.
Ensure that the Enable JTAG debug mode
and Enable freeze interface options are
turned on, and Enable Avalon-MM slave
interface option is turned off.
Figure 7. Intel® Arria® 10 Partial Reconfiguration Controller IP Core Parameters
-
Click Finish, and exit
the parameter editor without generating the system. The parameter editor
generates the pr_ip.ip IP variation file
and adds the file to the blinking_led
project.
Note:
- If you are copying the pr_ip.ip file from the pr folder, manually edit the blinking_led.qsf file to include the
following
line:
set_global_assignment -name IP_FILE pr_ip.ip
- Place the IP_FILE
assignment after the SDC_FILE
assignments (jtag.sdc and
blinking_led.sdc) in your
blinking_led.qsf file. This
ordering ensures appropriate constraining of the Partial
Reconfiguration Controller IP core.
Note: To detect the clocks, the .sdc file for the PR IP must follow any .sdc that creates the clocks that the IP core uses. You facilitate this order by ensuring the .ip file for the PR IP core comes after any .ip files or .sdc files that you use to create these clocks in the .qsf file for your Intel® Quartus® Prime project revision. For more information, refer to the Partial Reconfiguration IP Solutions User Guide.
- If you are copying the pr_ip.ip file from the pr folder, manually edit the blinking_led.qsf file to include the
following
line:
Updating the Top-Level Design
- To add the pr_ip instance to the
top-level design, uncomment the following code block in top.sv file:
pr_ip u_pr_ip ( .clk (clock), .nreset (1'b1), .freeze (freeze), .pr_start (1'b0), // ignored for JTAG .status (pr_ip_status), .data (16'b0), .data_valid (1'b0), .data_ready () );
- To force the output ports to logic 1 during reconfiguration, use the
freeze control signal output from PR_IP. Uncomment the
following lines of
code:
assign led_two_on_w = freeze ? 1'b1 : pr_led_two_on; assign led_three_on_w = freeze ? 1'b1 : pr_led_three_on;
- To assign an instance of the default persona (blinking_led), update the top.sv file
with the following block of
code:
blinking_led u_blinking_led ( .led_two_on (pr_led_two_on), .led_three_on (pr_led_three_on), .clock (clock), .counter (count_d) );
Step 5: Defining Personas
- Create three SystemVerilog files, blinking_led.sv, blinking_led_slow.sv, and blinking_led_empty.sv in your working directory for the three
personas.
Note: If you create the SystemVerilog files from the Intel® Quartus® Prime Text Editor, disable the Add file to current project option, when saving the files.
Table 2. Reference Design Personas File Name Description Code blinking_led.sv Default persona with same design as the flat implementation `timescale 1 ps / 1 ps `default_nettype none module blinking_led ( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_two_on, output wire led_three_on ); localparam COUNTER_TAP = 23; reg led_two_on_r; reg led_three_on_r; assign led_two_on = led_two_on_r; assign led_three_on = led_three_on_r; always_ff @(posedge clock) begin led_two_on_r <= counter[COUNTER_TAP]; led_three_on_r <= counter[COUNTER_TAP]; end endmodule
blinking_led_slow.sv LEDs blink slower `timescale 1 ps / 1 ps `default_nettype none module blinking_led_slow ( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_two_on, output wire led_three_on ); localparam COUNTER_TAP = 27; reg led_two_on_r; reg led_three_on_r; assign led_two_on = led_two_on_r; assign led_three_on = led_three_on_r; always_ff @(posedge clock) begin led_two_on_r <= counter[COUNTER_TAP]; led_three_on_r <= counter[COUNTER_TAP]; end endmodule
blinking_led_empty.sv LEDs stay ON `timescale 1 ps / 1 ps `default_nettype none module blinking_led_empty( // clock input wire clock, input wire [31:0] counter, // Control signals for the LEDs output wire led_two_on, output wire led_three_on ); // LED is active low assign led_two_on = 1'b0; assign led_three_on = 1'b0; endmodule
Step 6: Creating Revisions
The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA. From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.
Synthesis Revision | Implementation Revision |
---|---|
blinking_led_default | blinking_led_pr_alpha |
blinking_led_slow | blinking_led_pr_bravo |
blinking_led_empty | blinking_led_pr_charlie |
Creating Implementation Revisions
- To open the Revisions dialog box, click Project > Revisions.
- To create a new revision, double-click <<new revision>>.
- Specify the Revision name as blinking_led_pr_alpha and select blinking_led for Based on Revision.
- Disable the Set as current revision option and click OK.
- Similarly, create blinking_led_pr_bravo
and blinking_led_pr_charlie revisions, based on the
blinking_led revision.
Note: Do not set the above revisions as current revision.

Creating Synthesis-Only Revisions
- In the Intel® Quartus® Prime software, click Project > Revisions.
- Create blinking_led_default revision based on blinking_led revision. Do not set this revision as current revision.
- Modify blinking_led_default.qsf file
to include the following
assignments:
set_global_assignment -name TOP_LEVEL_ENTITY blinking_led set_global_assignment -name SYSTEMVERILOG_FILE blinking_led.sv
- Similarly, create blinking_led_empty and blinking_led_slow revisions based on blinking_led revision. Do not set these revisions as current revision.
- Update the blinking_led_slow.qsf
and blinking_led_empty.qsf files with their
corresponding TOP_LEVEL_ENTITY and SYSTEMVERILOG_FILE
assignments:
##blinking_led_slow.qsf set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_slow set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_slow.sv
##blinking_led_empty.qsf set_global_assignment -name TOP_LEVEL_ENTITY blinking_led_empty set_global_assignment -name SYSTEMVERILOG_FILE blinking_led_empty.sv
- To avoid synthesis errors, ensure that the synthesis revision files do
not contain any design partition, Logic Lock region
assignments, or pin assignments. Remove these assignments, if any, in the blinking_led_default.qsf, blinking_led_slow.qsf, and blinking_led_empty.qsf
files:
set_instance_assignment -name PARTITION pr_partition -to u_blinking_led set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON \ -to u_blinking_led set_instance_assignment -name PLACE_REGION "69 10 88 29" -to u_blinking_led set_instance_assignment -name RESERVE_PLACE_REGION ON -to u_blinking_led set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to u_blinking_led set_instance_assignment -name ROUTE_REGION "68 9 89 30" -to u_blinking_led
- Verify that the blinking_led.qpf
file contains the following revisions, in no particular
order:
PROJECT_REVISION = "blinking_led" PROJECT_REVISION = "blinking_led_pr_alpha" PROJECT_REVISION = "blinking_led_pr_bravo" PROJECT_REVISION = "blinking_led_pr_charlie" PROJECT_REVISION = "blinking_led_default" PROJECT_REVISION = "blinking_led_slow" PROJECT_REVISION = "blinking_led_empty"
Note: If you are copying the revision files from pr folder, manually update the blinking_led.qpf file with the above lines of code.
Specifying Revision Type
- Partial Reconfiguration - Base
- Partial Reconfiguration - Persona Synthesis
- Partial Reconfiguration - Persona Implementation
Revision Name | Revision Type |
---|---|
blinking_led.qsf | Partial Reconfiguration - Base |
blinking_led_default.qsf | Partial Reconfiguration - Persona Synthesis |
blinking_led_empty.qsf | Partial Reconfiguration - Persona Synthesis |
blinking_led_slow.qsf | Partial Reconfiguration - Persona Synthesis |
blinking_led_pr_alpha.qsf | Partial Reconfiguration - Persona Implementation |
blinking_led_pr_bravo.qsf | Partial Reconfiguration - Persona Implementation |
blinking_led_pr_charlie.qsf | Partial Reconfiguration - Persona Implementation |
- Click Project > Revisions. The Revisions dialog box appears.
- Select blinking_led in the Revision Name column, and click Set Current.
- Click Apply. The blinking_led revision opens.
- To set the revision type for blinking_led, click Assignments > Settings.
- Select the Revision Type as Partial Reconfiguration - Base.
- Similarly, set the revision types for the other six revisions, as
listed in the above table.
Note: You must set each revision as the current revision before assigning the revision type.
##blinking_led.qsf
set_global_assignment -name REVISION_TYPE PR_BASE
##blinking_led_default.qsf
set_global_assignment -name REVISION_TYPE PR_SYN
##blinking_led_slow.qsf
set_global_assignment -name REVISION_TYPE PR_SYN
##blinking_led_empty.qsf
set_global_assignment -name REVISION_TYPE PR_SYN
##blinking_led_pr_alpha.qsf
set_global_assignment -name REVISION_TYPE PR_IMPL
##blinking_led_pr_bravo.qsf
set_global_assignment -name REVISION_TYPE PR_IMPL
##blinking_led_pr_charlie.qsf
set_global_assignment -name REVISION_TYPE PR_IMPL
Step 7: Generating the Partial Reconfiguration Flow Script
-
From the
Intel®
Quartus® Prime command shell, create a
flow template by running the following command:
quartus_sh --write_flow_template -flow a10_partial_reconfig
Intel® Quartus® Prime generates the a10_partial_reconfig/flow.tcl file. -
Rename the generated
a10_partial_reconfig/setup.tcl.example to
a10_partial_reconfig/setup.tcl, and modify the
script to specify your partial reconfiguration project details:
-
To define the name of the project, update the following
line:
define_project blinking_led
-
To define the base revision, update the following
line:
define_base_revision blinking_led
-
To define each of the partial reconfiguration
implementation revisions, along with the PR partition names and the
synthesis revision that implements the revisions, update the following
lines:
define_pr_impl_partition -impl_rev_name blinking_led_pr_alpha \ -partition_name pr_partition \ -source_rev_name blinking_led_default define_pr_impl_partition -impl_rev_name blinking_led_pr_charlie \ -partition_name pr_partition \ -source_rev_name blinking_led_empty define_pr_impl_partition -impl_rev_name blinking_led_pr_bravo \ -partition_name pr_partition \ -source_rev_name blinking_led_slow
Note: All the revision projects must be in the same directory as blinking_led.qpf. Otherwise, update the flow script accordingly.
-
To define the name of the project, update the following
line:
Step 8: Running the Partial Reconfiguration Flow Script
To run the partial reconfiguration flow script:
- Click Tools > Tcl Scripts. The Tcl Scripts dialog box appears.
- Click Add to Project, browse and select the a10_partial_reconfig/flow.tcl.
-
Select the a10_partial_reconfig/flow.tcl in the Libraries pane, and click
Run.
This script runs the synthesis for the three personas. Intel® Quartus® Prime generates a SRAM Object File (.sof), a Partial-Masked SRAM Object File (.pmsf), and a Raw Binary File (.rbf) for each of the personas.
quartus_sh -t a10_partial_reconfig/flow.tcl -setup_script \ a10_partial_reconfig/setup.tcl
Step 9: Programming the Board
- Connect the power supply to the Intel® Arria® 10 SoC development board.
- Connect the USB Blaster cable between your PC USB port and the USB Blaster port on the development board.
To run the design on the Intel® Arria® 10 SoC development board:
- Open the Intel® Quartus® Prime software and click Tools > Programmer.
- In the Programmer, click Hardware Setup and select USB-Blaster.
- Click Auto Detect and select the device, 10AS066N3.
- Click OK. The Intel® Quartus® Prime software detects and updates the Programmer with the three FPGA chips on the board.
- Select the 10AS066N3 device, click Change File and load the blinking_led_pr_alpha.sof file.
- Enable Program/Configure for blinking_led_pr_alpha.sof file.
- Click Start and wait for the progress bar to reach 100%.
- Observe the LEDs on the board blinking at the same frequency as the original flat design.
- To program only the PR region, right-click the blinking_led_pr_alpha.sof file in the Programmer and click Add PR Programming File.
- Select the blinking_led_pr_bravo.rbf file.
- Disable Program/Configure for blinking_led_pr_alpha.sof file.
- Enable Program/Configure for blinking_led_pr_bravo.rbf file and click Start. On the board, observe LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, LED[2] and LED[3] blink slower.
- To re-program the PR region, right-click the .rbf file in the Programmer and click Change PR Programing File.
- Select the .rbf files for the other two personas to observe the behavior on the board. Loading the blinking_led_pr_alpha.rbf file causes the LEDs to blink at a specific frequency, and loading the blinking_led_pr_charlie.rbf file causes the LEDs to stay ON.
Modifying an Existing Persona
For example, to cause the blinking_led_slow persona to blink even slower:
- In the blinking_led_slow.sv file, modify the COUNTER_TAP parameter from 27 to 28.
-
To re-synthesize and re-implement just this persona, run the following
command:
quartus_sh -t a10_partial_reconfig/flow.tcl -setup_script \ a10_partial_reconfig/setup.tcl -impl blinking_led_pr_bravo
This command re-synthesizes the blinking_led_slow synthesis revision, and then runs the PR implementation compile using blinking_led_pr_bravo. Follow the steps in Step 9: Programming the Board to program the resulting RBF file into the FPGA.Note: This command does not recompile the base revision.
References to how you can add new personas
References to how to compile your PR design
Adding a New Persona to the Design
For example, to define a new persona that keeps one LED on and the other LED off:
- Copy blinking_led_empty.sv to blinking_led_wink.sv.
- In the blinking_led_wink.sv file, modify the assignment, assign led_three_on = 1'b0; to assign led_three_on = 1'b1;.
-
Create a new synthesis revision, blinking_led_wink, by following the steps in Creating Synthesis-Only Revisions.
Note: The blinking_led_wink revision must use the blinking_led_wink.sv file.
- Create a new implementation revision, blinking_led_pr_delta, by following the steps in Specifying Revision Type.
-
Update the a10_partial_reconfig/setup.tcl file to
define the new PR implementation:
define_pr_impl_partition -impl_rev_name blinking_led_pr_delta \ -partition_name pr_partition \ -source_rev_name blinking_led_wink
-
Compile just this new revision by running the following command:
quartus_sh –t a10_partial_reconfig/flow.tcl –setup_script \ a10_partial_reconfig/setup.tcl –impl blinking_led_pr_delta
For complete information on partially reconfiguring your design for Intel® Arria® 10 devices, refer to Creating a Partial Reconfiguration Design in Volume 1 of the Intel® Quartus® Prime Pro Edition Handbook.
Document Revision History
Date | Version | Changes |
---|---|---|
2017.11.06 |
17.1.0 |
|
2017.05.08 |
17.0.0 |
|
2016.10.31 |
16.1.0 |
|
2016.07.07 |
16.0.0 |
Initial release of the document |