Shift Register (RAM-based) Intel FPGA IP Release Notes
1. Shift Register (RAM-based) Intel FPGA IP Release Notes
If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Intel® Quartus® Prime Design Suite Update Release Notes.
Intel® FPGA IP versions match the Intel® Quartus® Prime Design Suite software versions until v19.1. Starting in Intel® Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Intel® Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Intel® Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
1.1. Shift Register (RAM-based) Intel FPGA IP v19.1.0
| Intel® Quartus® Prime Version | Description | Impact |
|---|---|---|
| 20.4 | Initial release for Intel® Agilex™ devices. | — |
| Intel® Quartus® Prime Version | Description | Impact |
|---|---|---|
| 20.3 | Added "X" propagation support in simulation model for Intel® Stratix® 10 devices. | — |
1.2. Intel Agilex Embedded Memory User Guide Archives
| IP Core Version | User Guide |
|---|---|
| 19.3 | Intel® Agilex™ Embedded Memory User Guide |
1.3. Intel Stratix 10 Embedded Memory User Guide Archives
| IP Core Version | User Guide |
|---|---|
| 20.1 | Intel® Stratix® 10 Embedded Memory User Guide |
| 19.1 | Intel® Stratix® 10 Embedded Memory User Guide |
| 18.1 | Intel® Stratix® 10 Embedded Memory User Guide |
| 18.0 | Intel® Stratix® 10 Embedded Memory User Guide |
| 17.1 | Intel® Stratix® 10 Embedded Memory User Guide |
| 17.0 | Intel® Stratix® 10 Embedded Memory User Guide |