1. Shift Register (RAM-based) Intel FPGA IP Release Notes
If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the
Quartus® Prime Design Suite Update Release Notes.
Intel® FPGA IP versions match the
Quartus® Prime Design Suite software versions until v19.1. Starting in
Quartus® Prime Design Suite software version 19.2,
Intel® FPGA IP has a new versioning scheme.
Intel® FPGA IP version (X.Y.Z) number
can change with each
Quartus® Prime software version. A change in:
X indicates a major revision of the IP. If you update the
Quartus® Prime software, you must
regenerate the IP.
Y indicates the IP includes new features. Regenerate your IP
to include these new features.
Z indicates the IP includes minor changes. Regenerate your IP
to include these changes.