Scalable Switch Intel® FPGA IP for PCI Express* User Guide

ID 683515
Date 5/22/2023
Public

1. Overview

Updated for:
Intel® Quartus® Prime Design Suite 23.1
IP Version 3.0.0

P-Tile is an FPGA companion tile die that supports PCI Express Gen4 in Endpoint, Root Port and TLP Bypass modes. It serves as a companion tile for both Intel® Stratix® 10 DX and Intel Agilex® 7 devices. P-Tile natively supports Gen3 and Gen4 configurations in accordance with the PCI Express Base Specification 4.0 Rev 1.0.

The Scalable Switch Intel® FPGA IP for PCI Express is a fully configurable switch that implements one fully configurable upstream port and connectivity for up to 32 discrete downstream ports/embedded endpoints (E-EPs). This IP supports Hot Plug capability for the downstream ports.

You can use the Scalable Switch Intel FPGA IP for PCI Express along with the P-Tile Avalon Streaming Intel FPGA IP for PCI Express in TLP Bypass mode to configure the discrete downstream ports or use the Intel Scalable Switch IP to configure the embedded endpoints allowing the use of fewer PCIe physical links.

The Scalable Switch Intel FPGA IP implements the upstream and downstream port configuration spaces and associated logic to route packets between the different ports. The P-Tile Avalon Streaming Intel FPGA IP for PCI Express can be used in TLP Bypass mode to implement the upstream port as well.

Note: The Scalable Switch Intel FPGA IP for PCI Express requires the use of a third party PCI Express Bus Functional Model (BFM).

The following three figures show Switch configurations using the Scalable Switch Intel FPGA IP for PCI Express. In the first configuration, the Endpoints are external to the Scalable Switch Intel FPGA IP (these are referred to as discrete Endpoints). In the second configuration, they are embedded in the IP. The third configuration is a mix of embedded Endpoints and discrete Endpoints.

Figure 1. Intel Switch IP with Discrete Endpoints
Note: Supporting discrete Endpoints requires the instantiation of the Intel Scalable Switch IP with Downstream switch port type for each discrete Endpoint.
Figure 2. Intel Switch IP with Embedded Endpoints
Figure 3. Intel Switch IP with a Combination of Discrete Endpoints and Embedded Endpoints