AC and servo drive system designs comprise multiple distinct but interdependent functions to realize requirements to meet the performance and efficiency demands of modern motor control systems. The system's primary function is to efficiently control the torque and speed of the AC motor through appropriate control of power electronics. A typical drive system includes the following items:

• Flexible pulse-width modulation (PWM) circuitry to switch the power stage transistors appropriately
• Motor control loops for single- or multiaxis control
• Industrial networking interfaces
• Position encoder interfaces
• Current, voltage, and temperature measurement feedback elements.
• Monitoring functions, for example, for vibration suppression.

The system requires system software running on a processor for high-level system control, coordination, and management.

Intel Cyclone^® and Intel^® MAX^® 10 devices offer high-performance fixed- and floating-point DSP functionality. Cyclone V SoC devices offer the integrated ARM-based hard processor subsystem (HPS); other Cyclone FPGA and Intel^® MAX^® 10 FPGA devices offer support for Nios II soft processors. Cyclone and Intel^® MAX^® 10 FPGA devices offer a uniquely scalable and flexible platform for integration of single- and multiaxis drives on a single FPGA. The Intel motor control development framework allows you to create these integrated systems easily. The framework provides a reference design that comprises IP cores, software libraries, and a hardware platform. The framework seamlessly integrates Intel system-level design tools such as DSP Builder and Qsys, and software and IP components that allow you to extend and customize the reference design to meet your own application needs. The framework also supports optimal partitioning decisions between software running on an integrated processor and IP performing portions of the motor control algorithm in the FPGA, to accelerate performance as required. For example, depending on the performance requirements of your system or the number of axes you need to support, you may implement all of the inner current control loop in hardware or entirely in software. The framework flexibly allows you to connect to the motor and power stages through off-chip ADCs, and feedback encoder devices and to connect to higher-level automation controllers through off-the-shelf digital encoder and industrial Ethernet IP cores, respectively.

The reference design offers vibration suppression, when you target the Cyclone V SoC devices. The design demonstrates how you can implement standard components (FFTs, FFT-post processing, IIR filter), to enable you to develop an automatic method for vibration suppression. You may use the FFTs and FFT postprocessing for condition monitoring, which detects vibrations that indicate degradation or wear and communicate the results to another system.

The reference design integrates Motor Control IP Suite components, a Nios^® II soft processor subsystem, or ARM-based HPS, and software that uses an FOC algorithm. The reference design uses the Intel DSP Builder system-level design tool to implement the FOC algorithm.

DSP Builder provides a MATLAB and Simulink flow that allows you to create hardware optimized fixed latency representations of algorithms without requiring HDL/hardware skills. Intel provides DSP Builder fixed-point and floating point algorithms to demonstrate both options. The DSP Builder folding feature reduces the resource usage of the logic as an alternative to a fully parallel implementation. The reference design also includes an efficient Avalon^® Memory-Mapped interface that you can integrate in Qsys.

The demonstration shows how to improve speed control. Speed is never perfectly constant because motors include discrete parts such as magnets, electrical coils and steel cages to hold these components. As the motor rotates, the torque produced for a given current magnitude varies. These variations (cogging torques) produce accelerations leading to speed variations. The feedback controller adjusts the current to counteract the speed variations depending on the strength of the control gains. Stronger gains reduce speed variation, but may lead to control instability or amplify mechanical resonances.

The demonstration shows the level of speed variation with default speed control gains. It then shows the speed control step response. The step response should be fast and with little overshoot or oscillation, so the speed output should look similar to the square-wave input command. The speed control step response with standard gains is slow and may stop briefly at zero speed because of friction when the motor changes direction. Increasing the speed control loop proportional gain makes the response look much faster and without any visible stop at zero speed. However, the motor produces high-frequency noise that is audible and visible in the FFTs as a broad peak around 1kHz. In a real system with a mechanism connected to the motor, this noise can easily excite mechanical vibrations. To counteract this undesirable change, apply the suppression filter using a broad notch characteristic centred on 1kHz. The resulting waveform still has a fast, square shape, but the filter suppresses the noise. The speed variation with the combination of high gain and filter is much less than the original graph, showing the benefit of the faster control.

FOC controls a motor's sinusoidal 3-phase currents in real time to create a smoothly rotating magnetic flux pattern, where the frequency of rotation corresponds to the frequency of the sine waves. FOC controls the current vector to keep:

• The torque-producing quadrature current, Iq, at 90 degrees to the rotor magnet flux axis
• The direct current component, Id, (commanded to be zero) inline with the rotor magnet flux.

The FOC algorithm:

1. Converts the 3-phase feedback current inputs and the rotor position from the encoder into quadrature and direct current components using Clarke and Park transforms.
2. Uses these current components as the inputs to two proportional and integral (PI) controllers running in parallel to limit the direct current to zero and the quadrature current to the desired torque.
3. Converts the direct and quadrature voltage outputs from the PI controllers back to 3-phase voltages with inverse Clarke and Park transforms.

The FOC algorithm includes:

• Forward and reverse Clarke and Park transforms
• Direct and quadrature current
• Proportional integral (PI) control loops
• Sine and cosine
• Saturate functions

After you develop the algorithm in Simulink*, DSP Builder can automatically generate pipelined HDL that it targets and optimizes to the chosen FPGA device. You can use this VHDL in a HDL simulator such as ModelSim* to verify the generated logic versus Simulink* and in the Quartus Prime software to compile the hardware. DSP Builder for Intel FPGAs gives instant feedback of the VHDL's logic utilization and algorithm latency in automatically generated Simulink* reports.

The DSP Builder for Intel FPGAs folding feature reuses physical resources such as multipliers and adders for different calculations with the VHDL generation automatically handling the complexity of building the time division multiplexed (TDM) hardware for the particular sample to clock rate ratio.

Intel compared floating- and fixed-point versions of the FOC algorithm with and without folding. In addition, Intel compared using a 26-bit (17-bit mantissa) instead of standard single-precision 32-bit (23-bit mantissa) floating point implementation. 26-bit is a standard type within DSP Builder that takes advantage of the FPGA architecture to save FPGA resources if this precision is sufficient.

Cyclone V devices use ALMs instead of LEs (one ALM is approximately two LEs plus two registers) and DSP blocks instead of multipliers (one DSP block can implement two 18-bit multipliers or other functions).

The results show:

• The model with folding uses fewer processing resources but has an increase in latency.
• A floating-point model with folding also uses significantly fewer logic resources (LEs/ALMs) than a model without folding.
• The 26-bit floating-point format saves significant resources compared to 32-bit in MAX 10 devices but proportionally less in Cyclone V SoCs.
• The fixed-point algorithms without folding use the fewest logic resources and give the lowest latency.

The reference design implements these FOC configurations:

• Floating-point 26-bit model on MAX 10 devices ; 32-bit on Cyclone V, both with folding.
• Fixed-point 16-bit model without folding.

The FOC algorithm comprises the FOC algorithm block and a latch block for implementing the integrators necessary for the PI controllers in the FOC algorithm. DSP Builder for Intel FPGAs implements the latches outside because of limitations of the folding synthesis.

The reference design includes fixed-point and floating-point models that implement the FOC algorithm.

Each model calls a corresponding .m setup script during initialization to set up the arithmetic precision, folding factor, and target clock speed. The folding factor is set to a large value to minimize resource usage.

The following models generate the FOC block including the Avalon-MM interface:

• DF_float_alu_av.slx for floating-point designs
• DF_fixp16_alu_av.slx for fixed-point designs

Verification models stimulate the FOC algorithm using dynamically changing inputs:

• verify_DF_float_alu.slx
• verify_DF_fixp16_alu.slx

Closed-loop simulation models validate that the FOC correctly controls a motor in simulation:

• sim_DF_float_alu.slx
• sim_DF_fixp16_alu.slx

A Simulink* library model contains the main FOC algorithm code, which the models reference:

• foc_blocks.slx

To allow direct connectivity in Qsys, the top-level DSP Builder for Intel FPGAs design adds blocks to terminate the parallel inputs and outputs and handshaking logic with an Avalon-MM register map.

DSP Builder for Intel FPGAs generates a .h file that contains address map information for interfacing with the DSP Builder for Intel FPGAs model.

To run the DSP Builder for Intel FPGAs model as part of the drive algorithm, a C function passes the data values between the processor and DSP Builder for Intel FPGAs. The handshaking logic ensures synchronization between the software and hardware. The software sets up any changes to hardware parameters such as PI gains, writes new feedback currents, position feedback and torque command input data before starting the DSP Builder for Intel FPGAs calculation. The software then waits for the DSP Builder for Intel FPGAs calculation to finish before reading out the new voltage command data.

The ISR that runs the FOC algorithm calls the C function with an option to switch between software and DSP Builder for Intel FPGAs implementations at runtime.

The processing time with a 100-MHz clock is around 0.6ms including the time to clock data out of the FFT block again. The processing time for two parallel FFTs is the same. You may choose other FFT implementations for the FPGA for faster processing times if required, at the expense of FPGA resources.

Methods of automatically tuning filter and control gains depend on:

• Knowledge of the mechanical and electrical properties of the mechanisms that the motor drives
• The effects of different filter settings on the overall control response

You can choose the waveform shape, period (expressed as a number of 16 kHz samples), and amplitude.

The IIR filter is a configurable second-order digital filter, based on the second-order continuous time transfer function (in Laplace notation):

The design converts the continuous time formulation to a discrete-time formulation using a combination of the Tustin (bilinear) transformation and frequency prewarping, which ensures that the discrete time and continuous time filter characteristics match at a specified frequency Ω:

The design applies prewarping to the denominator terms with Ω = Ωd and to the numerator terms with Ω = Ωn, which ensures that the filter preserves the corner frequencies of Ωd and Ωn after the transformation.

The design applies the IIR filter to the Vd and Vq voltage signals. These signals are the final outputs of the linear control system before the trigonometric transformation to stator-fixed voltages (V_α and V_β) and the space vector modulation (SVM) conversion to transistor gate signals.

The IIR filter is integrated into the FOC algorithm. Different DSP modes use different implementations of the FOC algorithm. Each implementation of the FOC algorithm includes a matching implementation of the IIR filter.

• Nios II fast processor
• Floating-point hardware custom instructions 2 (optional)
• Tightly coupled instruction and data memory
• JTAG master
• Performance counters
• Clocking and bridge
• SDRAM controller
• JTAG UART
• System console debugging RAM
• Debugging dump memory

The ISR uses the tightly coupled memory blocks for code and data to ensure fast predictable execution time for the motor control algorithm.

The Nios II subsystem uses the JTAG master and debug memories to allow real-time interactions between System Console and the processor. The reference design uses the System Console debugging RAM to send commands and receive status information. The debugging dump memory stores trace data that you can display as time graphs in System Console.

• 6-channel pulse width modulator (PWM)
• ADC interface
• BiSS encoder interface
• EnDat encoder interface
• Drive system monitor

The reference design puts the motor control peripheral components in a separate Qsys subsystem (DOC_AXIS_Periphs.qsys), which allows you to disable, enable, or add, extra axes.

This section describes the motor control peripheral components and describes specific connectivity issues when instancing the motor control suite peripherals in Qsys.

The PWM provides synchronization between multiple PWM instances. To implement this feature the reference design programs the PWMs identically: in Qsys one instance is the master PWM and connects the sync_out port to the other PWM sync_in port. For additional instances, continue chaining the sync_out port from the last instance to the next sync_in port. For example:

sync_out (PWM0) to sync_in (PWM1) and sync_out(PWM1) to sync_in(PWM2)

An internal counter defines the PWM period from 0 to PWM_MAX and then back to 0. The design configures it for an 8-kHz rate, and the internal clock rate of the PWM is 50 MHz. To achieve an 8-kHz period with an internal clock rate of 50 MHz, set the carrier register value to 3,125. Therefore:

carrier = (50 MHz / 8 kHz) / 2 = 3,125

The carrier_latch output indicates to the position encoder to take a position reading. It is high for one clock cycle when the counter is at zero and at PWM_MAX.

The start output indicates to the phase current ADC interfaces to start sampling. It is offset from the carrier_latch position, so it occurs at a fixed position before it. The pwm_trigger_up sets the trigger value when the PWM counter is counting up; pwm_trigger_down sets the trigger value when counting down (Table 14).

To offset the effect of current ripple, the reference design centers the ADC reading at the PWM reversal point. The reference design configures the start pulse to be at:

(settling time)/2

The reference design configures the phase current ADC interfaces to a decimation rate of M = 128, which requires a settling time of 19.2 s. To centre the ADC sampling, apply an offset to the PWM trigger of 9.6 s (480 clock periods @ 50 MHz).

For an ADC clock rate of 20 MHz,

An additional ADC measures the combined current flowing from the DC link for power consumption measurements.

The EnDat IP core requires a strobe to capture a position reading at a time synchronized with the ADC interface. The reference design generates the EnDat strobe at the exact reversal point of the PWM without offset.

The ip\biss_OCP directory includes the datasheet for the BiSS Master IP core.

The BiSS IP core requires a strobe to capture a position reading at a time synchronized with the ADC interface. The reference design generates the BiSS strobe at the exact reversal point of the PWM without offset.

Doxygen generated HTML help files are in the software\CVSX_DS5\DOC_CVSX\source\doxygen or software\source\doxygen directory. Open the index.html file in a browser to view the help files.

Intel provides DS-5 debug script that first loads and runs the preloader, then loads and runs the application to a breakpoint at main(). Execution can continue from this point or you can set further breakpoints or configure memory watch windows.