Video and Image Processing Suite Release Notes
Video and Image Processing Suite Release Notes
If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Intel® Quartus® Prime Design Suite Update Release Notes.
The following IP cores are no longer supported in versions 17.0 and later:
- 2D FIR Filter
- Alpha Blending Mixer
- Chroma Resampler
- Color Space Converter
- Color Plane Sequencer
- Control Synchronizer
- Deinterlacer
- Frame Buffer
- Frame Reader
- Gamma Corrector
- Interlacer
- Switch
Intel recommends that you use the upgraded versions of these IP cores.
Video and Image Processing Suite v19.1
Description | Impact |
---|---|
Added support for Intel® Stratix® 10 devices. |
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added the Support 6G and 12G-SDI parameter in the Clocked Video Input II Intel FPGA IP. This parameter enables support for 6G-SDI or 12G-SDI. |
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Added the Support 6G and 12G-SDI
and Default SDI video standard parameters in the
Clocked Video Output II Intel FPGA IP.
|
Video and Image Processing Suite v18.1
Description | Impact |
---|---|
Added new registers for the Deinterlacer II Intel FPGA IP.
|
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added new GUI parameters for the Mixer II Intel FPGA IP.
|
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Added new test pattern options for the Test Pattern II Intel FPGA IP. |
Video and Image Processing Suite v18.0
Description | Impact |
---|---|
Support for 8 pixels in parallel are now available for
the following IP cores:
|
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Clocked Video Output II IP core now supports Genlock. | |
Added new GUI parameters for the Clocked Video Output
II IP core:
|
|
Added Genlock signals for the Clocked Video Output II IP core:
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Video and Image Processing Suite v17.1
Description | Impact |
---|---|
Renamed Qsys to Platform Designer as per Intel rebranding. | – |
All Video and Image Processing IP cores that support 4:2:2 feature require even frame widths when using 4:2:2 data; odd frame widths create unpredictable results or distorted images. | – |
Added new parameters for Frame Buffer II IP core:
|
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Video and Image Processing Suite v17.0
Description | Impact |
---|---|
Added a new IP core: Configurable Guard Bands IP core. This IP core supports pixels in parallel and run-time control. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added device support for Intel Cyclone 10 LP and Cyclone 10 GX devices. | |
Removed the following IP cores. These IP cores are no longer supported
in Quartus Prime versions 17.0 and later.
|
|
Added new parameters for the Chroma Resampler II IP core:
|
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Removed these parameters for the Deinterlacer II IP core:
|
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Changed Cadence Detect On register to Cadence Detect and advanced tuning registers On register for the Deinterlacer II IP core. This updated register enables the cadence detection feature and (if configured) the video over film feature together with all the motion and cadence/VOF tuning registers. | |
Removed edge sharpening feature for the Scaler II IP core. |
Video and Image Processing Suite v16.1
Description | Impact |
---|---|
Added the following new IP cores for 16.1 release:
All these IP cores support pixels in parallel and run-time control. |
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Removed the Broadcast Deinterlacer IP core and merged the features into the Deinterlacer II IP core. If you were using the Broadcast Deinterlacer IP core versions 15.1 or 16.0, Qsys will automatically upgrade your design to the Deinterlacer II version 16.1 with the same configuration. |
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Mixer II IP core
|
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Clocked Video Interface IP core
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Video and Image Processing Suite v16.0
Description | Impact |
---|---|
Avalon-ST Video Stream Cleaner IP core
|
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Frame Buffer II IP core
|
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Mixer II IP core
|
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Clocked Video Interface IP core
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Switch II IP core
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Video and Image Processing Suite v15.1
Description | Impact |
---|---|
Removed Clipper and Test Pattern Generator IP cores. Use Clipper II and Test Pattern Generators II IP cores instead. | If you are using the obsoleted IP cores, you will not get any support from Altera. |
Supports Quartus Prime Standard edition only. | – |
Video and Image Processing Suite v15.0
Description | Impact |
---|---|
Updated the Input (0-3) Enable
registers for the Mixer II IP core. The 1-bit registers are changed to
2-bit registers:
|
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Updated the parameter settings for the Mixer II IP
core.
|
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Updated the parameter settings for the Frame Buffer
II IP core.
|
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Updated the parameter settings for the Avalon-ST
Video Monitor IP core.
|
Video and Image Processing Suite v14.1
Description | Impact |
---|---|
Updated the parameters for Clocked Video Input
II and Clocked Video Output II IP cores.
|
- |
Video and Image Processing Suite v14.0 Arria 10 Edition
Description | Impact |
---|---|
Added support for Arria 10 devices only in the
following IP cores:
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- |