High-Definition Multimedia Interface (HDMI) Intel FPGA IP Release Notes
1. Intel FPGA HDMI IP Release Notes
If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Intel® Quartus® Prime Design Suite Update Release Notes.
Intel® FPGA IP versions match the Intel® Quartus® Prime Design Suite software versions until v19.1. Starting in Intel® Quartus® Prime Design Suite software version 19.2, Intel® FPGA IP has a new versioning scheme.
The Intel® FPGA IP version (X.Y.Z) number can change with each Intel® Quartus® Prime software version. A change in:
- X indicates a major revision of the IP. If you update the Intel® Quartus® Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
1.1. HDMI Intel FPGA IP v19.6.0
Intel® Quartus® Prime Version | Description | Impact |
---|---|---|
20.4 |
Added support for HDMI 2.1 with fixed rate link (FRL) enabled for Intel® Stratix® 10 devices. |
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
1.2. HDMI Intel FPGA IP v19.5.0
Intel® Quartus® Prime Version | Description | Impact |
---|---|---|
20.3 |
The HDMI Intel® FPGA IP is repackaged. Added the following new parameters to include a RAM for storing EDID and I2C master or slave depending on the selected direction.
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These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Made changes in the interface as a result of the repackaging. Refer to the Source Interfaces and Sink Interfaces section in the HDMI Intel FPGA IP User Guide for more information. |
1.3. HDMI Intel FPGA IP v19.4.0
Intel® Quartus® Prime Version | Description | Impact |
---|---|---|
20.2 |
Added support for High-bandwidth Digital Content Protection (HDCP) feature for Intel® Stratix® 10 devices. This feature has also been available for Intel® Arria® 10 devices since the Intel® Quartus® Prime Pro Edition software version 19.3 and later. |
The HDCP feature is not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html. |
Intel® Quartus® Prime Version | Description | Impact |
---|---|---|
20.1 |
Added support for deep color implementation for HDMI 2.1 with fixed rate link (FRL) enabled. HDMI 2.1 is available only for Intel® Arria® 10 devices. |
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Enabled a DIP switch (dipsw) for HDMI 2.1 design examples. The switch enables you to toggle between passthrough mode and independent RX and TX mode, which can operate at different link rates. |
1.4. HDMI Intel FPGA IP v19.3.0
Intel® Quartus® Prime Version | Description | Impact |
---|---|---|
19.4 |
Added support for HDMI 2.1 with fixed rate link (FRL) enabled for Intel® Arria® 10 devices. |
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added the Support FRL parameter in the HDMI Intel® FPGA IP parameter editor. |
1.5. HDMI Intel FPGA IP v19.1
Description | Impact |
---|---|
Enabled final support for Intel® Stratix® 10 L-tile and H-tile devices. The design examples now target Intel Stratix 10 production devices. |
If you want to target your designs to use Intel® Stratix® 10 L-tile devices, you must upgrade your IP core. |
1.6. HDMI Intel FPGA IP v18.1 Update 1
18.1.1 December 2018
- For Intel® Stratix® 10 H-Tile devices, added VID_OPERATION_MODE "PMBUS MASTER" and PWRMGMT settings to the video connectivity design example IP .qsf file to enable Intel® Stratix® 10 SmartVID and power management capabilities.
1.7. HDMI Intel FPGA IP v18.1
Description | Impact |
---|---|
Improved the HDMI RX video lock time for HDMI 2.0 for Intel® Stratix® 10 design examples. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added support for Bitec HDMI FMC daughter card revision 11 in the Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 design examples. |
1.8. HDMI Intel FPGA IP v18.0
Description | Impact |
---|---|
Renamed Intel FPGA HDMI IP to HDMI Intel® FPGA IP as part of standardizing and rebranding exercise. | – |
Added preliminary support for Intel® Stratix® 10 (H-Tile) devices. | The Intel® Stratix® 10 devices are only available in the Intel® Quartus® Prime Pro Edition software. |
Updated the HDMI Intel® FPGA IP to support HDMI Specification 2.0b. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added support for Xcelium* Parallel simulator. | |
Added the following files:
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Added support for SCDC read request feature in the HDMI RX core. | |
Added final support for Intel® Cyclone® 10 GX devices. | The Intel® Cyclone® 10 GX devices are only available in the Intel® Quartus® Prime Pro Edition software. |
Added new design examples for Intel® Cyclone® 10 GX devices in version 17.1.1 release. Refer to the HDMI Intel Cyclone 10 GX FPGA IP Design Example User Guide for more information. |
Design Example | Required Files |
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Intel® Arria® 10 |
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Intel® Cyclone® 10 GX |
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1.9. Intel FPGA HDMI IP Core v17.1
Description | Impact |
---|---|
Renamed the following as per Intel
rebranding:
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– |
The Support for deep color parameter is now turned on by default. | – |
Added advance support for Intel® Cyclone® 10 GX devices. | The Intel® Cyclone® 10 GX devices are only available in the Intel® Quartus® Prime Pro Edition software. |
Added support for up to 32 audio channels. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added support for up to 1,536 kHz audio sample frequency. | |
In previous versions of the Intel FPGA HDMI design example for Intel® Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in the Intel® Quartus® Prime software version 17.1. |
If you are upgrading designs that have these additional constraints from the previous versions of the Intel® Quartus® Prime software to version 17.1, you must revise the constraints. Refer to the KDB page for more information. |
1.10. HDMI IP Core v17.0
Description | Impact |
---|---|
Available in both Quartus Prime Pro Edition and Quartus Prime Standard Edition. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added demonstration for HDR InfoFrame insertion and filtering. | |
Changed to FPLL direct for TX transceiver. | |
Enabled TX PMA recalibration. |
1.11. HDMI IP Core v16.1
Description | Impact |
---|---|
The 16.1 version of the HDMI IP core is available only in Quartus Prime Standard Edition. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added new Design Example tab in the HDMI IP core parameter editor. The design example is for Arria 10 devices. Refer to the HDMI IP Core Design Example User Guide for more information. | |
Changed audio_de port width to 1 bit. | |
Added EDID information pass trough from external sink to external source through the FPGA in the Arria 10 design example. | |
Removed Support 8-channel audio parameter. The IP core supports 8-channel audio by default. | |
Added version output port. |
1.12. HDMI IP Core v16.0
Description | Impact |
---|---|
Added Audio Metadata Packet to comply to HDMI Specification Version 2.0. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added new interface ports:
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1.13. HDMI IP Core v15.1
Description | Impact |
---|---|
Added the following new GUI parameters:
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These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Updated the following interface ports:
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1.14. HDMI IP Core v15.0 Update 1
Description | Impact |
---|---|
Fixed the timing violation on the oversampling block in the Arria V HDMI 2.0 design. | Upgrade if you are using the Arria V HDMI 2.0 design. |
1.15. HDMI IP Core v15.0
Description | Impact |
---|---|
Upgraded support for HDMI specification compliance from version 1.4b to 2.0. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added 4 symbols per clock. | |
Added Status and Control Data Channel (SCDC) for HDMI specification version 2.0. | |
Added the following interface ports:
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1.16. HDMI IP Core v14.1
Description | Impact |
---|---|
Initial release. | - |
1.17. HDMI Intel FPGA IP User Guide Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to 19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
Intel® Quartus® Prime Version | IP Core Version | User Guide |
---|---|---|
20.2 | 19.4.0 | HDMI Intel FPGA IP User Guide |
20.1 | 19.4.0 | HDMI Intel FPGA IP User Guide |
19.4 | 19.3.0 | HDMI Intel FPGA IP User Guide |
19.3 | 19.1.0 | HDMI Intel FPGA IP User Guide |
19.1 | 19.1 | HDMI Intel FPGA IP User Guide |
18.1 | 18.1 | HDMI Intel FPGA IP User Guide |
18.0 | 18.0 | HDMI Intel FPGA IP User Guide |
17.1 | 17.1 | HDMI IP Core User Guide |
17.0 | 17.0 | HDMI IP Core User Guide |
16.1 | 16.1 | HDMI IP Core User Guide |
16.0 | 16.0 | HDMI IP Core User Guide |
15.1 | 15.1 | HDMI IP Core User Guide |
15.0 | 15.0 | HDMI IP Core User Guide |
14.1 | 14.1 | HDMI IP Core User Guide |
1.18. HDMI Intel Arria 10 FPGA IP Design Example User Guide Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to 19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
Intel® Quartus® Prime Version | IP Core Version | User Guide |
---|---|---|
20.1 | 19.4.0 | HDMI Intel Arria 10 FPGA IP Design Example User Guide |
19.4 | 19.3.0 | HDMI Intel Arria 10 FPGA IP Design Example User Guide |
18.1 | 18.1 | HDMI Intel Arria 10 FPGA IP Design Example User Guide |
17.1 | 17.1 | Intel HDMI IP Design Example User Guide for Intel Arria 10 Devices |
17.0 | 17.0 | Intel Arria 10 HDMI IP Core Design Example User Guide |
16.1 | 16.1 | HDMI IP Core Design Example User Guide |
1.19. HDMI Intel Cyclone 10 GX FPGA IP Design Example User Guide Archives
Intel® Quartus® Prime Version | IP Core Version | User Guide |
---|---|---|
18.1 | 18.1 | Intel FPGA HDMI Design Example User Guide for Intel® Cyclone® 10 GX Devices |
17.1.1 | 17.1.1 | Intel FPGA HDMI Design Example User Guide for Intel® Cyclone® 10 GX Devices |
1.20. HDMI Intel Stratix 10 FPGA IP Design Example User Guide Archives
Intel® Quartus® Prime Version | IP Core Version | User Guide |
---|---|---|
20.3 | 19.5.0 | HDMI Intel Stratix 10 FPGA IP Design Example User Guide |
20.2 | 19.4.0 | HDMI Intel Stratix 10 FPGA IP Design Example User Guide |
19.1 | 19.1 | HDMI Intel Stratix 10 FPGA IP Design Example User Guide |
18.0 | 18.0 | HDMI Intel Stratix 10 FPGA IP Design Example User Guide |