DisplayPort Intel FPGA IP Release Notes
1. DisplayPort Intel FPGA IP Release Notes
If a release note is not available for a specific IP version, the IP has no changes in that version. For information on IP update releases up to v18.1, refer to the Intel® Quartus® Prime Design Suite Update Release Notes.
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP version (X.Y.Z) number may change from one Intel Quartus Prime software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
1.1. DisplayPort Intel FPGA IP v19.3.0
| Intel® Quartus® Prime Version | Description | Impact |
|---|---|---|
| 20.2 |
Added support for High-bandwidth Digital Content Protection (HDCP) feature for Intel® Stratix® 10 devices. This feature has also been available for Intel® Arria® 10 devices since the Intel® Quartus® Prime Pro Edition software version 19.4 and later. |
The HDCP feature is not included in the Intel® Quartus® Prime Pro Edition software. To access the HDCP feature, contact Intel at https://www.intel.com/content/www/us/en/broadcast/products/programmable/applications/connectivity-solutions.html. |
| Intel® Quartus® Prime Version | Description | Impact |
|---|---|---|
| 20.1 |
Enabled speed grade 3 (conditional support) for Intel® Arria® 10 and Intel® Stratix® 10 devices. |
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
|
Enabled multi-stream transport support up to 4 streams for Intel® Cyclone® 10 GX devices. |
1.2. DisplayPort Intel FPGA IP v19.1
| Description | Impact |
|---|---|
|
Enabled final support for Intel® Stratix® 10 L-tile and H-tile devices. The design examples now target Intel Stratix 10 production devices. |
If you want to target your designs to use Intel® Stratix® 10 L-tile devices, you must upgrade your IP core. |
1.3. DisplayPort Intel FPGA IP v18.1 Update 1
18.1.1 December 2018
- For Intel® Stratix® 10 devices, enabled Pixel Clock Recovery function.
- Changed Synopsys Design Constraints to entity-based Synopsys Design Constraints.
- Cleaned up compilation warnings found in Intel® Stratix® 10 design example with pixel clock recovery.
- Enabled Intel® Stratix® 10 design example with Pixel Clock Recovery variant.
- Enabled initiation of Tx in software regardless of the setting of DP_SUPPORT_EDID_PASSTHRU.
- Fixed an Intel® Arria® 10 design example when no display output occurred in non GPU mode.
- Enabled extended receiver capabilities when the maximum link rate is HBR3.
- For Intel® Stratix® 10 H-tile devices, added VID_OPERATION_MODE "PMBUS MASTER" and PWRMGMT settings to the video connectivity design example IP .qsf file to enable Intel® Stratix® 10 SmartVID and power management capabilities.
1.4. DisplayPort Intel FPGA IP v18.1
| Description | Impact |
|---|---|
| Added a new design example for Intel® Stratix® 10 devices in version 18.1 release. Refer to the DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide for more information. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
| Updated the design examples for Intel® Arria® 10 devices to support multi-stream transport (MST). |
1.5. DisplayPort Intel FPGA IP v18.0
| Description | Impact |
|---|---|
| Renamed Intel FPGA DisplayPort IP to DisplayPort Intel® FPGA IP as part of standardizing and rebranding exercise. | – |
| Added support for Xcelium* Parallel simulator. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added the following files:
|
|
| Added final support for Intel® Cyclone® 10 GX devices. | The Intel® Cyclone® 10 GX devices are only available in the Intel® Quartus® Prime Pro Edition software. |
| Added new design examples for Intel® Cyclone® 10 GX devices in version 17.1.1 release. Refer to the DisplayPort Intel Cyclone 10 GX FPGA IP Design Example User Guide for more information. |
| Design Example | Required Files |
|---|---|
| Intel® Arria® 10 |
|
| Intel® Cyclone® 10 GX |
|
1.6. Intel FPGA DisplayPort IP Core v17.1
| Description | Impact |
|---|---|
Renamed the following as per Intel rebranding:
|
– |
| Added advance support for Intel® Cyclone® 10 GX devices. | The Intel® Cyclone® 10 GX devices are only available in the Intel® Quartus® Prime Pro Edition software. |
| YCbCr 4:2:0 color format is now supported. | These features are only available in the Intel® Quartus® Prime Pro Edition software. |
| The Intel FPGA DisplayPort IP core version 17.1 conforms to Video Electronics Standards Association (VESA) DisplayPort Standard version 1.4. | |
| Added data link rate support for HBR3 (8.10 Gbps). This
rate is only available in quad symbols per clock for
Intel®
Arria® 10 and
Intel®
Cyclone® 10 GX devices. Note: The clock recovery module in the
Intel®
Arria® 10 design examples only
support up to 4Kp60 resolution.
|
|
| Updated the design examples to DisplayPort SST Parallel Loopback With PCR and DisplayPort SST Parallel Loopback Without PCR. | |
|
In previous versions of the DisplayPort Intel® FPGA IP design example for Intel® Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in the Intel® Quartus® Prime software version 17.1. |
If you are upgrading designs that have these additional constraints from the previous versions of Intel® Quartus® Prime to version 17.1, you must revise the constraints. Refer to the KDB page for more information. |
1.7. DisplayPort IP Core v17.0
| Description | Impact |
|---|---|
| Available in both Quartus Prime Pro Edition and Quartus Prime Standard Edition. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Added support for the following features:
|
|
| Added a new parameter: TX Video IM Enable. Turn on to enable the video image interface. Turn off to use the traditional HSYNC/ VSYNC/DE video input interface. | |
| Multi-stream transport (MST) feature supports audio data channel. |
1.8. DisplayPort IP Core v16.1
| Description | Impact |
|---|---|
| The 16.1 version of the DisplayPort IP core is available only in Quartus Prime Standard Edition. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
|
Multi-stream transport (MST) feature does not support audio data channel. |
|
| Added support for multiple TX instances in software API. | |
| Added new Design Example tab in the DisplayPort IP core parameter editor. The design example is for Arria 10 devices. Refer to the DisplayPort IP Core Design Example User Guide for more information. |
1.9. DisplayPort IP Core v16.0
| Description | Impact |
|---|---|
| Removed the Import fixed MSA parameter and the txN_msa_conduit signal. The DisplayPort source core now automatically inserts the TX main stream attribute (MSA). | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
| Added support for black video feature for DisplayPort sink core. | |
| Added support for Link Quality Analysis (LQA). |
1.10. DisplayPort IP Core v15.1
| Description | Impact |
|---|---|
| The txN_vid_f pin is removed from the DisplayPort IP core. The IP core handles the interface internally. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Updated multi-stream support:
|
1.11. DisplayPort IP Core v15.0
| Description | Impact |
|---|---|
| Added preliminary support for Arria 10 devices. | These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
Updated color support.
|
|
| Added source-supported DPCD locations. | |
| Added new bits for DPTX_TEST_80BIT_PATTERN bits. | |
Removed the Link Quality Generation register bits and
combined these bits into the DPTX_TX_CONTROL register.
|
|
| Added new sink-supported DPCD location bits: TEST_REQUEST, TEST_LINK_RATE, TEST_LANE_COUNT, PHY_TEST_PATTERN, and TEST_80BIT_CUSTOM_PATTERN. | |
| Added simulation testbench for Arria 10 devices. |
1.12. DisplayPort IP Core v14.1
| Description | Impact |
|---|---|
Added multi-stream support (MST, 1 to
4 source and sink streams). You can access this feature using these
parameters:
|
These changes are optional. If you do not upgrade your IP core, it does not have these new features. |
| Added support for 4Kp60 resolution. | |
| Removed support for double reference clocks—162 MHz and 270 MHz—for transceiver clocking. | |
| Updated the design example with pixel clock recovery feature and 4Kp60 support. | |
| Added new signals. | |
Added new source registers:
|
|
Added new sink registers:
|
|
Changed the value of the following register bits:
|
| Old Signal Name | New Signal Name | Notes |
|---|---|---|
| — | clk_cal | Calibration clock for transceiver management interface |
| — | tx_link_rate_8bits | Main link rate expressed in multiples of 270Mbps |
| — | rx_link_rate_8bits | |
| — | txN_video_in (N=1,2,3) | TX signals for Stream 1, 2 and 3 |
| — | txN_vid_clk (N=1,2,3) | |
| — | txN_audio (N=1,2,3) | |
| — | txN_audio_clk (N=1,2,3) | |
| — | txN_ss (N=1,2,3) | |
| — | txN_msa_conduit (N=1,2,3) | |
| — | rxN_video_out (N=1,2,3) | RX signals for Stream 1, 2 and 3 |
| — | rxN_vid_clk (N=1,2,3) | |
| — | rxN_audio (N=1,2,3) | |
| — | rxN_ss (N=1,2,3) | |
| — | rxN_msa_conduit (N=1,2,3) | |
| — | rxN_stream (N=1,2,3) | |
| tx_xcvr_clkout | tx_ss_clk | — |
| rx_xcvr_clkout | rx_ss_clk | — |
1.13. DisplayPort Intel FPGA IP User Guide Archives
| Intel® Quartus® Prime Version | IP Core Version | User Guide |
|---|---|---|
| 20.1 | 19.3.0 | DisplayPort Intel FPGA IP User Guide |
| 19.4 | 19.2.0 | DisplayPort Intel FPGA IP User Guide |
| 19.1 | 19.1 | DisplayPort Intel FPGA IP User Guide |
| 18.1 | 18.1 | DisplayPort Intel FPGA IP User Guide |
| 18.0 | 18.0 | DisplayPort Intel FPGA IP User Guide |
| 17.1 | 17.1 | Intel FPGA DisplayPort IP Core User Guide |
| 17.0 | 17.0 | DisplayPort IP Core User Guide |
| 16.1 | 16.1 | DisplayPort IP Core User Guide |
| 16.0 | 16.0 | DisplayPort IP Core User Guide |
| 15.1 | 15.1 | DisplayPort IP Core User Guide |
| 15.0 | 15.0 | DisplayPort IP Core User Guide |
| 14.1 | 14.1 | DisplayPort IP Core User Guide |
1.14. DisplayPort Intel Arria 10 FPGA IP Design Example User Guide Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to 19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
| Intel® Quartus® Prime Version | IP Core Version | User Guide |
|---|---|---|
| 19.2 | 19.1.0 | DisplayPort Intel Arria 10 FPGA IP Design Example User Guide |
| 19.1 | 19.1 | DisplayPort Intel Arria 10 FPGA IP Design Example User Guide |
| 17.1 | 17.1 | Intel FPGA DisplayPort IP Core Design Example for Arria 10 Devices User Guide |
| 17.0 | 17.0 | Intel Arria 10 DisplayPort IP Core Design Example User Guide |
| 16.1 | 16.1 | DisplayPort IP Core Design Example User Guide |
1.15. DisplayPort Intel Cyclone 10 GX FPGA IP Design Example User Guide Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to 19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
| Intel® Quartus® Prime Version | IP Core Version | User Guide |
|---|---|---|
| 19.2 | 19.1.0 | DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide |
| 19.1 | 19.1 | DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide |
| 17.1.1 | 17.1.1 | Intel FPGA DisplayPort IP Core Design Example User Guide for Intel® Cyclone® 10 GX Devices |
1.16. DisplayPort Intel Stratix 10 FPGA IP Design Example User Guide Archives
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to 19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
| Intel® Quartus® Prime Version | IP Core Version | User Guide |
|---|---|---|
| 20.1 | 19.3.0 | DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide |
| 19.2 | 19.1.0 | DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide |
| 19.1 | 19.1 | DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide |
| 18.1 | 18.1 | DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide |