The following table lists a summary of the number of pins required for various example memory interfaces. This table uses series OCT with calibration and parallel OCT with calibration, or dynamic calibrated OCT, when applicable, shown by the usage of R_UP and R_DN pins or RZQ pin.

Intel^® devices do not limit the width of external memory interfaces beyond the following requirements:

• Maximum possible interface width in any particular device is limited by the number of DQS groups available.
• Sufficient clock networks are available to the interface PLL as required by the IP.
• Sufficient spare pins exist within the chosen bank or side of the device to include all other address and command, and clock pin placement requirements.
• The greater the number of banks, the greater the skew, hence Intel^® recommends that you always generate a test project of your desired configuration and confirm that it meets timing.

• t_DQSCK is the skew between the CK or CK# signals and the SDRAM-generated DQS signal
• t_DSH is the DQS falling edge from CK rising edge hold time
• t_DSS is the DQS falling edge from CK rising edge setup time
• t_DQSS is the positive DQS latching edge to CK rising edge

SDRAM have a write requirement (t_DQSS) that states the positive edge of the DQS signal on writes must be within ± 25% (± 90°) of the positive edge of the SDRAM clock input. Therefore, you should generate the CK and CK# signals using the DDR registers in the IOE to match with the DQS signal and reduce any variations across process, voltage, and temperature. The positive edge of the SDRAM clock, CK, is aligned with the DQS write to satisfy t_DQSS.

DDR3 SDRAM can use a daisy-chained control address command (CAC) topology, in which the memory clock must arrive at each chip at a different time. To compensate for the flight-time skew between devices when using the CAC topology, you should employ write leveling.

For DDR, DDR2, and DDR3, the CS#, RAS#, CAS#, WE#, CKE, and ODT pins are SDRAM command and control pins. For DDR3 SDRAM, certain topologies such as RDIMM and LRDIMM include RESET#, PAR_IN (1.5V LVCMOS I/O standard), and ERR_OUT# (SSTL-15 I/O standard).

The DDR2 SDRAM command and address inputs do not have a symmetrical setup and hold time requirement with respect to the SDRAM clocks, CK, and CK#.

Although DDR4 operates in fundamentally the same way as other SDRAM, there are no longer dedicated pins for RAS#, CAS#, and WE#, as those are now shared with higher-order address pins. DDR4 still has CS#, CKE, ODT, and RESET# pins, similar to DDR3. DDR4 introduces some additional pins, including the ACT# (activate) pin and BG (bank group) pins. Depending on the memory format and the functions enabled, the following pins might also exist in DDR4: PAR (address command parity) pin and the ALERT# pin.

For Intel^® SDRAM high-performance controllers in Stratix III and Stratix IV devices, the command and address clock is a dedicated PLL clock output whose phase can be adjusted to meet the setup and hold requirements of the memory clock. The command and address clock is also typically half-rate, although a full-rate implementation can also be created. The command and address pins use the DDIO output circuitry to launch commands from either the rising or falling edges of the clock. The chip select CS#, clock enable CKE, and ODT pins are only enabled for one memory clock cycle and can be launched from either the rising or falling edge of the command and address clock signal. The address and other command pins are enabled for two memory clock cycles and can also be launched from either the rising or falling edge of the command and address clock signal.

In Arria II GX devices, the command and address clock is either shared with the write_clk_2x or the mem_clk_2x clock.

Regardless of interface width, DDR SDRAM always operates in ×8 mode DQS groups. DQ pins in DDR2, DDR3, and DDR4 SDRAM interfaces can operate in either ×4 or ×8 mode DQS groups, depending on your chosen memory device or DIMM, regardless of interface width. The ×4 and ×8 configurations use one pair of bidirectional data strobe signals, DQS and DQSn, to capture input data. However, two pairs of data strobes, UDQS and UDQS# (upper byte) and LDQS and LDQS# (lower byte), are required by the ×16 configuration devices. A group of DQ pins must remain associated with its respective DQS and DQSn pins.

The DQ signals are edge-aligned with the DQS signal during a read from the memory and are center-aligned with the DQS signal during a write to the memory. The memory controller shifts the DQ signals by –90 degrees during a write operation to center align the DQ and DQS signals. The PHY IP delays the DQS signal during a read, so that the DQ and DQS signals are center aligned at the capture register. Intel^® devices use a phase-locked loop (PLL) to center-align the DQS signal with respect to the DQ signals during writes and Intel^® devices use dedicated DQS phase-shift circuitry to shift the incoming DQS signal during reads. The following figure shows an example where the DQS signal is shifted by 90 degrees for a read from the DDR2 SDRAM.

The following figure shows an example of the relationship between the data and data strobe during a burst-of-four write.

The memory device's setup (t_DS) and hold times (t_DH) for the DQ and DM pins during writes are relative to the edges of DQS write signals and not the CK or CK# clock. Setup and hold requirements are not necessarily balanced inDDR2 and DDR3 SDRAM, unlike in DDR SDRAM devices.

The DQS signal is generated on the positive edge of the system clock to meet the t_DQSS requirement. DQ and DM signals use a clock shifted –90 degrees from the system clock, so that the DQS edges are centered on the DQ or DM signals when they arrive at the DDR2 SDRAM. The DQS, DQ, and DM board trace lengths need to be tightly matched (within 20 ps).

The SDRAM uses the DM pins during a write operation. Driving the DM pins low shows that the write is valid. The memory masks the DQ signals if the DM pins are driven high. To generate the DM signal, Intel^® recommends that you use the spare DQ pin within the same DQS group as the respective data, to minimize skew.

The DM signal's timing requirements at the SDRAM input are identical to those for DQ data. The DDR registers, clocked by the –90 degree shifted clock, create the DM signals.

DDR4 supports DM similarly to other SDRAM, except that in DDR4 DM is active LOW and bidirectional, because it supports Data Bus Inversion (DBI) through the same pin. DM is multiplexed with DBI by a Mode Register setting whereby only one function can be enabled at a time. DBI is an input/output identifying whether to store/output the true or inverted data. When enabled, if DBI is LOW, during a write operation the data is inverted and stored inside the DDR4 SDRAM; during a read operation, the data is inverted and output. The data is not inverted if DBI is HIGH. For Arria 10, the DBI (for DDR4) and the DM (for DDR3) pins in each DQS group must be paired with a DQ pin for proper operation.

Some SDRAM modules support error correction coding (ECC) to allow the controller to detect and automatically correct error in data transmission. The 72-bit SDRAM modules contain eight extra data pins in addition to 64 data pins. The eight extra ECC pins should be connected to a single DQS or DQ group on the FPGA.

Compared to the unbuffered DIMMs (UDIMM), registered and load-reduced DIMMs (RDIMMs and LRDIMMs, respectively) use at least two chip-select signals CS#[1:0] in DDR3 and DDR4. Both RDIMMs and LRDIMMs require an additional parity signal for address, RAS#, CAS#, and WE# signals. A parity error signal is asserted by the module whenever a parity error is detected.

LRDIMMs expand on the operation of RDIMMs by buffering the DQ/DQS bus. Only one electrical load is presented to the controller regardless of the number of ranks, therefore only one clock enable (CKE) and ODT signal are required for LRDIMMs, regardless of the number of physical ranks. Because the number of physical ranks may exceed the number of physical chip-select signals, DDR3 LRDIMMs provide a feature known as rank multiplication, which aggregates two or four physical ranks into one larger logical rank. Refer to LRDIMM buffer documentation for details on rank multiplication.

The following table shows UDIMM and RDIMM pin options for DDR, DDR2, and DDR3.

DM[8:0]

DM[8:0]

DM[8:0]

DM[8:0]

The following table shows LRDIMM pin options for DDR3.

The following table shows UDIMM, RDIMM, and LRDIMM pin options for DDR4.

• Input clocks K and K#
• Echo clocks CQ and CQ#

In addition, QDR II devices have a third pair of input clocks, C and C#.

The positive input clock, K, is the logical complement of the negative input clock, K#. Similarly, C and CQ are complements of C# and CQ#, respectively. With these complementary clocks, the rising edges of each clock leg latch the DDR data.

The QDR II SRAM devices use the K and K# clocks for write access and the C and C# clocks for read accesses only when interfacing more than one QDR II SRAM device. Because the number of loads that the K and K# clocks drive affects the switching times of these outputs when a controller drives a single QDR II SRAM device, C and C# are unnecessary. This is because the propagation delays from the controller to the QDR II SRAM device and back are the same. Therefore, to reduce the number of loads on the clock traces, QDR II SRAM devices have a single-clock mode, and the K and K# clocks are used for both reads and writes. In this mode, the C and C# clocks are tied to the supply voltage (VDD). Intel^® FPGA external memory IP supports only single-clock mode.

For QDR II, QDR II+, or QDR II+ Xtreme SRAM devices, the rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0], in similar fashion to QDR II SRAM devices in single clock mode. All accesses are initiated on the rising edge of K .

CQ and CQ# are the source-synchronous output clocks from the QDR II, QDR II+, or QDR II+ Xtreme SRAM device that accompanies the read data.

The Intel^® device outputs the K and K# clocks, data, address, and command lines to the QDR II, QDR II+, or QDR II+ Xtreme SRAM device. For the controller to operate properly, the write data (D), address (A), and control signal trace lengths (and therefore the propagation times) should be equal to the K and K# clock trace lengths.

You can generate K and K# clocks using any of the PLL registers via the DDR registers. Because of strict skew requirements between K and K# signals, use adjacent pins to generate the clock pair. The propagation delays for K and K# from the FPGA to the QDR II, QDR II+, or QDR II+ Xtreme SRAM device are equal to the delays on the data and address (D, A) signals. Therefore, the signal skew effect on the write and read request operations is minimized by using identical DDR output circuits to generate clock and data inputs to the memory.

At the pin, the read data is edge-aligned with the CQ and CQ# clocks while the write data is center-aligned with the K and K# clocks (see the following figures).

The byte write select signal (BWS#) indicates which byte to write into the memory device.

QDR II+ and QDR II+ Xtreme SRAM devices also have a QVLD pin that indicates valid read data. The QVLD signal is edge-aligned with the echo clock and is asserted high for approximately half a clock cycle before data is output from memory.

The three QDR IV differential clocks are as follows:

• Address and Command Input Clocks CK and CK#
• Data Input Clocks DKx and DKx#, where x can be A or B, referring to the respective ports
• Data Output Clocks, QKx and QKx#, where x can be A or B, referring to the respective ports

QDR IV SRAM devices have two independent bidirectional data ports, Port A and Port B, to support concurrent read/write transactions on both ports. These data ports are controlled by a common address port clocked by CK and CK# in double data rate. There is one pair of CK and CK# pins per QDR IV SRAM device.

DKx and DKx# samples the DQx inputs on both rising and falling edges. Similarly, QKx and QKx# samples the DQx outputs on both rising and falling edges.

QDR IV SRAM devices employ two sets of free running differential clocks to accompany the data. The DKx and DKx# clocks are the differential input data clocks used during writes. The QKx and QKx# clocks are the output data clocks used during reads. Each pair of DKx and DKx#, or QKx and QKx# clocks are associated with either 9 or 18 data bits.

The polarity of the QKB and QKB# pins in the Intel^® FPGA external memory interface IP was swapped with respect to the polarity of the differential input buffer on the FPGA. In other words, the QKB pins on the memory side must be connected to the negative pins of the input buffers on the FPGA side, and the QKB# pins on the memory side must be connected to the positive pins of the input buffers on the FPGA side. Notice that the port names at the top-level of the IP already reflect this swap (that is, mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive buffer leg).

QDR IV SRAM devices are available in x18 and x36 bus width configurations. The exact clock-data relationships are as follows:

• For ×18 data bus width configuration, there are 9 data bits associated with each pair of write and read clocks. So, there are two pairs of DKx and DKx# pins and two pairs of QKx or QKx# pins.
• For ×36 data bus width configuration, there are 18 data bits associated with each pair of write and read clocks. So, there are two pairs of DKx and DKx# pins and two pairs of QKx or QKx# pins.

There are tCKDK timing requirements for skew between CK and DKx or CK# and DKx# .Similarly, there are tCKQK timing requirements for skew between CK and QKx or CK# and QKx# .

QDR IV SRAM devices have the ability to invert all address pins to reduce potential simultaneous switching noise. Such inversion is accomplished using the Address Inversion Pin for Address and Address Parity Inputs (AINV), which assumes an address parity of 0, and indicates whether the address bus and address parity are inverted.

The above features are available as Option Control under Configuration Register Settings in Arria 10 EMIF IP. The commands and addresses must meet the memory address and command setup (tAS, tCS) and hold (tAH, tCH) time requirements.

The polarity of the QKB and QKB# pins in the Intel^® FPGA external memory interface IP was swapped with respect to the polarity of the differential input buffer on the FPGA. In other words, the QKB pins on the memory side need to be connected to the negative pins of the input buffers on the FPGA side, and the QKB# pins on the memory side need to be connected to the positive pins of the input buffers on the FPGA side. Notice that the port names at the top-level of the IP already reflect this swap (that is, mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive buffer leg).

The synchronous read/write input, RWx#, is used in conjunction with the synchronous load input, LDx#, to indicate a Read or Write Operation. For port A, these signals are sampled on the rising edge of CK clock, for port B, these signals are sampled on the falling edge of CK clock.

QDR IV SRAM devices have the ability to invert all data pins to reduce potential simultaneous switching noise, using the Data Inversion Pin for DQ Data Bus, DINVx. This pin indicates whether DQx pins are inverted or not.

To enable the data pin inversion feature, click Configuration Register Settings > Option Control in the Arria 10 or Stratix 10 EMIF IP.

QDR IV SRAM devices also have a QVLD pin which indicates valid read data. The QVLD signal is edge-aligned with QKx or QKx# and is high approximately one-half clock cycle before data is output from the memory.

Instead of a strobe, RLDRAM II and RLDRAM 3 devices use two sets of free-running differential clocks to accompany the data. The DK and DK# clocks are the differential input data clocks used during writes while the QK or QK# clocks are the output data clocks used during reads. Even though QK and QK# signals are not differential signals according to the RLDRAM II and RLDRAM 3 data sheets, Micron treats these signals as such for their testing and characterization. Each pair of DK and DK#, or QK and QK# clocks are associated with either 9 or 18 data bits.

The exact clock-data relationships are as follows:

• RLDRAM II: For ×36 data bus width configuration, there are 18 data bits associated with each pair of write and read clocks. So, there are two pairs of DK and DK# pins and two pairs of QK or QK# pins.
• RLDRAM 3: For ×36 data bus width configuration, there are 18 data bits associated with each pair of write clocks. There are 9 data bits associated with each pair of read clocks. So, there are two pairs of DK and DK# pins and four pairs of QK and QK# pins.
• RLDRAM II: For ×18 data bus width configuration, there are 18 data bits per one pair of write clocks and nine data bits per one pair of read clocks. So, there is one pair of DK and DK# pins, but there are two pairs of QK and QK# pins.
• RLDRAM 3: For ×18 data bus width configuration, there are 9 data bits per one pair of write clocks and nine data bits per one pair of read clocks. So, there are two pairs of DK and DK# pins, and two pairs of QK and QK# pins
• RLDRAM II: For ×9 data bus width configuration, there are nine data bits associated with each pair of write and read clocks. So, there is one pair of DK and DK# pins and one pair of QK and QK# pins each.
• RLDRAM 3: RLDRAM 3 does not have the ×9 data bus width configuration.

There are t_CKDK timing requirements for skew between CK and DK or CK# and DK#.

For both RLDRAM II and RLDRAM 3, because of the loads on these I/O pins, the maximum frequency you can achieve depends on the number of memory devices you are connecting to the Intel^® device. Perform SPICE or IBIS simulations to analyze the loading effects of the pin‑pair on multiple RLDRAM II or RLDRAM 3 devices.

These pins operate at single data rate using only one clock edge. RLDRAM II and RLDRAM 3 support both non-multiplexed and multiplexed addressing. Multiplexed addressing allows you to save a few user I/O pins while non‑multiplexed addressing allows you to send the address signal within one clock cycle instead of two clock cycles. CS#, REF#, and WE# pins are input commands to the RLDRAM II or RLDRAM 3 device.

The commands and addresses must meet the memory address and command setup (t_AS, t_CS) and hold (t_AH, t_CH) time requirements.

Intel^® devices use dedicated DQS phase-shift circuitry to shift the incoming QK signal during reads and use a PLL to center-align the DK and DK# signals with respect to the DQ signals during writes.

For RLDRAM II and RLDRAM 3, data mask (DM) pins are used only during a write. The memory controller drives the DM signal low when the write is valid and drives it high to mask the DQ signals.

For RLDRAM II, there is one DM pin per memory device. The DQ input signal is masked when the DM signal is high.

For RLDRAM 3, there are two DM pins per memory device. DM0 is used to mask the lower byte for the x18 device and (DQ[8:0],DQ[26:18]) for the x36 device. DM1 is used to mask the upper byte for the x18 device and (DQ[17:9], DQ[35:27]) for the x36 device.

The DM timing requirements at the input to the memory device are identical to those for DQ data. The DDR registers, clocked by the write clock, create the DM signals. This reduces any skew between the DQ and DM signals.

The RLDRAM II or RLDRAM 3 device's setup time (t_DS) and hold (t_DH) time for the write DQ and DM pins are relative to the edges of the DK or DK# clocks. The DK and DK# signals are generated on the positive edge of system clock, so that the positive edge of CK or CK# is aligned with the positive edge of DK or DK# respectively to meet the tCKDK requirement. The DQ and DM signals are clocked using a shifted clock so that the edges of DK or DK# are center-aligned with respect to the DQ and DM signals when they arrive at the RLDRAM II or RLDRAM 3 device.

The clocks, data, and DM board trace lengths should be tightly matched to minimize the skew in the arrival time of these signals.

RLDRAM II and RLDRAM 3 devices also have a QVLD pin indicating valid read data. The QVLD signal is edge-aligned with QK or QK# and is high approximately half a clock cycle before data is output from the memory.

The clock is defined as the differential pair which consists of CK and CKn. The positive clock edge is defined by the cross point of a rising CK and a falling CKn. The negative clock edge is defined by the cross point of a falling CK and a rising CKn.

The SDRAM data sheet specifies timing data for the following:

• t_DSH is the DQS falling edge hold time from CK.
• t_DSS is the DQS falling edge to the CK setup time.
• t_DQSS is the Write command to the first DQS latching transition.
• t_DQSCK is the DQS output access time from CK/CKn.

Differential DQS operation enables improved system timing due to reduced crosstalk and less simultaneous switching noise on the strobe output drivers. The DQ pins are also bidirectional. DQS is edge-aligned with the read data and centered with the write data.

DM is the input mask for the write data signal. Input data is masked when DM is sampled high coincident with that input data during a write access.

Unless otherwise noted, the calculation for the maximum number of interfaces is based on independent interfaces where the address or command pins are not shared. The maximum number of independent interfaces is limited to the number of PLLs each FPGA device has.

For interface information for Arria 10 and Stratix 10 devices, you can consult the EMIF Device Selector on www.altera.com.

Timing closure depends on device resource and routing utilization. For more information about timing closure, refer to the Area and Timing Optimization Techniques chapter in the Quartus Prime Handbook.

Each interface of size n, where n is a multiple of 8, consists of:

• n DQ pins (including error correction coding (ECC))
• n/8 DM pins
• n/8 DQS pins
• 18 address pins
• 6 command pins (CAS#, RAS#, WE#, CKE, and CS#)
• 1 CK, CK# pin pair for up to every three ×8 DDR SDRAM components

Each interface of size n, where n is a multiple of 8, consists of:

• n DQ pins (including ECC)
• n/8 DM pins
• n/8 DQS, DQSn pin pairs
• 18 address pins
• 7 command pins (CAS#, RAS#, WE#, CKE, ODT, and CS#)
• 1 CK, CK# pin pair up to every three ×8 DDR2 components

Each interface of size n, where n is a multiple of 8, consists of:

• n DQ pins (including ECC)
• n/8 DM pins
• n/8 DQS, DQSn pin pairs
• 17 address pins
• 7 command pins (CAS#, RAS#, WE#, CKE, ODT, reset, and CS#)
• 1 CK, CK# pin pair

One interface of ×36 consists of:

• 36 Q pins
• 36 D pins
• 1 K, K# pin pairs
• 1 CQ, CQ# pin pairs
• 19 address pins
• 4 BSWn pins
• WPSn, RPSn

One interface of ×9 consists of:

• 9 Q pins
• 9 D pins
• 1 K, K# pin pairs
• 1 CQ, CQ# pin pairs
• 21 address pins
• 1 BWSn pin
• WPSn, RPSn

One common I/O ×36 interface consists of:

• 36 DQ
• 1 DM pin
• 2 DK, DK# pin pairs
• 2 QK, QK# pin pairs
• 1 CK, CK# pin pair
• 24 address pins
• 1 CS# pin
• 1 REF# pin
• 1 WE# pin

One common I/O ×9 interface consists of:

• 9 DQ
• 1 DM pins
• 1 DK, DK# pin pair
• 1 QK, QK# pin pair
• 1 CK, CK# pin pair
• 25 address pins
• 1 CS# pin
• 1 REF# pin
• 1 WE# pin

Each interface of size n, where n is a multiple of 8, consists of:

• n DQ pins (including ECC)
• n/8 DM pins
• n/8 DQS, DQSn pin pairs
• 10 address pins
• 2 command pins (CKE and CSn)
• 1 CK, CK# pin pair up to every three x8 LPDDR2 components

The I/O column, I/O bank, I/O lane, adjacent I/O bank, and pairing pin for every physical I/O pin can be uniquely identified using the Bank Number and Index within I/O Bank values which are defined in each Arria 10 device pin-out file.

• The numeric component of the Bank Number value identifies the I/O column, while the letter represents the I/O bank.
• The Index within I/O Bank value falls within one of the following ranges: 0 to 11, 12 to 23, 24 to 35, or 36 to 47, and represents I/O lanes 1, 2, 3, and 4, respectively.
• The adjacent I/O bank is defined as the I/O bank with same column number but the letter is either before or after the respective I/O bank letter in the A-Z system.
• The pairing pin for an I/O pin is located in the same I/O bank. You can identify the pairing pin by adding one to its Index within I/O Bank number (if it is an even number), or by subtracting one from its Index within I/O Bank number (if it is an odd number).

For example, a physical pin with a Bank Number of 2K and Index within I/O Bank of 22, indicates that the pin resides in I/O lane 2, in I/O bank 2K, in column 2. The adjacent I/O banks are 2J and 2L. The pairing pin for this physical pin is the pin with an Index within I/O Bank of 23 and Bank Number of 2K.

If you are using the Altera hard memory controller, you should employ the relative pin locations defined in the <variation_name>/altera_emif_arch_nf_version number/<synth|sim>/<variation_name>_altera_emif_arch_nf_version number_<unique ID>_readme.txt file, which is generated with your IP.

Observe the following general guidelines for placing pins for your Arria 10 external memory interface:

1. Ensure that the pins of a single external memory interface reside within a single I/O column.
2. An external memory interface can occupy one or more banks in the same I/O column. When an interface must occupy multiple banks, ensure that those banks are adjacent to one another.
3. Be aware that any pin in the same bank that is not used by an external memory interface is available for use as a general purpose I/O of compatible voltage and termination settings.
4. All address and command pins and their associated clock pins (CK and CK#) must reside within a single bank. The bank containing the address and command pins is identified as the address and command bank.
5. To minimize latency, when the interface uses more than two banks, you must select the center bank of the interface as the address and command bank.
6. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the Arria 10 External Memory Interface Pin Information File, which is available on www.altera.com.

   You do not have to place every address and command pin manually. If you assign the location for one address and command pin, the Fitter automatically places the remaining address and command pins.

   Note: The pin-out scheme is a hardware requirement that you must follow, and can vary according to the topology of the memory device. Some schemes require three lanes to implement address and command pins, while others require four lanes. To determine which scheme to follow, refer to the messages window during parameterization of your IP, or to the <variation_name>/altera_emif_arch_nf_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nf_<version>_<unique ID>_readme.txt file after you have generated your IP.
7. An unused I/O lane in the address and command bank can serve to implement a data group, such as a x8 DQS group. The data group must be from the same controller as the address and command signals.
8. An I/O lane must not be used by both address and command pins and data pins.
9. Place read data groups according to the DQS grouping in the pin table and pin planner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQ and CQ# / QK and QK#) must reside at physical pins capable of functioning as DQS/CQ and DQSn/CQn for a specific read data group size. You must place the associated read data pins (such as DQ and Q), within the same group.
   Note:

   1. Unlike other device families, there is no need to swap CQ/CQ# pins in certain QDR II and QDR II+ latency configurations.
   2. QDR-IV requires that the polarity of all QKB/QKB# pins be swapped with respect to the polarity of the differential buffer inputs on the FPGA to ensure correct data capture on port B. All QKB pins on the memory device must be connected to the negative pins of the input buffers on the FPGA side, and all QKB# pins on the memory device must be connected to the positive pins of the input buffers on the FPGA side. Notice that the port names at the top-level of the IP already reflect this swap (that is, mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive buffer leg).
10. You can use a single I/O lane to implement two x4 DQS groups. The pin table specifies which pins within an I/O lane can be used for the two pairs of DQS and DQS# signals. In addition, for x4 DQS groups you must observe the following rules:
    • There must be an even number of x4 groups in an external memory interface.
    • DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly, DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS group X and DQS group X+1 must be in the same I/O lane, where X is an even number.
11. You should place the write data groups according to the DQS grouping in the pin table and pin planner. Output-only data clocks for QDR II, QDR II+, and QDR II+ Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, but must be placed on a differential pin pair. They must be placed in the same I/O bank as the corresponding DQS group.
    Note:

    For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.

12. For protocols and topologies with bidirectional data pins where a write data group consists of multiple read data groups, you should place the data groups and their respective write and read clock in the same bank to improve I/O timing.

    You do not need to specify the location of every data pin manually. If you assign the location for the read capture strobe/clock pin pairs, the Fitter will automatically place the remaining data pins.

13. Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/O pin and another in the pairing pin for that I/O pin. It is recommended—though not required—that you follow the same rule for DBI pins, so that at a later date you have the freedom to repurpose the pin as DM.

Multiple Interfaces in the Same I/O Column

To place multiple interfaces in the same I/O column, you must ensure that the global reset signals (global_reset_n) for each individual interface all come from the same input pin or signal.

I/O Banks Selection

• For each memory interface, select consecutive I/O banks.
• A memory interface can only span across I/O banks in the same I/O column.
• Because I/O bank 2A is also employed for configuration-related operations, you can use it to construct external memory interfaces only when the following conditions are met:
  • The pins required for configuration related use (such as configuration bus for Fast Passive Parallel mode or control signals for Partial Reconfiguration) are never shared with pins selected for EMIF use, even after configuration is complete.
  • The I/O voltages are compatible.
  • The design has achieved a successful fit in the Quartus Prime software.

  Refer to the Arria 10 Device Handbook and the Configuration Function column of the Pin-Out files for more information about pins and configuration modes.

• The number of I/O banks that you require depends on the memory interface width.
• The 3V I/O bank does not support dynamic OCT or calibrated OCT. To place a memory interface in a 3V I/O bank, ensure that calibrated OCT is disabled for the address/command signals, the memory clock signals, and the data bus signals, during IP generation.
• In some device packages, the number of I/O pins in some LVDS I/O banks is less that 48 pins.

Address/Command Pins Location

• All address/command pins for a controller must be in a single I/O bank.
• If your interface uses multiple I/O banks, the address/command pins must use the middle bank. If the number of banks used by the interface is even, any of the two middle I/O banks can be used for address/command pins.
• Address/command pins and data pins cannot share an I/O lane but can share an I/O bank.
• The address/command pin locations for the soft and hard memory controllers are predefined. In the External Memory Interface Pin Information for Devices spreadsheet, each index in the "Index within I/O bank" column denotes a dedicated address/command pin function for a given protocol. The index number of the pin specifies to which I/O lane the pin belongs:
  • I/O lane 0—Pins with index 0 to 11
  • I/O lane 1—Pins with index 12 to 23
  • I/O lane 2—Pins with index 24 to 35
  • I/O lane 3—Pins with index 36 to 47
• For memory topologies and protocols that require only three I/O lanes for the address/command pins, use I/O lanes 0, 1, and 2.
• Unused address/command pins in an I/O lane can be used as general-purpose I/O pins.

CK Pins Assignment

Assign the clock pin (CK pin) according to the number of I/O banks in an interface:

• The number of I/O banks is odd—assign one CK pin to the middle I/O bank.
• The number of I/O banks is even—assign the CK pin to any one of the middle two I/O banks.

Although the Fitter can automatically select the required I/O banks, Intel^® recommends that you make the selection manually to reduce the pre-fit run time.

PLL Reference Clock Pin Placement

Place the PLL reference clock pin in the address/command bank. Other I/O banks may not have free pins that you can use as the PLL reference clock pin:

• If you are sharing the PLL reference clock pin between several interfaces, the I/O banks must be consecutive.

The Arria 10 External Memory Interface IP does not support PLL cascading.

RZQ Pin Placement

You may place the RZQ pin in any I/O bank in an I/O column with the correct VCCIO and VCCPT for the memory interface I/O standard in use. The recommended location is in the address/command I/O bank.

DQ and DQS Pins Assignment

Intel^® recommends that you assign the DQS pins to the remaining I/O lanes in the I/O banks as required:

• Constrain the DQ and DQS signals of the same DQS group to the same I/O lane.
• DQ signals from two different DQS groups cannot be constrained to the same I/O lane.

If you do not specify the DQS pins assignment, the Fitter will automatically select the DQS pins.

Sharing an I/O Bank Across Multiple Interfaces

If you are sharing an I/O bank across multiple external memory interfaces, follow these guidelines:

• The interfaces must use the same protocol, voltage, data rate, frequency, and PLL reference clock.
• You cannot use an I/O bank as the address/command bank for more than one interface. The memory controller and sequencer cannot be shared.
• You cannot share an I/O lane. There is only one DQS input per I/O lane, and an I/O lane can only connect to one memory controller.

Ping Pong PHY Implementation

The Ping Pong PHY feature instantiates two hard memory controllers—one for the primary interface and one for the secondary interface. The hard memory controller I/O bank of the primary interface is used for address and command and is always adjacent and above the hard memory controller I/O bank of the secondary interface. All four lanes of the primary hard memory controller I/O bank are used for address and command.

When you use Ping Pong PHY, the EMIF IP exposes two independent Avalon-MM interfaces to user logic; these interfaces correspond to the two hard memory controllers inside the interface. Each Avalon-MM interface has its own set of clock and reset signals. Refer to Qsys Interfaces for more information on the additional signals exposed by Ping Pong PHY interfaces.

For more information on Ping Pong PHY in Arria 10, refer to Functional Description—Arria 10 EMIF, in this handbook. For pin allocation information for Arria 10 devices, refer to External Memory Interface Pin Information for Arria 10 Devices on www.altera.com.

Additional Requirements for DDR3 and DDR4 Ping-Pong PHY Interfaces

If you are using Ping Pong PHY with a DDR3 or DDR4 external memory interface on an Arria 10 device, follow these guidelines:

• The address and command I/O bank must not contain any DQS group.
• I/O banks that are above the address and command I/O bank must contain only data pins of the primary interface—that is, the interface with the lower DQS group indices.
• The I/O bank immediately below the address and command I/O bank must contain at least one DQS group of the secondary interface—that is, the interface with the higher DQS group indices. This I/O bank can, but is not required to, contain DQS groups of the primary interface.
• I/O banks that are two or more banks below the address and command I/O bank must contain only data pins of the secondary interface.

Multiple Interfaces in the Same I/O Column

To place multiple interfaces in the same I/O column, you must ensure that the global reset signals (global_reset_n) for each individual interface all come from the same input pin or signal.

PLL Reference Clock Pin

To conserve pin usage and enable core clock network and I/O bank sharing, you can share a PLL reference clock pin between multiple external memory interfaces. Sharing of a PLL reference clock pin also implies sharing of the reference clock network.

Observe the following guidelines for sharing the PLL reference clock pin:

1. To share a PLL reference clock pin, connect the same signal to the pll_ref_clk port of multiple external memory interfaces in the RTL code.
2. Place related external memory interfaces in the same I/O column.
3. Place related external memory interfaces in adjacent I/O banks. If you leave an unused I/O bank between the I/O banks used by the external memory interfaces, that I/O bank cannot be used by any other external memory interface with a different PLL reference clock signal.

Core Clock Network

To access all external memory interfaces synchronously and to reduce global clock network usage, you may share the same core clock network with other external memory interfaces.

Observe the following guidelines for sharing the core clock network:

1. To share a core clock network, connect the clks_sharing_master_out of the master to the clks_sharing_slave_in of all slaves in the RTL code.
2. Place related external memory interfaces in the same I/O column.
3. Related external memory interface must have the same rate, memory clock frequency, and PLL reference clock.
4. If you are sharing core clocks between a Ping Pong PHY and a hard controller that have the same protocol, rate, and frequency, the Ping Pong PHY must be the core clock master.

I/O Bank

To reduce I/O bank utilization, you may share an I/O Bank with other external memory interfaces.

Observe the following guidelines for sharing an I/O Bank:

1. Related external memory interfaces must have the same protocol, rate, memory clock frequency, and PLL reference clock.
2. You cannot use a given I/O bank as the address and command bank for more than one external memory interface.
3. You cannot share an I/O lane between external memory interfaces, but an unused pin can serve as a general purpose I/O pin, of compatible voltage and termination standards.

Hard Nios Processor

All external memory interfaces residing in the same I/O column will share the same hard Nios processor. The shared hard Nios processor calibrates the external memory interfaces serially.

Reset Signal

When multiple external memory interfaces occupy the same I/O column, they must share the same IP reset signal.

The I/O column, I/O bank, I/O lane, adjacent I/O bank, and pairing pin for every physical I/O pin can be uniquely identified by the Bank Number and Index within I/O Bank values, which are defined in each Stratix 10 device pin-out file.

• The numeric component of the Bank Number value identifies the I/O column, while the letter represents the I/O bank.
• The Index within I/O Bank value falls within one of the following ranges: 0 to 11, 12 to 23, 24 to 35, or 36 to 47, and represents I/O lanes 1, 2, 3, and 4, respectively.
• The adjacent I/O bank is defined as the I/O bank with same column number but the letter is either before or after the respective I/O bank letter in the A-Z system.
• The pairing pin for an I/O pin is located in the same I/O bank. You can identify the pairing pin by adding one to its Index within I/O Bank number (if it is an even number), or by subtracting one from its Index within I/O Bank number (if it is an odd number).

  For example, a physical pin with a Bank Number of 2M and Index within I/O Bank of 22, indicates that the pin resides in I/O lane 2, in I/O bank 2M, in column 2. The adjacent I/O banks are 2L and 2N. The pairing pin for this physical pin is the pin with an Index within I/O Bank of 23 and Bank Number of 2M

  .

If you are using the hard memory controller, you should employ the relative pin locations defined in the <variation_name>/altera_emif_arch_nd_version number/<synth|sim>/<variation_name>_altera_emif_arch_nd_version number_<unique ID>_readme.txt file, which is generated with your IP.

Observe the following guidelines when placing pins for your Stratix 10 external memory interface:

1. Ensure that the pins of a single external memory interface reside within a single I/O column.
2. An external memory interface can occupy one or more banks in the same I/O column. When an interface must occupy multiple banks, ensure that those banks are adjacent to one another. (That is, the banks must contain the same column number and letter before or after the respective I/O bank letter.)
3. Be aware that any pin in the same bank that is not used by an external memory interface is available for use as a general purpose I/O of compatible voltage and termination settings.
4. All address and command pins and their associated clock pins (CK and CK#) must reside within a single bank. The bank containing the address and command pins is identified as the address and command bank.
5. To minimize latency, when the interface uses more than two banks, you must select the center bank of the interface as the address and command bank.
6. The address and command pins and their associated clock pins in the address and command bank must follow a fixed pin-out scheme, as defined in the Stratix 10 External Memory Interface Pin Information File, which is available on www.altera.com.

   You do not have to place every address and command pin manually. If you assign the location for one address and command pin, the Fitter automatically places the remaining address and command pins.

   Note: The pin-out scheme is a hardware requirement that you must follow, and can vary according to the topology of the memory device. Some schemes require three lanes to implement address and command pins, while others require four lanes. To determine which scheme to follow, refer to the messages window during parameterization of your IP, or to the <variation_name>/altera_emif_arch_nd_<version>/<synth|sim>/<variation_name>_altera_emif_arch_nd_<version>_<unique ID>_readme.txt file after you have generated your IP.
7. An unused I/O lane in the address and command bank can serve to implement a data group, such as a x8 DQS group. The data group must be from the same controller as the address and command signals.
8. An I/O lane must not be used by both address and command pins and data pins.
9. Place read data groups according to the DQS grouping in the pin table and Pin Planner. Read data strobes (such as DQS and DQS#) or read clocks (such as CQ and CQ# / QK and QK#) must reside at physical pins capable of functioning as DQS/CQ and DQSn/CQn for a specific read data group size. You must place the associated read data pins (such as DQ and Q), within the same group.
   Note:

   1. Unlike other device families, there is no need to swap CQ/CQ# pins in certain QDR II and QDR II+ latency configurations.
   2. QDR-IV requires that the polarity of all QKB/QKB# pins be swapped with respect to the polarity of the differential buffer inputs on the FPGA to ensure correct data capture on port B. All QKB pins on the memory device must be connected to the negative pins of the input buffers on the FPGA side, and all QKB# pins on the memory device must be connected to the positive pins of the input buffers on the FPGA side. Notice that the port names at the top-level of the IP already reflect this swap (that is, mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive buffer leg).
10. You can implement two x4 DQS groups with a single I/O lane. The pin table specifies which pins within an I/O lane can be used for the two pairs of DQS and DQS# signals. In addition, for x4 DQS groups you must observe the following rules:
    • There must be an even number of x4 groups in an external memory interface.
    • DQS group 0 and DQS group 1 must be placed in the same I/O lane. Similarly, DQS group 2 and group 3 must be in the same I/O lane. Generally, DQS group X and DQS group X+1 must be in the same I/O lane, where X is an even number.
11. You should place the write data groups according to the DQS grouping in the pin table and pin planner. Output-only data clocks for QDR II, QDR II+, and QDR II+ Extreme, and RLDRAM 3 protocols need not be placed on DQS/DQSn pins, but must be placed on a differential pin pair. They must be placed in the same I/O bank as the corresponding DQS group.
    Note: For RLDRAM 3, x36 device, DQ[8:0] and DQ[26:18] are referenced to DK0/DK0#, and DQ[17:9] and DQ[35:27] are referenced to DK1/DK1#.
12. For protocols and topologies with bidirectional data pins where a write data group consists of multiple read data groups, you should place the data groups and their respective write and read clock in the same bank to improve I/O timing.

    You do not need to specify the location of every data pin manually. If you assign the location for the read capture strobe/clock pin pairs, the Fitter will automatically place the remaining data pins.

13. Ensure that DM/BWS pins are paired with a write data pin by placing one in an I/O pin and another in the pairing pin for that I/O pin. It is recommended—though not required—that you follow the same rule for DBI pins, so that at a later date you have the freedom to repurpose the pin as DM.

Multiple Interfaces in the Same I/O Column

To place multiple interfaces in the same I/O column, you must ensure that the global reset signals (global_reset_n) for each individual interface all come from the same input pin or signal.

I/O Banks Selection

• For each memory interface, select adjacent I/O banks. (That is, select banks that contain the same column number and letter before or after the respective I/O bank letter.)
• A memory interface can only span across I/O banks in the same I/O column.
• The number of I/O banks that you require depends on the memory interface width.
• In some device packages, the number of I/O pins in some LVDS I/O banks is less that 48 pins.

Address/Command Pins Location

• All address/command pins for a controller must be in a single I/O bank.
• If your interface uses multiple I/O banks, the address/command pins must use the middle bank. If the number of banks used by the interface is even, any of the two middle I/O banks can be used for address/command pins.
• Address/command pins and data pins cannot share an I/O lane but can share an I/O bank.
• The address/command pin locations for the soft and hard memory controllers are predefined. In the External Memory Interface Pin Information for Devices spreadsheet, each index in the "Index within I/O bank" column denotes a dedicated address/command pin function for a given protocol. The index number of the pin specifies to which I/O lane the pin belongs:
  • I/O lane 0—Pins with index 0 to 11
  • I/O lane 1—Pins with index 12 to 23
  • I/O lane 2—Pins with index 24 to 35
  • I/O lane 3—Pins with index 36 to 47
• For memory topologies and protocols that require only three I/O lanes for the address/command pins, use I/O lanes 0, 1, and 2.
• Unused address/command pins in an I/O lane can serve as general-purpose I/O pins.

CK Pins Assignment

Assign the clock pin (CK pin) according to the number of I/O banks in an interface:

• The number of I/O banks is odd—assign one CK pin to the middle I/O bank.
• The number of I/O banks is even—assign the CK pin to any one of the middle two I/O banks.

Although the Fitter can automatically select the required I/O banks, Intel recommends that you make the selection manually to reduce the pre-fit run time.

PLL Reference Clock Pin Placement

Place the PLL reference clock pin in the address/command bank. Other I/O banks may not have free pins that you can use as the PLL reference clock pin:

• If you are sharing the PLL reference clock pin between several interfaces, the I/O banks must be adjacent. (That is, the banks must contain the same column number and letter before or after the respective I/O bank letter.)

The Stratix 10 External Memory Interface IP does not support PLL cascading.

RZQ Pin Placement

You may place the RZQ pin in any I/O bank in an I/O column with the correct V_CCIO and V_CCPT for the memory interface I/O standard in use. However, it is recommended to place the RZQ pin in the address/command I/O bank, for greater flexibility during debug if a narrower interface project is required for testing.

DQ and DQS Pins Assignment

Intel recommends that you assign the DQS pins to the remaining I/O lanes in the I/O banks as required:

• Constrain the DQ and DQS signals of the same DQS group to the same I/O lane.
• DQ signals from two different DQS groups cannot be constrained to the same I/O lane.

If you do not specify the DQS pins assignment, the Fitter will select the DQS pins automatically.

Sharing an I/O Bank Across Multiple Interfaces

If you are sharing an I/O bank across multiple external memory interfaces, follow these guidelines:

• The interfaces must use the same protocol, voltage, data rate, frequency, and PLL reference clock.
• You cannot use an I/O bank as the address/command bank for more than one interface. The memory controller and sequencer cannot be shared.
• You cannot share an I/O lane. There is only one DQS input per I/O lane, and an I/O lane can connect to only one memory controller.

Ping Pong PHY Implementation

The Ping Pong PHY feature instantiates two hard memory controllers—one for the primary interface and one for the secondary interface. The hard memory controller I/O bank of the primary interface is used for address and command and is always adjacent (contains the same column number and letter before or after the respective I/O bank letter) and above the hard memory controller I/O bank of the secondary interface. All four lanes of the primary hard memory controller I/O bank are used for address and command.

When you use Ping Pong PHY, the EMIF IP exposes two independent Avalon-MM interfaces to user logic; these interfaces correspond to the two hard memory controllers inside the interface. Each Avalon-MM interface has its own set of clock and reset signals. Refer to Qsys Interfaces for more information on the additional signals exposed by Ping Pong PHY interfaces.

For more information on Ping Pong PHY in Stratix 10, refer to Functional Description—Stratix 10 EMIF, in this handbook. For pin allocation information for Stratix 10 devices, refer to External Memory Interface Pin Information for Stratix 10 Devices on www.altera.com.

Additional Requirements for DDR3 and DDR4 Ping-Pong PHY Interfaces

If you are using Ping Pong PHY with a DDR3 or DDR4 external memory interface on a Stratix 10 device, follow these guidelines:

• The address and command I/O bank must not contain any DQS group.
• I/O banks that are above the address and command I/O bank must contain only data pins of the primary interface—that is, the interface with the lower DQS group indices.
• The I/O bank immediately below the address and command I/O bank must contain at least one DQS group of the secondary interface—that is, the interface with the higher DQS group indices. This I/O bank can, but is not required to, contain DQS groups of the primary interface.
• I/O banks that are two or more banks below the address and command I/O bank must contain only data pins of the secondary interface.

PLL Reference Clock Pin

To conserve pin usage and enable core clock network and I/O bank sharing, you can share a PLL reference clock pin between multiple external memory interfaces; the interfaces must be of the same protocol, rate, and frequency. Sharing of a PLL reference clock pin also implies sharing of the reference clock network.

Observe the following guidelines for sharing the PLL reference clock pin:

1. To share a PLL reference clock pin, connect the same signal to the pll_ref_clk port of multiple external memory interfaces in the RTL code.
2. Place related external memory interfaces in the same I/O column.
3. Place related external memory interfaces in adjacent I/O banks. If you leave an unused I/O bank between the I/O banks used by the external memory interfaces, that I/O bank cannot be used by any other external memory interface with a different PLL reference clock signal.

Core Clock Network

To access all external memory interfaces synchronously and to reduce global clock network usage, you may share the same core clock network with other external memory interfaces.

Observe the following guidelines for sharing the core clock network:

1. To share a core clock network, connect the clks_sharing_master_out of the master to the clks_sharing_slave_in of all slaves in the RTL code.
2. Place related external memory interfaces in the same I/O column.
3. Related external memory interfaces must have the same rate, memory clock frequency, and PLL reference clock.

I/O Bank

To reduce I/O bank utilization, you may share an I/O Bank with other external memory interfaces.

Observe the following guidelines for sharing an I/O Bank:

1. Related external memory interfaces must have the same protocol, rate, memory clock frequency, and PLL reference clock.
2. You cannot use a given I/O bank as the address and command bank for more than one external memory interface.
3. You cannot share an I/O lane between external memory interfaces, but an unused pin can serve as a general purpose I/O pin, of compatible voltage and termination standards.

Hard Nios Processor

All external memory interfaces residing in the same I/O column will share the same hard Nios processor. The shared hard Nios processor calibrates the external memory interfaces serially.

Reset Signal

When multiple external memory interfaces occupy the same I/O column, they must share the same IP reset signal.

In addition, there are some exceptions for the following interfaces:

• ×36 emulated QDR II and QDR II+ SRAM in Arria II, Stratix III, and Stratix IV devices.
• RLDRAM II and RLDRAM 3 CIO devices.
• QDR II/+ SDRAM burst-length-of-two devices.
• You must compile the design in the Quartus Prime software to ensure that you are not violating signal integrity and Quartus Prime placement rules, which is critical when you have transceivers in the same design.

The following are general guidelines for placing pins optimally for your memory interfaces:

1. For Arria II GZ, Arria V, Cyclone V, Stratix III, Stratix IV, and Stratix V designs, if you are using OCT, the RUP and RDN, or RZQ pins must be in any bank with the same I/O voltage as your memory interface signals and often use two DQS or DQ pins from a group. If you decide to place the RUP and RDN, or RZQ pins in a bank where the DQS and DQ groups are used, place these pins first and then determine how many DQ pins you have left, to find out if your data pins can fit in the remaining pins. Refer to OCT Support for Arria II GX, Arria II GZ, Arria V, Arria V GZ, Cyclone V, Stratix III, Stratix IV, and Stratix V Devices.
2. Use the PLL that is on the same side of the memory interface. If the interface is spread out on two adjacent sides, you may use the PLL that is located on either adjacent side. You must use the dedicated input clock pin to that particular PLL as the reference clock for the PLL. The input of the memory interface PLL cannot come from the FPGA clock network.
3. The Intel^® FPGA IP uses the output of the memory interface PLL as the DLL input reference clock. Therefore, ensure you select a PLL that can directly feed a suitable DLL.
   Note: Alternatively, you can use an external pin to feed into the DLL input reference clock. The available pins are also listed in the External Memory Interfaces chapter of the relevant device family handbook. You can also activate an unused PLL clock output, set it at the desired DLL frequency, and route it to a PLL dedicated output pin. Connect a trace on the PCB from this output pin to the DLL reference clock pin, but be sure to include any signal integrity requirements such as terminations.
4. Read data pins require the usage of DQS and DQ group pins to have access to the DLL control signals.
   Note: In addition, QVLD pins in RLDRAM II and RLDRAM 3 DRAM, and QDR II+ SRAM must use DQS group pins, when the design uses the QVLD signal. None of the Intel^® FPGA IP uses QVLD pins as part of read capture, so theoretically you do not need to connect the QVLD pins if you are using the Intel^® solution. It is good to connect it anyway in case the Intel^® solution gets updated to use QVLD pins.
5. In differential clocking (DDR3/DDR2 SDRAM, RLDRAM II, and RLDRAM 3 interfaces), connect the positive leg of the read strobe or clock to a DQS pin, and the negative leg of the read strobe or clock to a DQSn pin. For QDR II or QDR II+ SRAM devices with 2.5 or 1.5 cycles of read latency, connect the CQ pin to a DQS pin, and the CQn pin to a CQn pin (and not the DQSn pin). For QDR II or QDR II+ SRAM devices with 2.0 cycles of read latency, connect the CQ pin to a CQn pin, and the CQn pin to a DQS pin.
6. Write data (if unidirectional) and data mask pins (DM or BWSn) pins must use DQS groups. While the DLL phase shift is not used, using DQS groups for write data minimizes skew, and must use the SW and TCCS timing analysis methodology.
7. Assign the write data strobe or write data clock (if unidirectional) in the corresponding DQS/DQSn pin with the write data groups that place in DQ pins (except in RLDRAM II and RLDRAM 3 CIO devices). Refer to the Pin-out Rule Exceptions for your memory interface protocol.
   Note: When interfacing with a DDR, or DDR2, or DDR3 SDRAM without leveling, put the CK and CK# pairs in a single ×4 DQS group to minimize skew between clocks and maximize margin for the t_DQSS, t_DSS, and t_DSH specifications from the memory devices.
8. Assign any address pins to any user I/O pin. To minimize skew within the address pin group, you should assign the address pins in the same bank or side of the device.
9. Assign the command pins to any I/O pins and assign the pins in the same bank or device side as the other memory interface pins, especially address and memory clock pins. The memory device usually uses the same clock to register address and command signals.
   • In QDR II and QDR II+ SRAM interfaces where the memory clock also registers the write data, assign the address and command pins in the same I/O bank or same side as the write data pins, to minimize skew.
   • For more information about assigning memory clock pins for different device families and memory standards, refer to Pin Connection Guidelines Tables.

• All I/O banks in U358- and F572-pin packages for all Arria II GX devices
• All I/O banks in F484-pin packages for all Stratix III devices
• All I/O banks in F780-pin packages for all Arria II GZ, Stratix III, and Stratix IV devices; top and side I/O banks in F780-pin packages for all Stratix V and Arria V GZ devices
• All I/O banks in F1152-pin packages for all Arria II GZ, Stratix III, and Stratix IV devices, except EP4SGX290, EP4SGX360, EP4SGX530, EPAGZ300, and EPAGZ350 devices
• Side I/O banks in F1517- and F1760-pin packages for all Stratix III devices
• All I/O banks in F1517-pin for EP4SGX180, EP4SGX230, EP4S40G2, EP4S40G5, EP4S100G2, EP4S100G5, and EPAGZ225 devices
• Side I/O banks in F1517-, F1760-, and F1932-pin packages for all Arria II GZ and Stratix IV devices

This limitation limits support for ×36 QDR II and QDR II+ SRAM devices. To support these memory devices, this following section describes how you can emulate the ×32/×36 DQS groups for these devices.

• The maximum frequency supported in ×36 QDR II and QDR II+ SRAM interfaces using ×36 emulation is lower than the maximum frequency when using a native ×36 DQS group.

To emulate a ×32/×36 DQS group, combine two ×16/×18 DQS groups together. For ×36 QDR II and QDR II+ SRAM interfaces, the 36-bit wide read data bus uses two ×16/×18 groups; the 36-bit wide write data uses another two ×16/×18 groups or four ×8/×9 groups. The CQ and CQn signals from the QDR II and QDR II+ SRAM device traces are then split on the board to connect to two pairs of CQ/CQn pins in the FPGA. You might then need to split the QVLD pins also (if you are connecting them). These connections are the only connections on the board that you need to change for this implementation. There is still only one pair of K and Kn connections on the board from the FPGA to the memory (see the following figure). Use an external termination for the CQ/CQn signals at the FPGA end. You can use the FPGA OCT features on the other QDR II interface signals with ×36 emulation. In addition, there may be extra assignments to be added with ×36 emulation.

You may also combine four ×9 DQS groups (or two ×9 DQS groups and one ×18 group) on the same side of the device, if not the same I/O bank, to emulate a x36 write data group, if you need to fit the QDR II interface in a particular side of the device that does not have enough ×18 DQS groups available for write data pins. Intel^® does not recommend using ×4 groups as the skew may be too large, as you need eight ×4 groups to emulate the ×36 write data bits.

You cannot combine four ×9 groups to create a ×36 read data group as the loading on the CQ pin is too large and hence the signal is degraded too much.

When splitting the CQ and CQn signals, the two trace lengths that go to the FPGA pins must be as short as possible to reduce reflection. These traces must also have the same trace delay from the FPGA pin to the Y or T junction on the board. The total trace delay from the memory device to each pin on the FPGA should match the Q trace delay (I2).

The slew rate degradation factor is taken into account during timing analysis when you indicate in the UniPHY Preset Editor that you are using ×36 emulation mode. However, you must determine the difference in CQ/CQn arrival time as it is highly dependent on your board topology.

The slew rate degradation factor for ×36 emulation assumes that CQ/CQn has a slower slew rate than a regular ×36 interface. The slew rate degradation is assumed not to be more than 500 ps (from 10% to 90% V_CCIO swing). You may also modify your board termination resistor to improve the slew rate of the ×36-emulated CQ/CQn signals. If your modified board does not have any slew rate degradation, you do not need to enable the ×36 emulation timing in the UniPHY-based controller parameter editor.

For more information about how to determine the CQ/CQn arrival time skew, refer to Determining the CQ/CQn Arrival Time Skew.

Because of this effect, the maximum frequency supported using x36 emulation is lower than the maximum frequency supported using a native x36 DQS group.

For vertical migration with the ×36 emulation implementation, check if migration is possible and enable device migration in the Quartus Prime software.

Each side of the device in these packages has four remaining ×8/×9 groups. You can combine four of the remaining for the write side (only) if you want to keep the ×36 QDR II and QDR II+ SRAM interface on one side of the device, by changing the Memory Interface Data Group default assignment, from the default 18 to 9.

For more information about rules to combine groups for your target device, refer to the External Memory Interfaces chapter in the respective device handbooks.

The following figure shows an example of a board topology comparing an emulated case where CQ is double-loaded and a non-emulated case where CQ only has a single load.

Figure 10. Board Simulation Topology Example

Run the simulation and look at the signal at the FPGA pin. The following figure shows an example of the simulation results from the preceding figure. As expected, the double-loaded emulated signal, in pink, arrives at the FPGA pin later than the single-loaded signal, in red. You then need to calculate the difference of this arrival time at VREF level (0.75 V in this case). Record the skew and rerun the simulation in the other two cases (slow-weak and fast-strong). To pick the largest and smallest skew to be included in Quartus Prime timing analysis, follow these steps:

1. Open the <variation_name>_report_timing.tcl and search for tmin_additional_dqs_variation.
2. Set the minimum skew value from your board simulation to tmin_additional_dqs_variation.
3. Set the maximum skew value from your board simulation to tmax_additional_dqs_variation.
4. Save the .tcl file.

Figure 11. Board Simulation Results

The address or command pins of RLDRAM II must be placed in a DQ-group because these pins are driven by the PHY clock. Half-rate RLDRAM II interfaces and full-rate RLDRAM 3 interfaces use the PHY clock for both the DQ pins and the address or command pins.

RLDRAM II devices have the following pins:

• 2 pins for QK and QK# signals
• 9 DQ pins (in a ×8/×9 DQS group)
• 2 pins for DK and DK# signals
• 1 DM pin
• 14 pins total (15 if you have a QVLD)

In the FPGA, the ×8/×9 DQS group consists of 12 pins: 2 for the read clocks and 10 for the data. In this case, move the QVLD (if you want to keep this connected even though this is not used in the Intel^® FPGA memory interface solution) and the DK and DK# pins to the adjacent DQS group. If that group is in use, move to any available user I/O pins in the same I/O bank.

RLDRAM II devices have the following pins:

• 4 pins for QK/QK# signals
• 18 DQ pins (in ×8/×9 DQS group)
• 2 pins for DK/DK# signals
• 1 DM pin
• 25 pins total (26 if you have a QVLD)

In the FPGA, you use two ×8/×9 DQS group totaling 24 pins: 4 for the read clocks and 18 for the read data.

Each ×8/×9 group has one DQ pin left over that can either use QVLD or DM, so one ×8/×9 group has the DM pin associated with that group and one ×8/×9 group has the QVLD pin associated with that group.

RLDRAM 3 devices have the following pins:

• 4 pins for QK/QK# signals
• 18 DQ pins (in ×8/×9 DQS group)
• 4 pins for DK/DK# signals
• 2 DM pins
• 28 pins total (29 if you have a QVLD)

In the FPGA, you use two ×8/×9 DQS group totaling 24 pins: 4 for the read clocks and 18 for the read data.

Each ×8/×9 group has one DQ pin left over that can either use QVLD or DM, so one ×8/×9 group has the DM pin associated with that group and one ×8/×9 group has the QVLD pin associated with that group.

RLDRAM II devices have the following pins:

• 4 pins for QK/QK# signals
• 36 DQ pins (in x16/x18 DQS group)
• 4 pins for DK/DK# signals
• 1 DM pins
• 46 pins total (47 if you have a QVLD)

In the FPGA, you use two ×16/×18 DQS groups totaling 48 pins: 4 for the read clocks and 36 for the read data. Configure each ×16/×18 DQS group to have:

• Two QK/QK# pins occupying the DQS/DQSn pins
• Pick two DQ pins in the ×16/×18 DQS groups that are DQS and DQSn pins in the ×4 or ×8/×9 DQS groups for the DK and DK# pins
• 18 DQ pins occupying the DQ pins
• There are two DQ pins leftover that you can use for QVLD or DM pins. Put the DM pin in the group associated with DK[1] and the QVLD pin in the group associated with DK[0].
• Check that DM is associated with DK[1] for your chosen memory component.

RLDRAM 3 devices have the following pins:

• 8 pins for QK/QK# signals
• 36 DQ pins (in x8/x9 DQS group)
• 4 pins for DK/DK# signals
• 2 DM pins
• 48 pins total (49 if you have a QVLD)

In the FPGA, you use four ×8/×9 DQS groups.

In addition, observe the following placement rules for RLDRAM 3 interfaces:

For ×18 devices:

• Use two ×8/×9 DQS groups. Assign the QK/QK# pins and the DQ pins of the same read group to the same DQS group.
• DQ, DM, and DK/DK# pins belonging to the same write group should be assigned to the same I/O sub-bank, for timing closure.
• Whenever possible, assign CK/CK# pins to the same I/O sub-bank as the DK/DK# pins, to improve tCKDK timing.

For ×36 devices:

• Use four ×8/×9 DQS groups. Assign the QK/QK# pins and the DQ pins of the same read group to the same DQS group.
• DQ, DM, and DK/DK# pins belonging to the same write group should be assigned to the same I/O sub-bank, for timing closure.
• Whenever possible, assign CK/CK# pins to the same I/O sub-bank as the DK/DK# pins, to improve tCKDK timing.

The address pins typically do not exceed 22 bits, so you may use one ×18 DQS groups or two ×9 DQS groups on the same side of the device, if not the same I/O bank. In Arria V GZ, Stratix III, Stratix IV, and Stratix V devices, one ×18 group typically has 22 DQ bits and 2 pins for DQS/DQSn pins, while one ×9 group typically has 10 DQ bits with 2 pins for DQS/DQSn pins. Using ×4 DQS groups should be a last resort.

Performing Manual Pin Placement

The following table lists rules that you can follow to perform proper manual pin placement and avoid timing failures.

The rules are categorized as follows:

• Mandatory—This rule is mandatory and cannot be violated as it would result in a no‑fit error.
• Recommended—This rule is recommended and if violated the implementation is legal but the timing is degraded.
• Highly Recommended—This rule is not mandatory but is highly recommended because disregarding this rule might result in timing violations.

Performing Manual Pin Placement

The following table lists rules you can follow to perform proper manual pin placement and avoid timing failures.

The rules are categorized as follows:

• Mandatory—This rule is mandatory and cannot be violated as it would result in a no‑fit error.
• Recommended—This rule is recommended and if violated the implementation is legal but the timing is degraded.

I/O Pins Not Available for DDR3 or LPDDR2 External Memory Interfaces (Preliminary)

The I/O pins named in the following table are not available for use when implementing a DDR3 or LPDDR2 external memory interface for a MAX 10 device.

Additional Restrictions on I/O Pin Availability

The following restrictions are in addition to those represented in the above table.

• When implementing a DDR3 or LPDDR2 external memory interface, you can use only 75 percent of the remaining I/O pins in banks 5 and 6 for normal I/O operations.
• When implementing a DDR2 external memory interface, 25 percent of the remaining I/O pins in banks 5 and 6 can be assigned only as input pins.

MAX 10 Board Design Considerations

• For DDR2, DDR3, and LPDDR2 interfaces, the maximum board skew between pins must be lower than 40 ps. This guideline applies to all pins (address, command, clock, and data).
• To minimize unwanted inductance from the board via, Intel recommends that you keep the PCB via depth for V_CCIO banks below 49.5 mil.
• For devices with DDR3 interface implementation, onboard termination is required for the DQ, DQS, and address signals. Intel recommends that you use termination resistor value of 80 Ω to V_TT.
• For the DQ, address, and command pins, keep the PCB trace routing length less than six inches for DDR3, or less than three inches for LPDDR2.

Power Supply Variation for LPDDR2 Interfaces

I/O Pins Connect to Ground for Hard Memory Interface Operation

According to the Cyclone V pin-out file, there are some general I/O pins that are connected to ground for hard memory interface operation. These I/O pins should be grounded to reduce crosstalk from neighboring I/O pins and to ensure the performance of the hard memory interface.

The grounded user I/O pins can also be used as regular I/O pins if you run short of available I/O pins; however, the hard memory interface performance will be reduced if these pins are not connected to ground.

For example, you can build simple DDR slow-speed interfaces that typically require only two clocks: system and write. You can then use the rising and falling edges of these two clocks to derive four phases (0°, 90°, 180°, and 270°). However, as clock speeds increase, the timing margin decreases and additional clocks are required, to optimize setup and hold and meet timing. Typically, at higher clock speeds, you need to have dedicated clocks for resynchronization, and address and command paths.

Intel^® FPGA memory interface IP uses one PLL, which generates the various clocks needed in the memory interface data path and controller, and provides the required phase shifts for the write clock and address and command clock. The PLL is instantiated when you generate the Intel^® FPGA memory IPs.

By default, the memory interface IP uses the PLL to generate the input reference clock for the DLL, available in all supported device families. This method eliminates the need of an extra pin for the DLL input reference clock.

The input reference clock to the DLL can come from certain input clock pins or clock output from certain PLLs.

For the actual pins and PLLs connected to the DLLs, refer to the External Memory Interfaces chapter of the relevant device family handbook.

You must use the PLL located in the same device quadrant or side as the memory interface and the corresponding dedicated clock input pin for that PLL, to ensure optimal performance and accurate timing results from the Quartus Prime software.

The input clock to the PLL can fan out to logic other than the PHY, so long as the clock input pin to the PLL is a dedicated input clock path, and you ensure that the clock domain transfer between UniPHY and the core logic is clocked by the reference clock going into a global clock.

• For the clock source, use the clock input pin specifically dedicated to the PLL that you want to use with your external memory interface. The input and output pins are only fully compensated when you use the dedicated PLL clock input pin. If the clock source for the PLL is not a dedicated clock input pin for the dedicated PLL, you would need an additional clock network to connect the clock source to the PLL block. Using additional clock network may increase clock jitter and degrade the timing margin.
• Pick a PLL and PLL input clock pin that are located on the same side of the device as the memory interface pins.
• Share the DLL and PLL static clocks for multiple memory interfaces provided the controllers are on the same or adjacent side of the device and run at the same memory clock frequency.
• If your design uses a dedicated PLL to only generate a DLL input reference clock, you must set the PLL mode to No Compensation in the Quartus Prime software to minimize the jitter, or the software forces this setting automatically. The PLL does not generate other output, so it does not need to compensate for any clock path.
• If your design cascades PLL, the source (upstream) PLL must have a low‑bandwidth setting, while the destination (downstream) PLL must have a high‑bandwidth setting to minimize jitter. Intel^® does not recommend using cascaded PLLs for external memory interfaces because your design gets accumulated jitters. The memory output clock may violate the memory device jitter specification.
• Use cascading PLLs at your own risk. For more information, refer to “PLL Cascading”.
• If you are using Arria II GX devices, for a single memory instance that spans two right-side quadrants, use a middle-side PLL as the source for that interface.
• If you are using Arria II GZ, Arria V GZ, Stratix III, Stratix IV, or Stratix V devices, for a single memory instance that spans two top or bottom quadrants, use a middle top or bottom PLL as the source for that interface. The ten dual regional clocks that the single interface requires must not block the design using the adjacent PLL (if available) for a second interface.

The UniPHY IP supports PLL cascading using the cascade path without any additional timing derating when the bandwidth and compensation rules are followed. The timing constraints and analysis assume that there is no additional jitter due to PLL cascading when the upstream PLL uses no compensation and low bandwidth, and the downstream PLL uses no compensation and high bandwidth.

The UniPHY IP does not support PLL cascading using the global and regional clock networks. You can implement PLL cascading at your own risk without any additional guidance and specifications from Intel^® . The Quartus Prime software does issue a critical warning suggesting use of the cascade path to minimize jitter, but does not explicitly state that Intel^® does not support cascading using global and regional clock networks.

Some Arria II GX devices (EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260) have direct cascade path for two middle right PLLs. Arria II GX PLLs have the same bandwidth options as Stratix IV GX left and right PLLs.

The Arria 10 External Memory Interface IP does not support PLL cascading.

For example, the top-left DLL can shift DQS pins on the top side and left side of the device. The DLL generates the same phase shift resolution for both sides, but can generate different phase offset to the two different sides, if needed. Each DQS pin can be configured to use or ignore the phase offset generated by the DLL.

The DLL cannot generate two different phase offsets to the same side of the device. However, you can use two different DLLs to for this functionality.

DLL reference clocks must come from either dedicated clock input pins located on either side of the DLL or from specific PLL output clocks. Any clock running at the memory frequency is valid for the DLLs.

To minimize the number of clocks routed directly on the PCB, typically this reference clock is sourced from the memory controllers PLL. In general, DLLs can use the PLLs directly adjacent to them (corner PLLs when available) or the closest PLL located in the two sides adjacent to its location.

When designing for 780-pin packages with EP3SE80, EP3SE110, EP3SL150, EP4SE230, EP4SE360, EP4SGX180, and EP4SGX230 devices, the PLL to DLL reference clock connection is limited. DLL2 is isolated from a direct PLL connection and can only receive a reference clock externally from pins CLK[11:4]p in EP3SE80, EP3SE110, EP3SL150, EP4SE230, and EP4SE360 devices. In EP4SGX180 and EP4SGX230 devices, DLL2 and DLL3 are not directly connected to PLL. DLL2 and DLL3 receive a reference clock externally from pins CLK[7:4]p and CLK[15:12]p respectively.

For more DLL information, refer to the respective device handbooks.

The DLL reference clock should be the same frequency as the memory interface, but the phase is not important.

The required DQS capture phase is optimally chosen based on operating frequency and external memory interface type (DDR, DDR2, DDR3 SDRAM, and QDR II SRAM, or RLDRAM II). As each DLL supports two possible phase offsets, two different memory interface types operating at the same frequency can easily share a single DLL. More may be possible, depending on the phase shift required.

Intel^® FPGA memory IP always specifies a default optimal phase setting, to override this setting, refer to Implementing and Parameterizing Memory IP .

When sharing DLLs, your memory interfaces must be of the same frequency. If the required phase shift is different amongst the multiple memory interfaces, you can use a different delay chain in the DQS logic block or use the DLL phase offset feature.

To simplify the interface to IP connections, multiple memory interfaces operating at the same frequency usually share the same system and static clocks as each other where possible. This sharing minimizes the number of dedicated clock nets required and reduces the number of different clock domains found within the same design.

As each DLL can directly drive four banks, but each PLL only has complete C (output) counter coverage of two banks (using dual regional networks), situations can occur where a second PLL operating at the same frequency is required. As cascaded PLLs increase jitter and reduce timing margin, you are advised to first ascertain if an alternative second DLL and PLL combination is not available and more optimal.

Select a DLL that is available for the side of the device where the memory interface resides. If you select a PLL or a PLL input clock reference pin that can also serve as the DLL input reference clock, you do not need an extra input pin for the DLL input reference clock.

For resource utilization examples to ensure that you can fit your other modules in the device, refer to the “Resource Utilization” section in the Introduction to UniPHY IP chapter of the External Memory Interface Handbook.

One OCT calibration block is used if you are using the FPGA OCT feature in the memory interface.The OCT calibration block uses two pins (RUP and RDN), or single pin (RZQ) (“OCT Support for Arria II GX, Arria II GZ, Arria V, Arria V GZ, Cyclone V, Stratix III, Stratix IV, and Stratix V Devices”). You can select any of the available OCT calibration block as you do not need to place this block in the same bank or device side of your memory interface. The only requirement is that the I/O bank where you place the OCT calibration block uses the same VCCIO voltage as the memory interface. You can share multiple memory interfaces with the same OCT calibration block if the VCCIO voltage is the same.

The following section describes leveling in DDR3, and is equally applicable to DDR4.

Fly-by topology reduces simultaneous switching noise (SSN) by deliberately causing flight-time skew between the data and strobes at every DRAM as the clock, address, and command signals traverse the DIMM, as shown in the following figure.

The flight‑time skew caused by the fly-by topology led the JEDEC committee to introduce the write leveling feature on the DDR3 SDRAMs. Controllers must compensate for this skew by adjusting the timing per byte lane.

During a write, DQS groups launch at separate times to coincide with a clock arriving at components on the DIMM, and must meet the timing parameter between the memory clock and DQS defined as tDQSS of ± 0.25 tCK.

During the read operation, the memory controller must compensate for the delays introduced by the fly-by topology. The Stratix® III, Stratix IV, and Stratix V FPGAs have alignment and synchronization registers built in the I/O element to properly capture the data.

In DDR2 SDRAM, there are only two drive strength settings, full or reduced, which correspond to the output impedance of 18-ohm and 40-ohm, respectively. These output drive strength settings are static settings and are not calibrated; consequently, the output impedance varies as the voltage and temperature drifts.

The DDR3 SDRAM uses a programmable impedance output buffer. There are two drive strength settings, 34-ohmand 40-ohm  . The 40-ohm drive strength setting is currently a reserved specification defined by JEDEC, but available on the DDR3 SDRAM, as offered by some memory vendors. Refer to the data sheet of the respective memory vendors for more information about the output impedance setting. You select the drive strength settings by programming the memory mode register defined by mode register 1 (MR1). To calibrate output driver impedance, an external precision resistor, RZQ, connects the ZQ pin and VSSQ. The value of this resistor must be 240-ohm ± 1%.

If you are using a DDR3 SDRAM DIMM, RZQ is soldered on the DIMM so you do not need to layout your board to account for it. Output impedance is set during initialization. To calibrate output driver impedance after power-up, the DDR3 SDRAM needs a calibration command that is part of the initialization and reset procedure and is updated periodically when the controller issues a calibration command.

In addition to calibrated output impedance, the DDR3 SDRAM also supports calibrated parallel ODT through the same external precision resistor, RZQ, which is possible by using a merged output driver structure in the DDR3 SDRAM, which also helps to improve pin capacitance in the DQ and DQS pins. The ODT values supported in DDR3 SDRAM are 20-ohm , 30-ohm , 40-ohm , 60-ohm , and 120-ohm , assuming that RZQ is 240-ohm.

When you enable dynamic ODT, and there is no write operation, the DDR3 SDRAM terminates to a termination setting of RTT_NOM; when there is a write operation, the DDR3 SDRAM terminates to a setting of RTT_WR. You can preset the values of RTT_NOM and RTT_WR by programming the mode registers, MR1 and MR2.

The following figure shows the behavior of ODT when you enable dynamic ODT.

Figure 14. Dynamic ODT: Behavior with ODT Asserted Before and After the Write

In the multi-load DDR3 SDRAM configuration, dynamic ODT helps reduce the jitter at the module being accessed, and minimizes reflections from any secondary modules.

For more information about using the dynamic ODT on DDR3 SDRAM, refer to the application note by Micron, TN-41-04 DDR3 Dynamic On-Die Termination.

In addition to RTT_NOM and RTT_WR, DDR4 has RTT_PARK which applies a specified termination value when the ODT signal is low.

The dynamic OCT scheme enables series termination (RS) and parallel termination (RT) to be dynamically turned on and off during the data transfer. The series and parallel terminations are turned on or off depending on the read and write cycle of the interface. During the write cycle, the RS is turned on and the RT is turned off to match the line impedance. During the read cycle, the RS is turned off and the RT is turned on as the FPGA implements the far-end termination of the bus.

For more information about dynamic OCT, refer to the I/O features chapters in the devices handbook for your Intel^® device.

The following figure shows dynamic series OCT scheme when the FPGA is writing to the memory.

Refer to the memory vendors when determining the over- and undershoot. They typically specify a maximum limit on the input voltage to prevent reliability issues.

When the SDRAM DIMM is driving the transmission line, the ringing and reflection is minimal because the FPGA-side termination 50-ohm pull-up resistor is matched with the transmission line.

You enable dynamic parallel termination only when the bidirectional I/O acts as a receiver and disable it when the bidirectional I/O acts as a driver. Similarly, you enable dynamic series termination only when the bidirectional I/O acts as a driver and is disable it when the bidirectional I/O acts as a receiver. The default setting for dynamic OCT is series termination, to save power when the interface is idle—no active reads or writes.

Dynamic OCT is useful for terminating any high-performance bidirectional path because signal integrity is optimized depending on the direction of the data. In addition, dynamic OCT also eliminates the need for external termination resistors when used with memory devices that support ODT (such as DDR3 SDRAM), thus reducing cost and easing board layout.

However, dynamic OCT in Stratix III and Stratix IV FPGA devices is different from dynamic ODT in DDR3 SDRAM mentioned in previous sections and these features should not be assumed to be identical.

For detailed information about the dynamic OCT feature in the Stratix III FPGA, refer to the Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device Handbook.

For detailed information about the dynamic OCT feature in the Stratix IV FPGA, refer to the I/O Features in Stratix IV Devices chapter in volume 1 of the Stratix IV Device Handbook.

You can use any one of the following as a reference resistor on the RZQ pin to implement different OCT values:

• 240-ohm reference resistor—to implement RS OCT of 34-ohm, 40-ohm, 48-ohm, 60-ohm, and 80-ohm; and RT OCT resistance of 20-ohm, 30-ohm, 40-ohm, and 120-ohm
• 100-ohm reference resistor—to implement RS OCT of 25-ohm and 50-ohm; and RT OCT resistance of 50-ohm

For detailed information about the dynamic OCT feature in the Stratix V FPGA, refer to the I/O Features in Stratix V Devices chapter in volume 1 of the Stratix V Device Handbook.

Two commonly used termination schemes of SSTL are:

• Single parallel terminated output load with or without series resistors (Class I, as stated in JESD8-15a)
• Double parallel terminated output load with or without series resistors (Class II, as stated in JESD8-15a)

Depending on the type of signals you choose, you can use either termination scheme. Also, depending on your design’s FPGA and SDRAM memory devices, you may choose external or internal termination schemes.

To reduce system cost and simplify printed circuit board layout, you may choose not to have any parallel termination on the transmission line, and use point‑to‑point connections between the memory interface and the memory. In this case, you may take advantage of internal termination schemes such as on‑chip termination (OCT) on the FPGA side and on-die termination (ODT) on the SDRAM side when it is offered on your chosen device.

The following two figures illustrate the most common termination topologies: fly-by topology and non‑fly-by topology, respectively.

With fly‑by topology, you place the parallel termination resistor after the receiver. This termination placement resolves the undesirable unterminated stub found in the non‑fly-by topology. However, using this topology can be costly and complicate routing.

With non‑fly‑by topology, the parallel termination resistor is placed between the driver and receiver (closest to the receiver). This termination placement is easier for board layout, but results in a short stub, which causes an unterminated transmission line between the terminating resistor and the receiver. The unterminated transmission line results in ringing and reflection at the receiver.

If you do not use external termination, DDR2 offers ODT and Intel^® FPGAs have varying levels of OCT support. You should explore using ODT and OCT to decrease the board power consumption and reduce the required board space.

The following table summarizes the extent of OCT support for devices earlier than Arria 10. This table provides information about SSTL‑18 standards because SSTL-18 is the supported standard for DDR2 memory interface by Intel^® FPGAs.

For Arria II, Stratix III and Stratix IV devices, on-chip series (RS) termination is supported only on output and bidirectional buffers. The value of RS with calibration is calibrated against a 25-ohm resistor for class II and 50-ohm resistor for class I connected to RUP and RDN pins and adjusted to ± 1% of 25-ohm or 50-ohm . On-chip parallel (RT) termination is supported only on inputs and bidirectional buffers. The value of RT is calibrated against 100-ohm connected to the RUP and RDN pins. Calibration occurs at the end of device configuration. Dynamic OCT is supported only on bidirectional I/O buffers.

For Arria V, Cyclone V, and Stratix V devices, RS and RT values are calibrated against the on-board resistor RZQ. If you want 25 or 50 ohm values for your RS and RT, you must connect a 100 ohm resistor with a tolerance of +/-1% to the RZQ pin .

For more information about on-chip termination, refer to the device handbook for the device that you are using.

Signals include data (DQ), data strobe (DQS/DQSn), data mask (DM), clocks (mem_clk/mem_clk_n), and address and command signals.

When interfacing with multiple DDR2 SDRAM components where the address, command, and memory clock pins are connected to more than one load, follow these steps:

1. Simulate the system to get the new slew-rate for these signals.
2. Use the derated tIS and tIH specifications from the DDR2 SDRAM data sheet based on the simulation results.
3. If timing deration causes your interface to fail timing requirements, consider signal duplication of these signals to lower their loading, and hence improve timing.

These guidelines will help you plan your board layout, but are not meant as strict rules that must be adhered to. Intel recommends that you perform your own board-level simulations to ensure that the layout you choose for your board allows you to achieve your desired performance.

For more information about how the memory manufacturers route these address and control signals on their DIMMs, refer to the Cadence PCB browser from the Cadence website, at www.cadence.com. The various JEDEC example DIMM layouts are available from the JEDEC website, at www.jedec.org.

For more information about board skew parameters, refer to Board Skews in the Implementing and Parameterizing Memory IP chapter. For assistance in calculating board skew parameters, refer to the board skew calculator tool, which is available at the Intel website.

Intel recommends that you get accurate time base skew numbers for your design when you simulate the specific implementation.

• DIMM—UDIMM topology
• DIMM—RDIMM topology
• Discrete components laid out in UDIMM topology
• Discrete components laid out in RDIMM topology

Trace lengths for CLK and DQS should tightly match for each memory component. To match the trace lengths on the board, a balanced tree topology is recommended for clock and address and command signal routing. In addition to matching the trace lengths, you should ensure that DDR timing is passing in the Report DDR Timing report. For Stratix devices, this timing is shown as Write Leveling tDQSS timing. For Arria and Cyclone devices, this timing is shown as CK vs DQS timing

For a table of device family topology support, refer to Leveling and Dynamic ODT.

The following table lists DDR2 SDRAM layout guidelines. These guidelines are Intel recommendations, and should not be considered as hard requirements. You should perform signal integrity simulation on all the traces to verify the signal integrity of the interface. You should extract the slew rate and propagation delay information, enter it into the IP and compile the design to ensure that timing requirements are met.