AN 927: JESD204C Intel FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Stratix 10 E-Tile Devices

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AN-927 | 2020.09.28

1. JESD204C Intel FPGA IP and ADI AD9081 MxFE* ADC Interoperability Checkout Report for Intel Stratix 10 E-tile Devices

The JESD204C Intel^® FPGA IP is a high-speed point-to-point serial interface intellectual property (IP).

The JESD204C Intel^® FPGA IP has been hardware-tested with a number of selected JESD204C compliant analog-to-digital converter (ADC) devices.

This report highlights the interoperability of the JESD204C Intel^® FPGA IP with the AD9081 ADC converter evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout methodology and test results of the ADC to FPGA JESD204C RX IP. The FPGA JESD204C TX IP data path to AD9081 DAC is not checked out.

1.1. Hardware Requirements

The hardware checkout test requires the following hardware and software tools:

Intel^® Stratix^® 10 TX Signal Integrity (SI) Development Kit (Production Rev B Edition) (1ST280EY2F55E1VG) with 12 V power adaptor
Analog Devices AD9081 MxFE* EVM, part number AD9081-FMCA-EBZ
Voltage divider
SMA (Male) to SMP (Female) cables
SMA (Male) to SMA (Male) cables

1.2. Hardware Setup

An Intel^® Stratix^® 10 TX SI Development Kit (Production Rev B Edition) is used with the ADI AD9081 daughter card module installed to the FMC+ connector of the development board.

The AD9081 EVM derives power from the S10 board through the FMC+ connector.
The E-tile transceiver reference clock of the FPGA is also supplied by the Silicon Labs Si5341 programmable clock generator present in the Intel^® Stratix^® 10 development kit.
The Si5341 programmable clock generator provides a reference clock to the HMC7044 programmable clock generator present in the AD9081 EVM through FPGA (to convert differential clock from Si5431 to single ended clock for HMC7044) and SMA to SMP cable.
The HMC7044 programmable clock generator provides the AD9081 device reference clock. The phase-locked loop (PLL) present in the AD9081 device generates the desired ADC sampling clock from the device reference clock.
The PLL reference clock of the JESD204C Intel^® FPGA IP is supplied by the HMC7044 programmable clock generator through the FMC+ connector.
For Subclass 1, the HMC7044 clock generator generates the SYSREF signal for the AD9081 device and for the JESD204C Intel^® FPGA IP through the FMC+ connector.
The rx_dl_signal signal is connected in between the output of the FPGA and the ADC 0 input of AD9081 through a voltage divider circuit with the SMA to SMA cables to measure the deterministic latency.

Note: Intel^® recommends the SYSREF to be provided by the clock generator that sources the JESD204C Intel^® FPGA IP device clock and sampling clock to ADC.

Figure 1. Hardware Setup

The following system-level diagram shows how the different modules are connected in this design.

Figure 2. System Diagram

In this setup, where LMF = 841, the data rate of transceiver lanes is 24.75 Gbps. The SYSREF and clocking scheme for FPGA and ADC is explained below and illustrated in Figure 2.

The Si5341 out8 generates 375 MHz clock to E-Tile transceiver reference clock. The 122.88 MHz differential output clock generated by the Si5341 out2 is fed to FPGA and taken out of FPGA as a single ended clock connected to CLK OUT SMA port J33 in the development kit for the HMC7044 EXT_HMCREF SMP port in AD9081 EVM through a cable. The HMC7044 takes the 122.88 MHz reference clock and generates 375 MHz for the device clock CLKIN of AD9081 and a periodic SYSREF signal of 11.71875 MHz for the SYSREF input of AD9081. The HMC7044 also generates 375 MHz for the FPGA core PLL reference clock and a periodic SYSREF signal of 11.71875 MHz for JESD204C Intel^® FPGA IP through the FMC+ connector.

The JESD204C Intel^® FPGA IP is instantiated in duplex mode but only the receiver path is used. For FCLK_MULP = 2, WIDTH_MULP = 8, S = 1 the core PLL generates 187.5 MHz link clock and 375 MHz frame clock.

The rx_dl_signal signal from CLK OUT SMA port J31 to ADC0/None SMA port is for the deterministic latency measurement.

1.3. Hardware Checkout Methodology

The following section describes the test objectives, procedure, and the passing criteria. The test covers the following areas:

Receiver data link layer
Receiver transport layer
Deterministic Latency (Subclass 1)

1.3.1. Receiver Data Link Layer

This test area covers the test cases for sync header alignment (SHA) and extended multiblock alignment (EMBA).

On link start up, after the receiver reset, the JESD204C Intel^® FPGA IP starts looking for the sync header stream that is transmitted by the device. The Signal Tap logic analyzer tool monitors the receiver data link layer operation.

1.3.1.1. Sync Header Alignment (SHA)

Table 1. Sync Header Alignment Test Cases
Test Case	Objective	Description	Passing Criteria
SHA.1	Check if Sync Header Lock is asserted after the completion of reset sequence.	The following signals in `<ip_variant_name>` _base.v are tapped: `j204c_rx_rst_n` `j204c_rx_sh_lock` `j204c_rx_int` ¹ The `rxlink_clk` is used as the sampling clock for the Signal Tap.	The `j204c_rx_sh_lock` is asserted after the deassertion of `j204c_rx_rst_n.` The `j204c_rx_int` ¹ signal should stay low if there is no error.
SHA.2	Check Sync Header Lock status after sync header lock is achieved (or during the Extended Multi-Block Alignment phase) and stable.	The following signals in `<ip_variant_name>` _base.v are tapped `j204c_rx_sh_lock` `j204c_rx_int` ¹ The `rxlink_clk` is used as the sampling clock for the Signal Tap.	The `j204c_rx_sh_lock` is asserted. The `j204c_rx_int¹` signal is deasserted if there is no error.

¹ The error interrupts that are enabled by default is sufficient for passing criteria.

1.3.1.2. Extended Multiblock Alignment (EMBA)

Table 2. Extended Multiblock Alignment Test Cases
Test Case	Objective	Description	Passing Criteria
EMBA.1	Check if the Extended Multiblock Lock is asserted only after the assertion of Sync Header Lock.	The following signals in `<ip_variant_name>` _base.v are tapped: `j204c_rx_emb_lock` `j204c_rx_sh_lock` `j204c_rx_int` ⁰ The `rxlink_clk` is used as the sampling clock for the Signal Tap.	The `j204c_rx_emb_lock` is asserted after assertion of `j204c_rx_sh_lock`. The `j204c_rx_int` ⁰ signal is deasserted if there is no error.
EMBA.2	Check if the Extended Multiblock Lock status being stable (after extended multiblock lock or until elastic buffer is released) along with no invalid multiblock.	The following signals in `<ip_variant_name>` _base.v are tapped: `j204c_rx_emb_lock` `j204c_rx_int` ⁰ The `rxlink_clk` is used as the sampling clock for the Signal Tap.	The `j204c_rx_emb_lock` should remain asserted. The `j204c_rx_int` ⁰ signal is deasserted if there is no error.
EMBA.3	Check the lane alignment.	The following signals in `<ip_variant_name>` _base.v are tapped: `j204c_rx_dev_lane_align` `j204c_rx_int` ⁰ The `rxlink_clk` is used as the sampling clock for the Signal Tap.	The `j204c_rx_dev_lane_align` is asserted after the assertion of `j204c_rx_emb_lock` and next LEMC event. The `j204c_rx_int` ⁰ signal is deasserted if there is no error.

1.3.2. Receiver Transport Layer (TL)

To check the data integrity of the payload data stream through the receiver (RX) JESD204C Intel^® FPGA IP and transport layer, the ADC is configured to ramp/PRBS test pattern. The ADC is also set to operate with the same configuration as set in the JESD204C Intel^® FPGA IP. The ramp/PRBS checker in the FPGA fabric checks the ramp/PRBS data integrity for one minute. The RX JESD204C Intel^® FPGA IP register rx_err is polled continuously for zero value for one minute.

The figure below shows the conceptual test setup for data integrity checking.

Figure 3. Data Integrity Check Using Ramp/PRBS15 Checker

Table 3. Transport Layer Test Cases
Test Case	Objective	Description	Passing Criteria
TL.1	Check the transport layer mapping of the data channel using ramp test pattern.	The following signals in `<ip_variant_name>` _base.v are tapped: `j204c_rx_avst_ready` `j204c_rx_avst_valid` `j204c_rx_avst_data [(MSWIDTH_MULPN)-1:0]` ² ³ ⁴ ⁵ `j204c_rx_avst_control [(MSWIDTH_MULPCS)-1:0]` ² ³ ⁴ ⁶ `rx_patchk_data_error_int` The `rxframe_clk` is used as the sampling clock for the Signal Tap. The `rx_patchk_data_error_int` signal indicates a pass or fail for the ramp checker.	The `j204c_rx_avst_valid` is asserted. The `j204c_rx_avst_ready` is asserted. The `rx_patchk_data_error_int` signal is deasserted.
TL.2	Check the transport layer mapping of the data channel using the PRBS15 test pattern.	The following signals in `<ip_variant_name>` _base.v are tapped: `j204c_rx_avst_ready` `j204c_rx_avst_valid` `j204c_rx_avst_data [(MSWIDTH_MULPN)-1:0]` ² ³ ⁴ ⁵ `j204c_rx_avst_control [(MSWIDTH_MULPCS)-1:0]` ² ³ ⁴ ⁶ `rx_patchk_data_error_int` The `rxframe_clk` is used as the sampling clock for the Signal Tap. The `rx_patchk_data_error_int` signal indicates a pass or fail for the ramp checker.	The `j204c_rx_avst_valid` is asserted. The `j204c_rx_avst_ready` is asserted. The `rx_patchk_data_error_int` signal is deasserted.

² M is the number of converters.

³ S is the number of transmitted samples per converter per frame.

⁴ WIDTH_MULP is the data width multiplier between the application layer and transport layer.

⁵ N is the number of conversion bits per converter.

⁶ CS is the number of control bits per conversion samples.

1.3.3. Deterministic Latency - Subclass 1 (DL)

The Deterministic Latency Measurement Block Diagram figure shows the conceptual test setup for deterministic latency measurement. The HMC7044 is configured to provide a periodic SYSREF to both AD9081 and JESD204C Intel^® FPGA IP in FPGA with the required extended multiblock period.

The deterministic latency measurement block checks the deterministic latency by measuring the number of frame clock counts between the assertion of the rx_dl_signal signal and logic OR of the MSB bit of all sample at the output of the RX JESD204C Intel^® FPGA IP after the link is established or after the assertion of j204c_rx_avst_valid.

Note: The voltage divider is using the resistor divider circuit in the rx_dl_signal signal path to match the voltage level of the FPGA output and AD9081 ADC input.

Figure 4. Deterministic Latency Measurement Block Diagram

Figure 5. Deterministic Latency Measurement Timing Diagram

With the setup in System Diagram figure, three test cases were defined to prove deterministic latency. The JESD204C Intel^® FPGA IP does continuous SYSREF detection.

Table 4. Deterministic Latency Test Cases
Test Case	Objective	Description	Passing Criteria
DL.1	Check the FPGA SYSREF single detection.	Check that the FPGA detects the first rising edge of SYSREF pulse. Read the status of `sysref_singledet` (bit[2]) identifier in `rx_sysref_ctrl` register at address `0x54`. Read the status of `sysref_lemc_err` (bit[0]) identifier in the `rx_err` register at address `0x60`.	The value of `sysref_singledet` identifier should be zero. The value of `sysref_lemc_err` identifier should be zero.
DL.2	Check the SYSREF capture.	Check that FPGA and ADC capture SYSREF correctly and restart the LEM counter. Both FPGA and ADC are also repetitively reset. Read the value of `rbd_count` (bit[18:10]) identifier in `rx_status0` register at address `0x80`.	If the SYSREF is captured correctly and the LEM counter restarts, for every reset, the `rbd_count` value should only drift within 1-2 link clocks to accommodate for worst-case power cycle variation.
DL.3	Check the data latency during user data phase.	Check that the data latency is consistent for every FPGA and ADC reset and power cycle (using the `rx_dl_signal` signal as shown in Deterministic Latency Measurement Block Diagram figure). The deterministic latency measurement block in System Diagram figure has a counter to measure the link clock count.	The link clock count value should only drift within 1-2 link clocks for at least 10 power cycle test.

1.4. JESD204C Intel FPGA IP and ADC Configurations

The JESD204C Intel^® FPGA IP parameters (L, M, and F) in this hardware checkout are natively supported by the AD9081 device. The transceiver data rate, sampling clock, and other JESD204C parameters comply with the AD9081 operating conditions.

The hardware checkout testing implements the JESD204C Intel^® FPGA IP with the following parameter configuration.

Global setting for all configuration:

CF = 0
CS = 0
Subclass = 1
SH_CONFIG = CRC-12
FPGA Management Clock (MHz) = 100

Note: The other configurations are retained at default values.

Table 5. Parameter Configuration
LMF	N	NP	S	HD	E	ADC Sampling Clock (MHz)	FPGA Device Clock (MHz) ⁷	FPGA Link Clock (MHz) ⁸	FPGA Frame Clock (MHz)⁸	Lane Rate (Gbps)	Decimation Factor	Data Pattern
841	16	16	1	1	1	3000.00	375.00	187.50	375.00	24.75000	1	PRBS15	Ramp
8.16.4	16	16	1	0	1	2480.00	310.00	155.00	155.00	20.46000	4	PRBS15	Ramp
886	12	12	4	0	3	2949.12	184.32	92.16	368.64	12.16512	3	PRBS15	Ramp
821	16	16	2	1	1	2949.12	184.32	92.16	368.64	12.16512	1	PRBS15	Ramp
882	16	16	1	0	1	2949.12	245.76	122.88	122.88	16.22016	3	PRBS15	Ramp
442	16	16	1	0	1	3360.00	280.00	140.00	140.00	18.48000	3	PRBS15	Ramp
484	16	16	1	0	1	2949.12	184.32	92.16	92.16	12.16512	8	PRBS15	Ramp
823	12	12	8	0	3	2949.12	276.48	69.12	276.48	9.12384	1	PRBS15	Ramp
882	16	16	1	0	1	2949.12	245.76	61.44	61.44	8.11008	6	PRBS15	Ramp
821	16	16	2	1	1	3072.00	192.00	96.00	384.00	12.67200	1	PRBS15	Ramp
6.12.4	16	16	1	0	1	2760.00	345.00	172.50	172.50	22.77000	4	PRBS15	Ramp
364	16	16	1	0	1	2700.00	225.00	112.50	112.50	14.85000	6	PRBS15	Ramp
288	16	16	1	0	1	2880.00	180.00	90.00	90.00	11.88000	16	PRBS15	Ramp

⁷ The device clock frequency of the E-tile transceiver is the same as the core PLL of the JESD204C Intel^® FPGA IP.

⁸ The frame clock and link clock are derived from the device clock by using an internal core PLL.

1.5. Test Results

The following table contains the possible results and their definition.

Table 6. Results Definition
Result	Definition
PASS	The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments	The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included (example: due to time limitations, only a portion of the testing was performed).
FAIL	The DUT was observed to exhibit non-conformant behavior.
Warning	The DUT was observed to exhibit behavior that is not recommended.
Refer to comments	From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2 with different values of L, M, F, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 7. Result for Test Cases SHA.1, SHA.2, EMBA.1, EMBA.2, EMBA.3, TL.1, and TL.2
Test	L	M	F	Data Rate (Gbps)	ADC Sampling Clock (MHz)	FPGA Link Clock (MHz) ⁹	FPGA Frame Clock (MHz)⁹	Result
1	8	4	1	24.75000	3000.00	187.50	375.00	PASS
2	8	16	4	20.46000	2480.00	155.00	155.00	PASS
3	8	8	6	12.16512	2949.12	92.16	368.64	PASS
4	8	2	1	12.16512	2949.12	92.16	368.64	PASS
5	8	8	2	16.22016	2949.12	122.88	122.88	PASS
6	4	4	2	18.48000	3360.00	140.00	140.00	PASS
7	4	8	4	12.16512	2949.12	92.16	92.16	PASS
8	8	2	3	9.12384	2949.12	69.12	276.48	PASS
9	8	8	2	8.11008	2949.12	61.44	61.44	PASS
10	8	2	1	12.67200	3072.00	96.00	384.00	PASS
11	6	12	4	22.77000	2760.00	172.50	172.50	PASS
12	3	6	4	14.85000	2760.00	112.50	112.50	PASS
13	2	8	8	11.88000	2880.00	90.00	90.00	PASS

The following table shows the results for test cases DL.1, DL.2, and DL.3 with different values of L, M, F, data rate, sampling clock, link clock, and SYSREF frequencies.

Table 8. Result for Deterministic Latency Test
Test	L	M	F	Data Rate (Gbps)	ADC Sampling Clock (MHz)	FPGA Link Clock (MHz)⁹	FPGA Frame Clock (MHz)⁹	Result	RBD Count	Latency (Frame Clock Cycles)	Latency (Equivalent Link Clock Cycles)
DL.1	8	4	1	24.75000	3000.00	187.50	375.00	PASS	14	96	48
DL.2	8	4	1	24.75000	3000.00	187.50	375.00	PASS
DL.3	8	4	1	24.75000	3000.00	187.50	375.00	PASS
DL.1	8	16	4	20.46000	2480.00	155.00	155.00	PASS	5	91	91
DL.2	8	16	4	20.46000	2480.00	155.00	155.00	PASS
DL.3	8	16	4	20.46000	2480.00	155.00	155.00	PASS
DL.1	8	8	6	12.16512	2949.12	92.16	368.64	PASS	28	244	61
DL.2	8	8	6	12.16512	2949.12	92.16	368.64	PASS
DL.3	8	8	6	12.16512	2949.12	92.16	368.64	PASS
DL.1	8	2	1	12.16512	2949.12	92.16	368.64	PASS	5	164	41
DL.2	8	2	1	12.16512	2949.12	92.16	368.64	PASS
DL.3	8	2	1	12.16512	2949.12	92.16	368.64	PASS
DL.1	8	8	2	16.22016	2949.12	122.88	122.88	PASS	14	55	55
DL.2	8	8	2	16.22016	2949.12	122.88	122.88	PASS
DL.3	8	8	2	16.22016	2949.12	122.88	122.88	PASS
DL.1	4	4	2	18.48000	3360.00	140.00	140.00	PASS	2	66	66
DL.2	4	4	2	18.48000	3360.00	140.00	140.00	PASS
DL.3	4	4	2	18.48000	3360.00	140.00	140.00	PASS
DL.1	4	8	4	12.16512	2949.12	92.16	92.16	PASS	5	91	91
DL.2	4	8	4	12.16512	2949.12	92.16	92.16	PASS
DL.3	4	8	4	12.16512	2949.12	92.16	92.16	PASS
DL.1	8	2	3	9.12384	2949.12	69.12	276.48	PASS	20	224	56
DL.2	8	2	3	9.12384	2949.12	69.12	276.48	PASS
DL.3	8	2	3	9.12384	2949.12	69.12	276.48	PASS
DL.1	8	8	2	8.11008	2949.12	61.44	61.44	PASS	10	54	54
DL.2	8	8	2	8.11008	2949.12	61.44	61.44	PASS
DL.3	8	8	2	8.11008	2949.12	61.44	61.44	PASS
DL.1	8	2	1	12.67200	3072.00	96.00	384.00	PASS	5	165	42
DL.2	8	2	1	12.67200	3072.00	96.00	384.00	PASS
DL.3	8	2	1	12.67200	3072.00	96.00	384.00	PASS
DL.1	6	12	4	22.77000	2760.00	172.50	172.50	PASS	14	86	86
DL.2	6	12	4	22.77000	2760.00	172.50	172.50	PASS
DL.3	6	12	4	22.77000	2760.00	172.50	172.50	PASS
DL.1	3	6	4	14.85000	2700.00	112.50	112.50	PASS	7	89	89
DL.2	3	6	4	14.85000	2700.00	112.50	112.50	PASS
DL.3	3	6	4	14.85000	2700.00	112.50	112.50	PASS
DL.1	2	8	8	11.88000	2880.00	90.00	90.00	PASS	9	117	117
DL.2	2	8	8	11.88000	2880.00	90.00	90.00	PASS
DL.3	2	8	8	11.88000	2880.00	90.00	90.00	PASS

⁹ The frame clock and link clock are derived from the core clock using an internal core PLL.

1.6. Test Result Comments

In each test case, the RX JESD204C Intel^® FPGA IP successfully establishes the sync header alignment, extended multiblock alignment, and until user data phase.

No data integrity issue is observed by the ramp checker for JESD configurations at different lanes rates covering all physical lanes, also no cyclic redundancy check (CRC) and command parity error is observed.

In the deterministic latency measurement, consistent RBD count and total latency between the AD9081 ADC input and the JESD Intel^® FPGA IP transport layer output are observed across multiple power cycles or resets.

To avoid lane de-skew error and achieve deterministic latency, the LEMC or RBD offset need to be programmed in the JESD204C RX IP for a few JESD configurations. The modes as stated in the table below.

Mode (LMF)	rbd_offset (sysref_ctrl[24:16])	lemc_offset (sysref_ctrl[15:8])
841	14	Default. Compile-time specific.
882	14	13
6.12.4	14	Default. Compile-time specific.

1.7. Document Revision History for AN 927: JESD204C Intel FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Intel Stratix 10 E-Tile Devices

Document Version	Changes
2020.09.28	Initial release.

1.8. Appendix

Intel^® Quartus^® Prime Pro Edition software version 19.4.0 Build 64 is used for compilation of designs.

The ADC supports over 100 JESD204C operating modes, all of which are also supported by the JESD204C Intel^® FPGA IP. The 13 ADC modes that are tested represent a set of popular JESD204C parameters to demonstrate broad interoperability across all modes supported by the ADC.