Parallel loopback with external VCXO,

Parallel loopback without external VCXO,

Serial loopback

• Parallel loopback with external VCXO: Parallel loopback design with an external VCXO to synchronize the clock between RX and TX.
• Parallel loopback without external VCXO: Parallel loopback design which uses internal fPLL on the FPGA to synchronize the clock between RX and TX.
  Note: This option is only available if you use production device.
• Serial loopback: A serial loopback design to enables a simple demonstration when you do not have a video source available and to highlight the Dynamic Tx clock switching feature. The IP core generates an internal video pattern generator along with the TX to be transmitted to RX.

Tx PLL type

CMU,

fPLL,

ATX

ATX-fPLL cascading

Select the transceiver PLL type.

Dynamic Tx clock switching

Off,

Tx PLL switching,

Tx PLL reference clock switching

• Off: Disable dynamic switching.
• Tx PLL switching: Instantiates two PLLs, each with its own reference input clock.
• Tx PLL reference clock switching: Instantiates one PLL with two reference input clocks.

Turn on this option to allow dynamic switching between 1 and 1/1.001 data rates.

On,

Off

On,

Off

Verilog,

VHDL

Nextera VIDIO 12G-SDI FMC card,

Terasic 12G-SDI FMC card

No Development Kit,

Stratix 10 GX FPGA L-tile Development Kit,

Stratix 10 GX FPGA H-tile Development Kit,

Custom Development Kit

• No Development Kit: This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.
• Intel^® Stratix^® 10 L-tile or H-tile FPGA Development Kit: This option automatically selects the project's target device to match the device on this development kit. You may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit. Based on the Intel^® Stratix^® 10 device you are using, you can choose to use either the Stratix 10 GX FPGA L-tile or H-tile development kit.
  Note: This option is not available if you select Bidirectional mode. The SDI channels on the development kit and daughter card pins are only compatible with simplex mode.
• Custom Development Kit: This option allows the design example to be tested on a third party development kit with an Intel FPGA. You may need to set the pin assignments on your own.

On,

Off

• TX
  • The TX core receives the video data from the top level and encodes the necessary information, (e.g. line number (LN), cyclical redundancy check (CRC), payload ID), into the data stream(s).
  • In a multi-rate design, the TX core oversamples the received data up to 11.88 Gbps data rate for every video standard.
  • Specify the assignment of the parallel data interface (tx_parallel_data) to the transceiver based on the 11.88 Gbps data rate settings.
• RX
  • The RX core receives the parallel data from the L-Tile/H-Tile Transceiver Native PHY Intel^® Stratix^® 10 FPGA IP core and decodes information. This information includes descrambling, realigning data, and extracting the necessary information for user.
  • For a multi-rate design, due to the difference in data widths recovered for different video standards, rearrange rx_parallel_data from the transceiver before passing the data back to the protocol block.

L-Tile/H-Tile Transceiver Native PHY Intel^® Stratix^® 10 FPGA IP

The maximum parallel data width on the L-Tile/H-Tile Transceiver Native PHY Intel^® Stratix^® 10 FPGA IP core can only go up to 40 bits. Therefore, the design requires a PHY adapter block to be compatible with the IP core.

For the duplex mode transceiver (SDI triple-rate parallel loopback with external VCXO design example), generate a dummy RX only PHY ( sdi_rx_phy.ip) to get the transceiver configuration files (*_CFG0.sv, *_CFG1.sv, …) for RX reconfiguration. The generated configuration files from the duplex mode transceiver may contain some TX registers. You need not reconfigure the registers because only the SDI RX core requires transceiver reconfiguration.

Transceiver PHY Reset Controller Intel^® Stratix^® 10 FPGA IP

• TX
  • The reset input of this controller is triggered from the top level.
  • The controller generates the corresponding analog and digital reset signal to the L-Tile/H-Tile Transceiver Native PHY Intel^® Stratix^® 10 FPGA IP block, according to the reset sequencing inside the block.
  • Use the tx_ready output signal from the block as a reset signal to the TX core to indicate that the transceiver is up and running, and ready to receive data from the core.
• RX
  • The reset input of this controller is triggered by the IP core.
  • The controller generates the corresponding analog and digital reset signal to the L-Tile/H-Tile Transceiver Native PHY Intel^® Stratix^® 10 FPGA IP block according to the reset sequencing inside the block.

RX transceiver reconfiguration management block that reconfigures the L-Tile/H-Tile Transceiver Native PHY Intel^® Stratix^® 10 FPGA IP block to receive different data rates from SD-SDI to 12G-SDI standards.

To indicate the status of the transceiver, connect rx_cal_busy and rx_analogreset_stat from the transceiver to this block.

TX PLL or transceiver reconfiguration management block that reconfigures the TX PLL or L-Tile/H-Tile Transceiver Native PHY Intel^® Stratix^® 10 FPGA IP block to change the TX clock dynamically for switching between integer and fractional frame rates.

The block requires tx_cal_busy, pll_cal_busy, and tx_analogreset_stat from the transceiver, and the PLLs to indicate the status of the transceiver in a TX PLL switching design.

Move the TX PLL out from the TX top if you want to merge the PLL between multiple channels.

Basic video pattern generator which supports SD-SDI up to 12G-SDI video formats with 4:2:2 YCbCr. The generator enables you to select static video with colorbar pattern or pathological pattern.

Provides a memory-mapped interface for controlling the video pattern generator.

Provides System Console host access to the Parallel I/O (PIO) IP core in the design through the JTAG interface.

This generic functional block prevents transceivers from recalibrating simultaneously when either RX or TX transceivers within the same physical channel require reconfiguration. The simultaneous recalibration impacts applications where RX and TX transceivers within the same channel are assigned to independent IP implementations.

This transceiver arbiter is an extension to the resolution recommended for merging simplex TX and simplex RX into the same physical channel. This transceiver arbiter also assists in merging and arbitrating the Avalon-MM RX and TX reconfiguration requests targeting simplex RX and TX transceivers within a channel as the reconfiguration interface port of the transceivers can only be accessed sequentially. The transceiver arbiter is not required when only either RX or TX transceiver is used in a channel.

The transceiver arbiter identifies the requester of a reconfiguration through its Avalon-MM reconfiguration interfaces and ensures that the corresponding tx_reconfig_cal_busy or rx_reconfig_cal_busy is gated accordingly.

Input

1

644.53125 MHz dedicated transceiver reference clock. Programmable to 148.5, 148.35165, or 100 MHz from the Clock Controller.

Input

1

156.25 MHz dedicated transceiver reference clock. Programmable to 148.5 MHz from the Clock Controller.

Input

1

148.5 or 148.35 MHz dedicated transceiver reference clock.

Input

1

625 MHz dedicated transceiver reference clock. Programmable to 297 or 296.7033 MHz from the Clock Control GUI.

Input

1

Dedicated transceiver reference clock that is connected to the second TX PLL in parallel loopback designs with dynamic TX clock switching enabled.

Input

1

125 MHz clock.

Input

1

Push button to power down LMK03328 after switching the jumper settings.

Input

1

Global reset.

Output

Green LED display.

Output

Red LED display.

Input

1

On-board SDI RX serial data.

Output

1

On-board SDI TX serial data.

Output

1

Voltage control for Si516.

Output

1

Voltage control for Si516.

Output

1

On-board SDI RX Equalizer Bypass.

Output

1

On-board SDI RX Equalizer Auto Sleep.

Output

1

On-board SDI RX Equalizer Mute.

Output

1

On-board SDI TX cable driver slew rate control.

Input

1

297 or 296.7 MHz dedicated transceiver reference clock from FMC port A.

Input

1

SDI RX serial data from FMC port A.

Input

1

RX cable equalizer lock status on Nextera daughter card.

Output

1

SDI TX serial data from FMC port A.

Output

1

Initialize LMH1983 on Nextera daughter card.

Output

1

F sync signal LMH1983 on Nextera daughter card.

Output

1

V sync signal LMH1983 on Nextera daughter card.

H sync signal LMH1983 on Nextera daughter card.

Power-down signal LMH1983 on Nextera daughter card.

Input

1

SDI RX serial data from FMC port A.

Input

1

RX cable equalizer lock status on Terasic daughter card.

Output

1

SDI TX serial data from FMC port A.

Input

1

RX transceiver reference clock. This clock must be a free-running clock.

Input

1

SDI RX core clock. This clock must be a free-running clock.

Input

1

TX PLL reference clock. This clock must be a free-running clock.

Input

1

Secondary TX PLL reference clock. This clock must be a free-running clock.

Input

1

RX reconfiguration management clock, Avalon-MM interface clock, and PHY reset control input clock. This clock must be a free-running clock.

Input

1

TX reconfiguration management clock, and Avalon-MM interface clock, and PHY reset control input clock. This clock must be a free-running clock.

Output

1

RX transceiver recovered parallel clock for video data.

Output

1

TX transceiver recovered parallel clock for video data.

Input

1

TX core and PHY reset signal.

Input

1

RX core and PHY reset signal.

Input

TX reconfiguration reset signal.

Input

1

RX reconfiguration reset signal.

Output

Reset signal generated to reset the receiver downstream protocol logic. This generated reset signal is synchronous to rx_vid_clkout clock domain.

Output

20*N

Output

1

Data valid signal generated from SDI RX core. The timing must be synchronous to rx_vid_clkout and has the following settings:

• SD-SDI: 1H 4L 1H 5L
• HD/3G/6G/12G-SDI: H

Output

3

Received video standard.

• 3'b000: SD-SDI
• 3'b001: HD-SDI
• 3'b011: 3G-SDI Level A
• 3'b010 3G-SDI Level B
• 3'b101: 6G-SDI 4 Streams Interleaved
• 3'b100: 6G-SDI 8 Streams Interleaved
• 3'b111: 12G-SDI 8 Streams Interleaved
• 3'b110: 12G-SDI16 Streams Interleaved

Output

1

Frame locked indicates that the IP core has spotted multiple frames with the same timing.

Output

N

Output

N

Output

N

Output

N

Output

20*N

Input

1

Transmitter parallel data valid. The timing (H: High, L: Low) must be synchronous to tx_pclk clock domain and has the following settings:

• SD-SDI = 1H 4L 1H 5L
• HD-SDI = H (for single-rate) and 1H 1L (triple-rate/multi-rate)
• 3G/6G/12G-SDI = H

Input

3

Indicates the desired transmit video standard.

• 3'b000: SD-SDI
• 3'b001: HD-SDI
• 3'b011: 3G-SDI Level A
• 3'b010 3G-SDI Level B
• 3'b101: 6G-SDI 4 Streams Interleaved
• 3'b100: 6G-SDI 8 Streams Interleaved
• 3'b111: 12G-SDI 8 Streams Interleaved
• 3'b110: 12G-SDI16 Streams Interleaved

Input

1

Transmitter TRS input.

For use in LN, CRC, or payload ID insertion. Assert on the first word of both end of active video (EAV) TRS and start of active video (SAV) TRS.

Input

1

Enable CRC insertion for all SDI video standards, except SD-SDI.

Input

1

Enable LN insertion for all SDI video standards, except SD-SDI.

Input

11*N

Input

11*N

LN insertion in the data stream when sdi_tx_enable_ln = 1.

Input

1

Enable this signal to overwrite the existing payload ID embedded in the data stream.

Input

11*N

Indicates the line number to be inserted with the payload ID.

Input

11*N

Input

8*N

Payload ID byte to be inserted in the payload ID field.

Input

8*N

Input

8*N

Input

8*N

Input

8*N

Input

8*N

Input

8*N

Input

8*N

Input

1

Output

1

Data valid signal generated from SDI TX core. The timing (H: High, L: Low) is synchronous to tx_vid_clkout and has the following settings:

• SD-SDI = 1H 4L 1H 5L
• HD-SDI = H (for single-rate) and 1H 1L (triple-rate/multi-rate)
• 3G/6G/12G-SDI = H

Output

1

Alignment locked indicating the IP core has spotted a TRS and word alignment performed.

Output

N

Output

1

Indicates that the receiver is receiving video rate at integer or fractional frame rate:

• 0: Integer frame rate
• 1: Fractional frame rate

Output

4*N

Output

N

Output

N

Output

11*N

Received line number from protocol.

Output

11*N

Output

N

CRC error status signal from protocol.

Output

N

Output

N

Output

N

Output

11*N

Payload ID status from protocol.

Output

11*N

Output

8*N

Output

8*N

Output

8*N

Output

8*N

Output

N

Output

N

Output

8*N

Output

8*N

Output

8*N

Output

8*N

Output

N

Output

N

Input

1

Always set to 1'b0 if you are not doing any TX clock dynamic switching.

Input

1

Transceiver calibration status to TX PHY reset controller.

Input

1

Transceiver calibration status to RX PHY reset controller and Rx reconfiguration management module.

1

RX transceiver serial data.

Output

1

TX transceiver serial data.

Output

1

RX transceiver status.

Output

1

TX transceiver status.

Output

1

Calibration status signal from RX transceiver.

Output

1

Calibration status signal from TX transceiver.

Output

1

TX PLL lock status.

Output

1

TX PLL alt lock status.

Output

1

RX CDR reconfiguration status.

Output

1

TX PLL/transceiver reconfiguration status.

Input

1

Reconfiguration interface signals from transceiver arbiter to duplex mode transceiver.

Input

1

Input

11

Input

32

Output

32

Output

1

Input

1

Reconfiguration interface signals from transceiver arbiter to RX transceiver.

Input

1

Input

11

Input

32

Output

32

Output

1

Input

1

Reconfiguration interface signals from transceiver arbiter to TX transceiver.

Input

1

Input

11

Input

32

Output

32

Output

1

Input

32

Reconfiguration interface signals from RX reconfiguration management module to transceiver arbiter.

Input

1

Output

1

Output

1

Output

11

Output

32

Input

32

Reconfiguration interface signals from TX reconfiguration management module to transceiver arbiter

Input

1

Output

1

Output

1

Output

11

Output

32

Input

1

Reconfiguration interface signals to fPLL Avalon-MM interface.

Input

1

Input

32

Input

11

Output

32

Output

1

Input

1

TX transceiver recovered parallel clock for video data.

Input

1

RX transceiver recovered parallel clock for video data.

Input

1

Input clock for reclock module (without external VCXO solution). This clock should be the same as fPLL reconfig_clk.

Input

1

Input

1

Reset signal from SDI RX core to indicate that the protocol is currently held in reset.

Input

1

Reset signal to reclock module (without external VCXO solution).

Input

20*N

Input

1

Data valid signal generated from SDI RX core.

Input

3

Received video standard from SDI RX core.

Input

N

Input

Input

1

Frame locked status signal from SDI RX core.

Input

1

Data valid signal generated from SDI TX core.

Input

1

Horizontal blanking interval timing signal extracted from SDI RX core.

Input

4

Received video transport format.

Input

1

Indication from SDI RX core that the receiver is receiving video rate at integer or fractional frame rate.

Output

20*N

Output

1

Data valid for the transmitter parallel data to SDI TX core.

Output

1

Transmitter TRS input to indicate that the current word is a TRS to SDI TX core.

Output

3

Indicates the desired transmit video standard to SDI TX core.

Output

1

Voltage up signal to Si516 to increase the voltage.

Output

1

Voltage down signal to Si516 to decrease the voltage.

Input

1

PLL lock status signal.

Input

32

Reconfiguration interface signals to fPLL Avalon-MM interface.

Input

1

Output

1

Output

1

Output

Output

11

Input

1

Reconfiguration clock. This clock should be sharing the same clock as reconfiguration management blocks.

Input

1

Reset signal. This reset should be sharing the same reset as reconfiguration management blocks.

Input

1

RX reconfiguration enable signal.

Input

1

TX reconfiguration enable signal.

Input

2

Indicates which channel to be reconfigured on RX. Always assign to 2'b00 for SDI case.

Input

2

Indicates which channel to be reconfigured on TX. Always assign to 2'b00 for SDI case.

Input

1

Reconfiguration Avalon-MM interfaces from RX reconfiguration management.

Input

1

Input

11

Input

32

Output

32

Output

1

Input

1

Reconfiguration Avalon-MM interfaces from TX reconfiguration management.

Input

1

Input

11

Input

32

Output

32

Output

1

Output

1

Reconfiguration Avalon-MM interfaces to transceiver.

Output

1

Output

11

Output

32

Input

32

Input

1

1

Input

1

Input

1

Calibration status signal from RX transceiver.

Input

1

Calibration status signal from TX transceiver.

Output

1

Calibration status signal to RX transceiver PHY reset control.

Output

1

Calibration status signal from TX transceiver PHY reset control.

Input

1

Clock signal. This clock must be connected to the tx_vid_clkout input signal on TX/Du top.

Input

1

Reset signal. This reset signal should be synchronized with the tx_vid_clkout clock signal from the TX/Du top.

Input

1

Enable this signal to generate 100% color-bar pattern. Disable to generate 75% color-bar pattern.

Input

1

Input

1

Enable this signal to generate pathological pattern.

Input

1

Enable this signal to generate blank signal.

Input

1

Enable this signal to generate bar with no color.

Input

1

Enable this signal to generate payload ID for segmented frame video format when generating 1080i50 or 1080i60 video.

Input

3

Indicates the desired transmit video standard. This input signal must match tx_vid_std on the TX/Du top.

Input

4

Indicates the desired transmit video format.

Input

1

Enable this signal to generate data streams with dual-link mapping.

Input

1

Enable this signal to generate payload ID for fractional frame rate video format. Disable to generate integer frame rate video format.

Output

20*S

Data output signal to be connected to the tx_vid_data input signal on the TX/Du top.

Output

1

Data valid output signal to be connected to the tx_vid_datavalid input signal on the TX/Du top.

Output

1

TRS output signal to be connected to the tx_vid_trs input signal on the TX/Du top.

Output

11*S

Line number output signal to be connected to the sdi_tx_ln input signal on the TX/Du top.

Output

20*S

Data output signal for link B (HD dual link).

Output

1

Data valid output signal for link B (HD dual link).

Output

1

TRS output signal for link B (HD dual link).

Output

11*S

Line number output signal to be connected to the sdi_tx_ln_b input signal on the TX/Du top.

Input

8*N

The payload ID output signal to be connected to sdi_tx_vpid_byte1 input signal on TX/Du top.

Input

8*N

The payload ID output signal to be connected to sdi_tx_vpid_byte2 input signal on TX/Du top.

Input

8*N

The payload ID output signal to be connected to sdi_tx_vpid_byte3 input signal on TX/Du top.

Input

8*N

The payload ID output signal to be connected to sdi_tx_vpid_byte4 input signal on TX/Du top.

Input

8*N

The payload ID output signal to be connected to sdi_tx_vpid_byte1_b input signal on TX/Du top.

Input

8*N

The payload ID output signal to be connected to sdi_tx_vpid_byte2_b input signal on TX/Du top.

Input

8*N

The payload ID output signal to be connected to sdi_tx_vpid_byte3_b input signal on TX/Du top.

Input

8*N

The payload ID output signal to be connected to sdi_tx_vpid_byte4_b input signal on TX/Du top.

Output

11*N

The line number output signal to be inserted with the payload ID. This signal must connect to sdi_tx_line_f0 input signal on TX/Du top.

Output

11*N

The line number output signal to be inserted with the payload ID. This signal must connect to sdi_tx_line_f1 input signal on TX/Du top.

Input

1

Clock signal to Avalon-MM interface.

Input

1

Clock signal to Parallel I/O (PIO) IP. This clock must share the same clock as video pattern generator.

Input

1

Reset signal to Avalon-MM interface.

Input

1

Input reset signals to a reset synchronizer which synchronizes the reset to the tx_clkout_in_clk clock domain.

Input

Input

1

Output reset from the reset synchronizer. This reset synchronizes to the tx_clkout_in_clk clock domain and connects to the video pattern generator’s input reset.

Output

12

Output control signal from PIO to control the video pattern generator.

Input

1

Clock signal to reset delay module.

Output

1

Signal that indicates the device has finished its initialization stage after a programmable delay, which is determined by the CNTR_BITS parameter.

OUTW_MULTP

1, 4

1

Defines the width of the output ports. Select 4 for a multi-rate design, otherwise select 1.

SD_BIT_WIDTH

10, 20

10

Defines the generated SD interface bit width. This value must match with the SD interface bit width parameter of the SDI II TX core in the same design.

TEST_GEN_ANC

0, 1

0

Select 1 to generate the ancillary data packet in output stream. The module inserts the embedded Data ID (DID) packet with 10’h242 if TEST_GEN_VPID is not enabled.

TEST_GEN_VPID

0, 1

0

Select 1 to generate the payload ID packet in output streams. The module inserts the embedded Data ID (DID) packet with 10’h241.