Intel Quartus Prime Pro Edition Settings File Reference Manual
Version Information
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 20.3 |
1. Intel Quartus Prime Pro Edition Settings File Reference Manual
1.1. Advanced I/O Timing Assignments
1.1.1. BOARD_MODEL_EBD_FAR_END
Specifies the far-end node to be used in the Electronic Board Description (EBD) path description.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name BOARD_MODEL_EBD_FAR_END -to <to> -entity <entity name> <value>
1.1.2. BOARD_MODEL_EBD_FILE_NAME
Specifies the Electronic Board Description (EBD) file that contains the path description for an I/O pin.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports wildcards.
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name BOARD_MODEL_EBD_FILE_NAME -to <to> -entity <entity name> <value>
1.1.3. BOARD_MODEL_EBD_SIGNAL_NAME
Specifies the Electronic Board Description (EBD) path description to be used with an I/O pin. You must specify the EBD file name.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name BOARD_MODEL_EBD_SIGNAL_NAME -to <to> -entity <entity name> <value>
1.1.4. BOARD_MODEL_FAR_C
Specifies, in farads, the board trace model far capacitance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_C -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_FAR_C -section_id <section identifier> <value>
1.1.5. BOARD_MODEL_FAR_DIFFERENTIAL_R
Specifies, in ohms, the board trace model far differential resistance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_FAR_DIFFERENTIAL_R -section_id <section identifier> <value>
1.1.6. BOARD_MODEL_FAR_PULLDOWN_R
Specifies, in ohms, the board trace model far pull-down resistance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_FAR_PULLDOWN_R -section_id <section identifier> <value>
1.1.7. BOARD_MODEL_FAR_PULLUP_R
Specifies, in ohms, the board trace model far pull-up resistance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_PULLUP_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_FAR_PULLUP_R -section_id <section identifier> <value>
1.1.8. BOARD_MODEL_FAR_SERIES_R
Specifies, in ohms, the board trace model far series resistance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_FAR_SERIES_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_FAR_SERIES_R -section_id <section identifier> <value>
1.1.9. BOARD_MODEL_NEAR_C
Specifies, in farads, the board trace model near capacitance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_C -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_C -section_id <section identifier> <value>
1.1.10. BOARD_MODEL_NEAR_DIFFERENTIAL_R
Specifies, in ohms, the board trace model near differential resistance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_DIFFERENTIAL_R -section_id <section identifier> <value>
1.1.11. BOARD_MODEL_NEAR_PULLDOWN_R
Specifies, in ohms, the board trace model near pull-down resistance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_PULLDOWN_R -section_id <section identifier> <value>
1.1.12. BOARD_MODEL_NEAR_PULLUP_R
Specifies, in ohms, the board trace model near pull-up resistance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_PULLUP_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_PULLUP_R -section_id <section identifier> <value>
1.1.13. BOARD_MODEL_NEAR_SERIES_R
Specifies, in ohms, the board trace model near series resistance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_SERIES_R -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_SERIES_R -section_id <section identifier> <value>
1.1.14. BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH
Specifies, in farads/inch, the board trace model near transmission line distributed capacitance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH -section_id <section identifier> <value>
1.1.15. BOARD_MODEL_NEAR_TLINE_LENGTH
Specifies, in inches, the board trace model near transmission line length.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_TLINE_LENGTH -section_id <section identifier> <value>
1.1.16. BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH
Specifies, in henrys/inch, the board trace model near transmission line distributed inductance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH -section_id <section identifier> <value>
1.1.17. BOARD_MODEL_TERMINATION_V
Specifies, in volts, the board trace model termination voltage.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TERMINATION_V -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_TERMINATION_V -section_id <section identifier> <value>
1.1.18. BOARD_MODEL_TLINE_C_PER_LENGTH
Specifies, in farads/inch, the board trace model far transmission line distributed capacitance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_TLINE_C_PER_LENGTH -section_id <section identifier> <value>
1.1.19. BOARD_MODEL_TLINE_LENGTH
Specifies, in inches, the board trace model far transmission line length.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_TLINE_LENGTH -section_id <section identifier> <value>
1.1.20. BOARD_MODEL_TLINE_L_PER_LENGTH
Specifies, in henrys/inch, the board trace model far transmission line distributed inductance.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -to <to> -entity <entity name> <value> set_global_assignment -name BOARD_MODEL_TLINE_L_PER_LENGTH -section_id <section identifier> <value>
1.1.21. OUTPUT_IO_TIMING_ENDPOINT
Specifies the node at which output I/O Timing ends.
Type
Enumeration
Values
- Far End
- Near End
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name OUTPUT_IO_TIMING_ENDPOINT -to <to> -entity <entity name> <value> set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT -entity <entity name> <value> set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT <value>
Default Value
Near End
1.1.22. OUTPUT_IO_TIMING_FAR_END_VMEAS
Specifies, in volts, the measurement voltage at the far-end.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -to <to> -entity <entity name> <value> set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS -section_id <section identifier> <value> set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS <value>
1.1.23. OUTPUT_IO_TIMING_NEAR_END_VMEAS
Specifies, in volts, the measurement voltage at the near-end.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
Syntax
set_instance_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -to <to> -entity <entity name> <value> set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS -section_id <section identifier> <value> set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS <value>
1.2. Analysis & Synthesis Assignments
1.2.1. ADV_NETLIST_OPT_ALLOWED
Specifies whether the Compiler should perform advanced netlist optimizations, such as gate-level retiming or physical synthesis, on the specified node or entity. If this option is set to 'Default', the Compiler duplicates, moves, or changes the synthesis of the node or entity, or allows register retiming during netlist optimization, only if doing so does not negatively affect the timing or performance of the design. If this option is set to 'Always Allow', the Compiler can alter the node or entity, even if doing so affects the timing or performance of the design. Intel does not recommend using this setting. If this option is set to 'Never Allow' the Compiler cannot alter the node or entity.
Type
Enumeration
Values
- Always Allow
- Default
- Never Allow
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ADV_NETLIST_OPT_ALLOWED -entity <entity name> <value> set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name adv_netlist_opt_allowed "always allow" -to reg
1.2.2. ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This option uses the setting specified in the Optimization Technique logic option.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP <value> set_instance_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name adv_netlist_opt_synth_wysiwyg_remap on set_instance_assignment -name adv_netlist_opt_synth_wysiwyg_remap on -to foo
See Also
Optimization Technique
1.2.3. AGGRESSIVE_MUX_AREA_OPTIMIZATION
Performs aggressive area optimization on multiplexers.
Type
Enumeration
Values
- Auto
- Off
- On
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AGGRESSIVE_MUX_AREA_OPTIMIZATION <value> set_global_assignment -name AGGRESSIVE_MUX_AREA_OPTIMIZATION -entity <entity name> <value> set_instance_assignment -name AGGRESSIVE_MUX_AREA_OPTIMIZATION -to <to> -entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name aggressive_mux_area_optimization off set_instance_assignment -name aggressive_mux_area_optimization on -to accel
1.2.4. ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION
Allows the Compiler to infer RAMs of any size, even if they don't meet the current minimum requirements.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION <value> set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -entity <entity name> <value> set_instance_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name allow_any_ram_size_for_recognition off set_instance_assignment -name allow_any_ram_size_for_recognition off -to foo
1.2.5. ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION
Allows the Compiler to infer ROMs of any size even if the ROMs do not meet the design's current minimum size requirements.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION <value> set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -entity <entity name> <value> set_instance_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name allow_any_rom_size_for_recognition off set_instance_assignment -name allow_any_rom_size_for_recognition off -to foo
1.2.6. ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION
Allows the Compiler to infer shift registers of any size even if they do not meet the design's current minimum size requirements.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION <value> set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION -entity <entity name> <value> set_instance_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name allow_any_shift_register_size_for_recognition off set_instance_assignment -name allow_any_shift_register_size_for_recognition off -to foo
1.2.7. ALLOW_CHILD_PARTITIONS
Specifies whether or not an instance or a section of design hierarchy can contain user partitions.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_CHILD_PARTITIONS -entity <entity name> <value> set_instance_assignment -name ALLOW_CHILD_PARTITIONS -to <to> -entity <entity name> <value>
Example
set_global_assignment -name allow_child_partitions off set_instance_assignment -name allow_child_partitions off -to "sub:inst"
1.2.8. ALLOW_POWER_UP_DONT_CARE
Causes registers that do not have a Power-Up Level logic option setting to power up with a don't care logic level (X). A don't care setting allows the Compiler to change the power-up level of a register to minimize the area of the design.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE <value>
Default Value
On
Example
set_global_assignment -name allow_power_up_dont_care off
See Also
Power-Up Level
1.2.9. ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES
Allows the Compiler to take shift registers from different hierarchies of the design and put them in the same RAM.
Type
Enumeration
Values
- Always
- Auto
- Off
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES <value> set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES -entity <entity name> <value> set_instance_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES -to <to> -entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name allow_shift_register_merging_across_hierarchies off set_instance_assignment -name allow_shift_register_merging_across_hierarchies off -to foo
See Also
Auto Shift Register Replacement
1.2.10. ALLOW_SYNCH_CTRL_USAGE
Allows the Compiler to utilize synchronous clear and/or synchronous load signals in normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE <value> set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE -entity <entity name> <value> set_instance_assignment -name ALLOW_SYNCH_CTRL_USAGE -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name allow_synch_ctrl_usage off set_instance_assignment -name allow_synch_ctrl_usage off -to foo
See Also
Force Use of Synchronous Clear Signals
1.2.11. ALTERA_A10_IOPLL_BOOTSTRAP
Turns on the A10 IOPLL bootstrap fix
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name ALTERA_A10_IOPLL_BOOTSTRAP <value>
1.2.12. AUTO_CLOCK_ENABLE_RECOGNITION
Allows the Compiler to find logic that feeds a register and move the logic to the register's clock enable input port.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION <value> set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -entity <entity name> <value> set_instance_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_clock_enable_replacement off set_instance_assignment -name auto_clock_enable_replacement off -to reg
1.2.13. AUTO_DSP_RECOGNITION
Allows the Compiler to find a multiply-accumulate function or a multiply-add function that can be replaced with a DSP block.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_DSP_RECOGNITION <value> set_global_assignment -name AUTO_DSP_RECOGNITION -entity <entity name> <value> set_instance_assignment -name AUTO_DSP_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_dsp_recognition off set_instance_assignment -name auto_dsp_recognition off -to foo
1.2.14. AUTO_ENABLE_SMART_COMPILE
Specifies whether the Signal Tap Logic Analyzer should perform a smart compilation if conditions exist in which Signal Tap with incremental routing is used.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name AUTO_ENABLE_SMART_COMPILE <value>
1.2.15. AUTO_OPEN_DRAIN_PINS
Allows the Compiler to automatically convert a tri-state buffer with a strong low data input into the equivalent open-drain buffer.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_OPEN_DRAIN_PINS <value> set_global_assignment -name AUTO_OPEN_DRAIN_PINS -entity <entity name> <value> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_open_drain_pins off set_instance_assignment -name auto_open_drain_pins off -to foo
1.2.16. AUTO_PARALLEL_SYNTHESIS
Option to enable/disable automatic parallel synthesis. This option can be used to speed up synthesis compile time by using multiple processors when available.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS <value>
Default Value
On
Example
set_global_assignment -name auto_parallel_synthesis on
1.2.17. AUTO_RAM_RECOGNITION
Allows the Compiler to find a set of registers and logic that can be replaced with the altsyncram or the lpm_ram_dp megafunction. Turning on this option may change the functionality of the design.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_RAM_RECOGNITION <value> set_global_assignment -name AUTO_RAM_RECOGNITION -entity <entity name> <value> set_instance_assignment -name AUTO_RAM_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_ram_recognition off set_instance_assignment -name auto_ram_recognition off -to foo
1.2.18. AUTO_RESOURCE_SHARING
Allows the Compiler to share hardware resources among many similar, but mutually exclusive, operations in your HDL source code. If you enable this option, the Compiler will merge compatible addition, subtraction, and multiplication operations. By merging operations, this may reduce the area required by your design. Because resource sharing introduces extra muxing and control logic on each shared resource, it may negatively impact the final fmax of your design.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_RESOURCE_SHARING <value> set_global_assignment -name AUTO_RESOURCE_SHARING -entity <entity name> <value> set_instance_assignment -name AUTO_RESOURCE_SHARING -to <to> -entity <entity name> <value>
Default Value
Off
1.2.19. AUTO_ROM_RECOGNITION
Allows the Compiler to find logic that can be replaced with the altsyncram or the lpm_rom megafunction. Turning on this option may change the power-up state of the design.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_ROM_RECOGNITION <value> set_global_assignment -name AUTO_ROM_RECOGNITION -entity <entity name> <value> set_instance_assignment -name AUTO_ROM_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name auto_rom_recognition off set_instance_assignment -name auto_rom_recognition off -to foo
1.2.20. AUTO_SHIFT_REGISTER_RECOGNITION
Allows the Compiler to find a group of shift registers of the same length that can be replaced with the altshift_taps megafunction. The shift registers must all use the same clock and clock enable signals, must not have any other secondary signals, and must have equally spaced taps that are at least three registers apart.
Type
Enumeration
Values
- Always
- Auto
- Off
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION <value> set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -entity <entity name> <value> set_instance_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name auto_shift_register_recognition off set_instance_assignment -name auto_shift_register_recognition off -to foo
1.2.21. BARRELSHIFTER_CARRY_CHAIN_PACKING
Allows the Compiler to reduce the number of logic elements required by implementing barrelshifters in carry chains. This option repacks barrelshifters more efficiently for area, but may negatively affect timing. With the 'Auto' setting synthesis will make the trade-off between area and speed. Setting to 'Off' will disable this optimization, and setting to 'On' will enable it for all barrelshifters.
Type
Enumeration
Values
- Auto
- Off
- On
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name BARRELSHIFTER_CARRY_CHAIN_PACKING <value> set_global_assignment -name BARRELSHIFTER_CARRY_CHAIN_PACKING -entity <entity name> <value> set_instance_assignment -name BARRELSHIFTER_CARRY_CHAIN_PACKING -to <to> -entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name barrelshifter_carry_chain_packing off set_instance_assignment -name barrelshifter_carry_chain_packing on -to accel
1.2.22. BLOCK_DESIGN_NAMING
Specify the naming scheme used for the block design. This option is ignored if it is assigned to anything other than a design entity.
Type
Enumeration
Values
- Auto
- MaxPlusII
- QuartusII
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name BLOCK_DESIGN_NAMING -entity <entity name> <value> set_instance_assignment -name BLOCK_DESIGN_NAMING -to <to> -entity <entity name> <value> set_global_assignment -name BLOCK_DESIGN_NAMING <value>
Default Value
Auto
Example
set_global_assignment -name block_design_naming MaxPlusII set_instance_assignment -name block_design_naming MaxPlusII -to top
1.2.23. BOARD
Specifies the board or development kit to use.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name BOARD <value>
1.2.24. DEVICE_FILTER_PACKAGE
Package filter for available devices.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_PACKAGE <value>
Default Value
Any
1.2.25. DEVICE_FILTER_PIN_COUNT
Pin count filter for available devices.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_PIN_COUNT <value>
Default Value
Any
1.2.26. DEVICE_FILTER_SPEED_GRADE
Speed grade filter for available devices.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE <value>
Default Value
Any
1.2.27. DEVICE_FILTER_VOLTAGE
Voltage filter for available devices.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name DEVICE_FILTER_VOLTAGE <value>
1.2.28. DISABLE_DSP_NEGATE_INFERENCING
Allow you to specify whether to use the negate port on an inferred DSP block.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING -entity <entity name> <value> set_instance_assignment -name DISABLE_DSP_NEGATE_INFERENCING -to <to> -entity <entity name> <value> set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING <value>
Default Value
Off
Example
set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING ON set_instance_assignment -name DISABLE_DSP_NEGATE_INFERENCING OFF -to dps1
1.2.29. DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES
Specifies whether registers that are in different hierarchies are allowed to be merged if their inputs are the same.
Type
Enumeration
Values
- Auto
- Off
- On
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES <value>
Default Value
Auto
1.2.30. DISABLE_REGISTER_POWER_UP_INITIALIZATION
Specifies whether the Assembler generates a bit stream with register power-up initialization.
Old Name
DISABLE_REGISTER_POWERUP_INITIALIZATION
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name DISABLE_REGISTER_POWER_UP_INITIALIZATION <value>
Default Value
Off
1.2.31. DONT_MERGE_REGISTER
When set to On, this option prevents the specified register from merging with other registers, and prevents other registers from merging with the specified register.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports Fitter wildcards.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name DONT_MERGE_REGISTER -entity <entity name> <value> set_instance_assignment -name DONT_MERGE_REGISTER -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name dont_merge_register on -to foo
1.2.32. DSE_SYNTH_EXTRA_EFFORT_MODE
Specifies the Design Space Explorer synthesis extra effort mode.
Type
Enumeration
Values
- MODE_1
- MODE_2
- MODE_3
- MODE_4
- MODE_5
- MODE_DEFAULT
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name DSE_SYNTH_EXTRA_EFFORT_MODE <value>
1.2.33. DSP_BLOCK_BALANCING
Allows you to control the conversion of certain DSP block slices during DSP block balancing.
Type
Enumeration
Values
- Auto
- DSP blocks
- Logic Elements
- Off
- Simple 18-bit Multipliers
- Simple Multipliers
- Width 18-bit Multipliers
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name DSP_BLOCK_BALANCING -entity <entity name> <value> set_instance_assignment -name DSP_BLOCK_BALANCING -to <to> -entity <entity name> <value> set_global_assignment -name DSP_BLOCK_BALANCING <value>
Default Value
Auto
Example
set_global_assignment -name dsp_block_balancing "dsp blocks" set_instance_assignment -name dsp_block_balancing "logic elements" -to mult0
1.2.34. DUPLICATE_HIERARCHY_DEPTH
Pushes the last register and some number of registers that precede it in a chain of simple registers down the hierarchy tree of the modules it fans out to, creating a tree with duplicates for each instance at every level of the hierarchy. The registers in the chain must already be present in the design, with no logic in between them and no other fanins/fanouts between them.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name duplicate_hierarchy_depth -to last_reg_in_chain 2
1.2.35. EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
Specifies the third-party EDA tool used for design entry/synthesis
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL <value> set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL -entity <entity name> <value>
Default Value
<None>
1.2.36. EDA_INPUT_DATA_FORMAT
Specifies the format of the input data read from other EDA design entry/synthesis tools.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_INPUT_DATA_FORMAT -section_id <section identifier> <value> set_global_assignment -name EDA_INPUT_DATA_FORMAT -entity <entity name> -section_id <section identifier> <value>
Default Value
NONE, requires section identifier
1.2.37. EDA_INPUT_GND_NAME
Specifies the global high signal used in the files generated by the EDA synthesis tool, which is GND.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_INPUT_GND_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_INPUT_GND_NAME -entity <entity name> -section_id <section identifier> <value>
Default Value
GND, requires section identifier
1.2.38. EDA_INPUT_VCC_NAME
Specifies the global power-down signal.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_INPUT_VCC_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_INPUT_VCC_NAME -entity <entity name> -section_id <section identifier> <value>
Default Value
VCC, requires section identifier
1.2.39. EDA_LMF_FILE
Specifies the default Library Mapping File (.lmf) for the current compilation.
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_LMF_FILE -section_id <section identifier> <value> set_global_assignment -name EDA_LMF_FILE -entity <entity name> -section_id <section identifier> <value>
1.2.40. EDA_RUN_TOOL_AUTOMATICALLY
Runs the third-party EDA tool automatically from Quartus Prime when a design is compiled.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -section_id <section identifier> <value> set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.2.41. EDA_SHOW_LMF_MAPPING_MESSAGES
Determines whether to display messages describing the mappings used in the Library Mapping File.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -section_id <section identifier> <value> set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.2.42. EDA_VHDL_LIBRARY
Specifies the logical name of a user-defined VHDL design library : physical name.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name EDA_VHDL_LIBRARY -to <to> -section_id <section identifier> <value> set_instance_assignment -name EDA_VHDL_LIBRARY -to <to> -entity <entity name> -section_id <section identifier> <value>
1.2.43. ENABLE_FORMAL_VERIFICATION
Allows the Compiler to write scripts that can be used to run OneSpin formal verification tool. These are the only supported scripts used for formal verification.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ENABLE_FORMAL_VERIFICATION <value>
Default Value
Off
Example
set_global_assignment -name enable_formal_verification on
1.2.44. ENABLE_FPGA_TAMPER_DETECTION
Enable FPGA tamper detection.
Type
Boolean
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_FPGA_TAMPER_DETECTION <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_FPGA_TAMPER_DETECTION ON
1.2.45. ENABLE_STATE_MACHINE_INFERENCE
Allows the Compiler to infer state machines from Verilog/Vhdl Design Files. The Compiler optimizes state machines using special techniques to reduce area and/or improve performance. If set to Off, the Compiler extracts and optimizes state machines in Verilog/VHDL Design Files as regular logic.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE <value>
Default Value
On
Example
set_global_assignment -name enable_state_machine_inference on
1.2.46. FAMILY
Specifies the device family to use for compilation.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name FAMILY <value>
Default Value
Cyclone 10 GX
1.2.47. FORCE_CLOCK_ENABLE_INFERENCE
Directs the Compiler to aggressively infer clock enables on the specified registers. Turning on this option helps to infer clock enables on registers even the compiler would not have otherwise done so. It might negatively impact the fitting since the number of clock enable signals available in a LAB is limited.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name FORCE_CLOCK_ENABLE_INFERENCE -entity <entity name> <value> set_instance_assignment -name FORCE_CLOCK_ENABLE_INFERENCE -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name force_clock_enable_inference on -to foo
See Also
Allow Synchronous Control Signals
1.2.48. FORCE_SYNCH_CLEAR
Forces the Compiler to utilize synchronous clear signals in normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might negatively impact the fitting since synchronous control signals are shared by all the logic cells in a LAB.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name FORCE_SYNCH_CLEAR <value> set_global_assignment -name FORCE_SYNCH_CLEAR -entity <entity name> <value> set_instance_assignment -name FORCE_SYNCH_CLEAR -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name force_synch_clear on set_instance_assignment -name force_synch_clear on -to foo
See Also
Allow Synchronous Control Signals
1.2.49. FRACTAL_SYNTHESIS
Allows the Compiler to apply dense packing to arithmetic blocks, minimizing the area of the design.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name FRACTAL_SYNTHESIS <value> set_global_assignment -name FRACTAL_SYNTHESIS -entity <entity name> <value> set_instance_assignment -name FRACTAL_SYNTHESIS -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_instance_assignment -name fractal_synthesis on -entity multiplier
1.2.50. HDL_INITIAL_FANOUT_LIMIT
Directs Integrated Synthesis to check the initial fan-out of each net in the netlist immediately after elaboration but prior to any netlist optimizations. If the fan-out for a net exceeds the specified limit, then Integrated Synthesis will issue a warning.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name HDL_INITIAL_FANOUT_LIMIT -entity <entity name> <value> set_instance_assignment -name HDL_INITIAL_FANOUT_LIMIT -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name hdl_initial_fanout_limit 100 -to foo
1.2.51. HDL_MESSAGE_LEVEL
Specifies the type of HDL messages you want to view, including messages that display processing errors in the HDL source code. 'Level1' allows you to view only the most important HDL messages. 'Level2' allows you to view most HDL messages, including warning and information based messages. 'Level3' allows you to view all HDL messages, including warning and information based messages and alerts about potential design problems or lint errors.
Type
Enumeration
Values
- Level1
- Level2
- Level3
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name HDL_MESSAGE_LEVEL <value>
Default Value
Level2
1.2.52. HDL_MESSAGE_OFF
Specifies the list of HDL message ids you want to turn off for this project.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
INTEGER_RANGE
10000, 11000
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name HDL_MESSAGE_OFF <value>
1.2.53. HDL_MESSAGE_ON
Specifies the list of HDL message ids you want to turn on for this project.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
INTEGER_RANGE
10000, 11000
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name HDL_MESSAGE_ON <value>
1.2.54. HPS_PARTITION
Specifies whether an entity or instance is a special-purpose partition that models the internals of the Hard Processor System (HPS).
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name HPS_PARTITION -entity <entity name> <value> set_instance_assignment -name HPS_PARTITION -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name hps_partition on -entity hps
1.2.55. IGNORE_GLOBAL_BUFFERS
Ignores GLOBAL buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual GLOBAL buffer or a design entity containing GLOBAL buffers.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_GLOBAL_BUFFERS <value> set_global_assignment -name IGNORE_GLOBAL_BUFFERS -entity <entity name> <value> set_instance_assignment -name IGNORE_GLOBAL_BUFFERS -to <to> -entity <entity name> <value>
Default Value
Off
1.2.56. IGNORE_LCELL_BUFFERS
Ignores LCELL buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual LCELL buffer or a design entity containing LCELL buffers.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_LCELL_BUFFERS <value> set_global_assignment -name IGNORE_LCELL_BUFFERS -entity <entity name> <value> set_instance_assignment -name IGNORE_LCELL_BUFFERS -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name ignore_lcell_buffers on set_instance_assignment -name ignore_lcell_buffers on -to foo
1.2.57. IGNORE_MAX_FANOUT_ASSIGNMENTS
Directs the Compiler to ignore the Maximum Fan-Out Assignments on a node, an entity, or the whole design. One can remove the Maximum Fan-Out Assignments from the project but it is inconvenient/impossible as some assignments are embedded in the HDL sources.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS <value> set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS -entity <entity name> <value> set_instance_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS -to <to> -entity <entity name> <value>
Default Value
Off
1.2.58. IGNORE_REGISTER_POWER_UP_INITIALIZATION
This allows the compiler to ignore the power-up condition of this register from what was specified in the RTL. Doing so gives more freedom to the tool to optimize this register, in partilcar for retiming.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name IGNORE_REGISTER_POWER_UP_INITIALIZATION -entity <entity name> <value> set_instance_assignment -name IGNORE_REGISTER_POWER_UP_INITIALIZATION -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name ignore_register_power_up_initialization on -to r
1.2.59. IGNORE_SOFT_BUFFERS
Ignores SOFT buffers that are instantiated in the design. This option is ignored if it is applied to anything other than an individual SOFT buffer or a design entity containing SOFT buffers.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name IGNORE_SOFT_BUFFERS <value> set_global_assignment -name IGNORE_SOFT_BUFFERS -entity <entity name> <value> set_instance_assignment -name IGNORE_SOFT_BUFFERS -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name ignore_soft_buffers off set_instance_assignment -name ignore_soft_buffers off -to foo
1.2.60. IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF
Instructs Analysis & Synthesis to ignore all translate_off/synthesis_off synthesis directives in your Verilog and VHDL design files. You can use this option to disable these synthesis directives and include previously ignored code during elaboration.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF <value>
Default Value
Off
Example
set_global_assignment -name ignore_translate_off_and_synthesis_off on
1.2.61. IMPLEMENT_AS_CLOCK_ENABLE
Specifies that this node should function as a clock enable signal for one or more registers.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_instance_assignment -name IMPLEMENT_AS_CLOCK_ENABLE -to <to> -entity <entity name> <value>
1.2.62. IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL
Implements the output of a primitive in a logic cell. You can apply this option to a logic function that would not ordinarily be implemented in a logic cell, typically a combinatorial function such as an AND2 gate. Implementing the output of a primitive a logic cell makes it possible to observe its output in simulation and timing analysis. However, because an additional logic cell is used, overall device utilization will increase. This option does not insert an additional logic cell on a function that is already implemented in a logic cell, such as a flipflop. This option is ignored if it is applied to anything other than a primitive.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_instance_assignment -name IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name implement_as_output_of_logic_cell on -to foo
1.2.63. INFER_RAMS_FROM_RAW_LOGIC
Instructs the Compiler to infer RAM from registers and multiplexers. Some HDL patterns that differ from Intel FPGA RAM templates are initially converted into logic. However, these structures function as RAM and, because of that, the Compiler may create an altsyncram megafunction instance for them at a later stage when this assignment is on. With this assignment is turned on, the Compiler may use more device RAM resources and less LABs.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC <value> set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC -entity <entity name> <value> set_instance_assignment -name INFER_RAMS_FROM_RAW_LOGIC -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name infer_rams_from_raw_logic off set_instance_assignment -name infer_rams_from_raw_logic off -to foo
1.2.64. IP_SEARCH_PATHS
Specifies the IP search paths specific to the project.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name IP_SEARCH_PATHS <value>
1.2.65. MAX_BALANCING_DSP_BLOCKS
Allows you to specify the maximum number of DSP blocks that the DSP block balancer will assume exist in the current device for each partition. This option overrides the usual method of using the maximum number of DSP blocks the current device supports.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS <value> set_instance_assignment -name MAX_BALANCING_DSP_BLOCKS -to <to> -entity <entity name> <value>
Default Value
-1 (Unlimited)
Example
set_global_assignment -name max_balancing_dsp_blocks 4 set_instance_assignment -name max_balancing_dsp -to "my_partition_root_entity:my_partition_root_entity_inst"
1.2.66. MAX_FANOUT
Directs the Compiler to control the number of destinations the specified node feeds so the fan-out count does not exceed the value specified as the maximum number of fan-out allowed from the node.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_FANOUT -entity <entity name> <value> set_instance_assignment -name MAX_FANOUT -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name max_fanout 10 -to foo
1.2.67. MAX_LABS
Allows you to specify the maximum number of LABs that Analysis & Synthesis should try to utilize for a device. This option overrides the usual method of using the maximum number of LABs the current device supports, when the value is non-negative and is less than the maximum number of LABs available on the current device.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_LABS <value> set_instance_assignment -name MAX_LABS -to <to> -entity <entity name> <value>
Default Value
-1 (Unlimited)
Example
set_global_assignment -name max_labs 100
1.2.68. MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS
Allows you to specify the maximum number of registers that Analysis & Synthesis can use for conversion of uninferred RAMs. You can use this option as a project-wide option or on a specific partition by setting the assignment on the instance name of the partition root. The assignment on a partition overrides the global assignment (if any) for that particular partition. This option prevents synthesis from causing long compilations and running out of memory when many registers are used for uninferred RAMs. Instead of continuing the compilation, the Quartus Prime software issues an error and exits.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS <value> set_instance_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS -to <to> -entity <entity name> <value>
Default Value
-1 (Unlimited)
Example
set_global_assignment -name max_number_of_registers_from_uninferred_rams 2048
1.2.69. MAX_RAM_BLOCKS_M4K
Allows you to specify the maximum number of M4K,M9K,M20K,or M10K memory blocks that the Compiler may use for a device. This option overrides the usual method of using the maximum number of M4K,M9K,M20K, or M10K memory blocks the current device supports, when the value is non-negative and is less than the maximum number of M4K,M9K,M20K, or M10K memory blocks available on the current device.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MAX_RAM_BLOCKS_M4K <value> set_instance_assignment -name MAX_RAM_BLOCKS_M4K -to <to> -entity <entity name> <value>
Default Value
-1 (Unlimited)
Example
set_global_assignment -name max_ram_blocks_m4k 4
See Also
Maximum Number of M512 Memory Blocks Maximum Number of M-RAM Memory Blocks
1.2.70. MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE
Allows you to specify whether you want the Timing Analyzer to evaluate timing constraints between the write and the read operation of the MLAB memory block. Performing a write and read operation simultaneously at the same address might result in metastability because no timing constraints between those operations exist by default. Turning on this option introduces timing constraints between the write and read operation on the MLAB memory block and thereby avoids metastability issues; however, turning on this option degrades the performance of the MLAB memory blocks. If your design does not perform write and read operations simulataneously at the same address you do not need to set this option.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE -entity <entity name> <value> set_instance_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE -to <to> -entity <entity name> <value> set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE <value>
Default Value
Off
1.2.71. MUX_RESTRUCTURE
Allows the Compiler to reduce the number of logic elements required to implement multiplexers in a design. This option is useful if your design contains buses of fragmented multiplexers. This option repacks multiplexers more efficiently for area, allowing the design to implement multiplexers with a reduced number of logic elements. You can select the 'On' setting to minimize your design area; it will decrease logic element usage but may negatively affect design clock speed (fMAX). You can select the 'Off' to disable multiplexer restructuring; it does not decrease logic element usage and does not affect design clock speed (fMAX). You may select 'Auto' setting to allow the Quartus Prime software to determine whether multiplexer restructuring should be enabled. The Quartus Prime software uses other synthesis settings, for example, the Optimization Technique option, to determine if multiplexer restructuring should be applied to the design; the 'Auto' setting will decrease logic element usage but may negatively affect design clock speed (fMAX).
Type
Enumeration
Values
- Auto
- Off
- On
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name MUX_RESTRUCTURE <value> set_global_assignment -name MUX_RESTRUCTURE -entity <entity name> <value> set_instance_assignment -name MUX_RESTRUCTURE -to <to> -entity <entity name> <value>
Default Value
Auto
Example
set_global_assignment -name mux_restructure off set_instance_assignment -name mux_restructure on -to accel
1.2.72. NOT_GATE_PUSH_BACK
Allows the Compiler to push an inversion (that is, a NOT gate) back through a register and implement it on that register's data input if it is necessary to implement the design. If this option is turned on, a register may power up to an active-high state, so it may need to be explicitly cleared during initial operation of the device. This option is ignored if it is applied to anything other than an individual register or a design entity containing registers. If it is applied to an output pin that is directly fed by a register, it is automatically transferred to that register.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name NOT_GATE_PUSH_BACK -entity <entity name> <value> set_instance_assignment -name NOT_GATE_PUSH_BACK -to <to> -entity <entity name> <value> set_global_assignment -name NOT_GATE_PUSH_BACK <value>
Default Value
On
Example
set_global_assignment -name not_gate_push_back off set_instance_assignment -name not_gate_push_back off -to reg
1.2.73. NUMBER_OF_INVERTED_REGISTERS_REPORTED
Allows you to specify the maximum number of inverted registers that the Synthesis Report should display.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED <value>
Default Value
100
Example
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 200
1.2.74. NUMBER_OF_PROTECTED_REGISTERS_REPORTED
Allows you to specify the maximum number of protected registers that the Synthesis Report should display.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED <value>
Default Value
100
Example
set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 200
1.2.75. NUMBER_OF_REMOVED_REGISTERS_REPORTED
Allows you to specify the maximum number of removed registers that the Synthesis Report should display.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED <value>
Default Value
5000
Example
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 200
1.2.76. NUMBER_OF_SWEPT_NODES_REPORTED
Allows you to specify the maximum number of swept nodes that the Synthesis Report displays. A swept node is any node which was eliminated from your design because the Quartus Prime software found the node to be unnecessary.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED <value>
Default Value
5000
Example
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 200
1.2.77. OCP_HW_EVAL
Enables or disables Intel FPGA IP Evaluation Mode feature.
Type
Enumeration
Values
- Disable
- Enable
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name OCP_HW_EVAL <value>
Default Value
Enable
1.2.78. OPTIMIZATION_TECHNIQUE
Specifies the overall optimization goal for Analysis & Synthesis: attempt to maximize performance, minimize logic usage, or balance high performance with minimal logic usage.
Old Name
Optimization Technique -- Stratix IV
Type
Enumeration
Values
- Area
- Balanced
- Speed
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name OPTIMIZATION_TECHNIQUE <value> set_global_assignment -name OPTIMIZATION_TECHNIQUE -entity <entity name> <value> set_instance_assignment -name OPTIMIZATION_TECHNIQUE -to <to> -entity <entity name> <value>
Default Value
Balanced
Example
set_global_assignment -name optimization_technique speed
1.2.79. OPTIMIZE_POWER_DURING_SYNTHESIS
Controls the power-driven compilation setting of Analysis & Synthesis. This option determines how aggressively Analysis & Synthesis optimizes the design for power. If this option is set to 'Off', Analysis & Synthesis does not perform any power optimizations. If this option is set to 'Normal compilation', Analysis & Synthesis performs power optimizations as long as they are not expected to reduce design performance. When this option is set to 'Extra effort', Analysis & Synthesis will perform additional power optimizations which may reduce design performance.
Type
Enumeration
Values
- Extra effort
- Normal compilation
- Off
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS <value> set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS -entity <entity name> <value> set_instance_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS -to <to> -entity <entity name> <value>
Default Value
Normal compilation
Example
set_global_assignment -name optimize_power_during_synthesis off
1.2.80. PARAMETER
Assigns an attribute that determines the logic created or used to implement the function, for example, the width of a bus. Parameters are characteristics that determine the size, behavior, or silicon implementation of a function. Parameter values are inherited from project defaults or higher hierarchical levels unless you make explicit assignments to individual nodes. Parameters are also overridden by explicit logic synthesis and fitting options.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_parameter <value> set_parameter -entity <entity name> <value>
1.2.81. PHYSICAL_SHIFT_REGISTER_INFERENCE
Allows the Compiler perform placement-driven shift register inference it in Fitter instead of performing shift register inference in Synthesis.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name PHYSICAL_SHIFT_REGISTER_INFERENCE <value>
Example
set_global_assignment -name physical_shift_register_inference off
1.2.82. POWER_UP_LEVEL
Causes a register to power up with the specified logic level, either High (1) or Low (0). If this option is specified for an input pin, it is automatically transferred to the register that is driven by the pin if the following conditions are present: (1) there is no intervening logic, other than inversion, between the pin and the register; (2) the input pin drives the data input of the register; and (3) the input pin does not fan-out to any other logic. If this option is specified for an output or bidirectional pin, it is automatically transferred to the register that feeds the pin if: (1) there is no intervening logic, other than inversion, between the register and the pin; and (2) the register does not fan-out to any other logic. You can assign this option to any register, or to a pin with any logic configuration other than those described above. You can also assign this option to a design entity containing registers if you want to set the power level for all registers in the design entity. In order for the register to power up with the specified logic level, the Compiler may perform NOT Gate Push-Back on the register.
Type
Enumeration
Values
- High
- Low
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name POWER_UP_LEVEL -entity <entity name> <value> set_instance_assignment -name POWER_UP_LEVEL -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name power_up_level low -to foo
See Also
Power-Up Don't Care
1.2.83. PRESERVE_FANOUT_FREE_NODE
Prevents a register that has no fan-out from being removed during synthesis.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name preserve_fanout_free_node on -to reg
1.2.84. PRESERVE_FANOUT_FREE_WYSIWYG
Prevents a user-instantiated wysiwyg or primitive from being removed when it has no fanout.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name PRESERVE_FANOUT_FREE_WYSIWYG -entity <entity name> <value> set_instance_assignment -name PRESERVE_FANOUT_FREE_WYSIWYG -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name preserve_fanout_free_wysiwyg on -to wys
1.2.85. PRESERVE_REGISTER
Prevents a register from minimizing away during synthesis and prevents sequential netlist optimizations. Sequential netlist optimizations can eliminate redundant registers and registers with constant drivers.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports Fitter wildcards.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name PRESERVE_REGISTER -entity <entity name> <value> set_instance_assignment -name PRESERVE_REGISTER -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name preserve_register on -to foo
1.2.86. PRESERVE_REGISTER_SYN_ONLY
Prevents a register from minimizing away during synthesis. This does not affect retiming or other optimizations in the fitter.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports Fitter wildcards.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name PRESERVE_REGISTER_SYN_ONLY -entity <entity name> <value> set_instance_assignment -name PRESERVE_REGISTER_SYN_ONLY -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name preserve_register_syn_only on -to foo
1.2.87. PRPOF_ID
Specifies whether a register is a unique partial reconfiguration bitstream identifier. The same identifier value will be used to generate the partial reconfiguration bitstream.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name PRPOF_ID -entity <entity name> <value> set_instance_assignment -name PRPOF_ID -to <to> -entity <entity name> <value> set_global_assignment -name PRPOF_ID <value>
Default Value
Off
Example
set_instance_assignment -name prpof_id on -to reg
1.2.88. QUICK_ELAB_TILE_IP
Specifies that an entity is to be reported as a tile IP by the quick elaboration flow. The string value represents the tile type.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name QUICK_ELAB_TILE_IP -entity <entity name> <value> set_instance_assignment -name QUICK_ELAB_TILE_IP -to <to> -entity <entity name> <value>
1.2.89. RAMSTYLE_ATTRIBUTE
Sets the ramstyle attribute of a shift register, RAM, or ROM.
Type
Enumeration
Values
- M10K
- M144K
- M20K
- M4K
- M512
- M9K
- MEGARAM
- MLAB
- auto
- logic
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name RAMSTYLE_ATTRIBUTE -entity <entity name> <value> set_instance_assignment -name RAMSTYLE_ATTRIBUTE -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name ramstyle_attribute M512 -to foo
1.2.90. RBCGEN_CRITICAL_WARNING_TO_ERROR
To convert Quartus Prime critical warning to error.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR <value>
Default Value
On
1.2.91. REMOVE_DUPLICATE_REGISTERS
Removes a register if it is identical to another register. If two registers generate the same logic, the second one will be deleted and the first one will be made to fan out to the second one's destinations. Also, if the deleted register has different logic option assignments, they will be ignored. This option is useful if you wish to prevent the Compiler from removing duplicate registers that you have used deliberately. You can do this by setting the option to Off. This option is ignored if it is applied to anything other than an individual register or a design entity containing registers.
Old Name
DUPLICATE_REGISTER_EXTRACTION
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS <value> set_global_assignment -name REMOVE_DUPLICATE_REGISTERS -entity <entity name> <value> set_instance_assignment -name REMOVE_DUPLICATE_REGISTERS -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name remove_duplicate_registers off set_instance_assignment -name remove_duplicate_registers off -to foo
1.2.92. REMOVE_REDUNDANT_LOGIC_CELLS
Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option on optimizes a circuit for area and speed. This option is ignored if it is applied to anything other than a design entity.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -entity <entity name> <value> set_instance_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS -to <to> -entity <entity name> <value> set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS <value>
Default Value
Off
Example
set_global_assignment -name remove_redundant_logic_cells on set_instance_assignment -name remove_redundant_logic_cells on -to node
1.2.93. REPORT_ENTITY_UTILIZATION_TO_ASCII_PRO
Specifies whether panels of Resource Utilization by Entity for each partition should be printed to the ascii version of the synthesis report.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_ENTITY_UTILIZATION_TO_ASCII_PRO <value>
Default Value
On
1.2.94. REPORT_PARAMETER_SETTINGS_PRO
Specifies whether the synthesis report should include the panels in the Parameter Settings by Entity Instance folder
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO <value>
Default Value
On
1.2.95. REPORT_PARAMETER_SETTINGS_TO_ASCII_PRO
Specifies whether the Parameter Settings by Entity Instance folder should be printed to the ascii version of the synthesis report.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_PARAMETER_SETTINGS_TO_ASCII_PRO <value>
Default Value
On
1.2.96. REPORT_PR_INITIAL_VALUES_AS_ERROR
Allows you to flag explicitly defined initial values found in PR partitions as Errors instead of Warnings.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_PR_INITIAL_VALUES_AS_ERROR <value>
Default Value
Off
Example
set_global_assignment -name REPORT_PR_INITIAL_VALUES_AS_ERROR ON
1.2.97. REPORT_SOURCE_ASSIGNMENTS_PRO
Specifies whether the synthesis report should include the panels in the Source Assignments folder
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO <value>
Default Value
On
1.2.98. REPORT_SOURCE_ASSIGNMENTS_TO_ASCII_PRO
Specifies whether the Source Assignments folder should be printed to the ascii version of the synthesis report.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_TO_ASCII_PRO <value>
Default Value
On
1.2.99. RESYNTHESIS_OPTIMIZATION_EFFORT
Specifies whether the resynthesis tool should focus on fmax or area during resynthesis.
Type
Enumeration
Values
- Low
- Normal
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT -section_id <section identifier> <value> set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT -entity <entity name> -section_id <section identifier> <value>
Default Value
Normal, requires section identifier
1.2.100. RESYNTHESIS_PHYSICAL_SYNTHESIS
Specifies the physical synthesis level for resynthesis.
Type
Enumeration
Values
- ADVANCED
- Normal
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS -section_id <section identifier> <value> set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS -entity <entity name> -section_id <section identifier> <value>
Default Value
Normal, requires section identifier
1.2.101. RESYNTHESIS_RETIMING
Specifies the paths on which retiming will be performed: all paths, register-to-register paths only, or none.
Type
Enumeration
Values
- CORE
- Full
- Off
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name RESYNTHESIS_RETIMING -section_id <section identifier> <value> set_global_assignment -name RESYNTHESIS_RETIMING -entity <entity name> -section_id <section identifier> <value>
Default Value
FULL, requires section identifier
1.2.102. SAFE_STATE_MACHINE
Tells the compiler to implement state machines that can recover gracefully from an illegal state.
Type
Enumeration
Values
- Auto
- Never
- On
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SAFE_STATE_MACHINE -entity <entity name> <value> set_instance_assignment -name SAFE_STATE_MACHINE -to <to> -entity <entity name> <value> set_global_assignment -name SAFE_STATE_MACHINE <value>
Default Value
Auto
Example
set_global_assignment -name safe_state_machine on set_instance_assignment -name safe_state_machine on -to foo
See Also
State Machine Processing Extract Verilog State Machines Extract VHDL State Machines
1.2.103. SAVE_DISK_SPACE
Saves disk space by reducing the number of node names available for entering assignments, simulation, timing analysis, reporting, etc.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SAVE_DISK_SPACE <value>
Default Value
On
1.2.104. SEARCH_PATH
Specifies the path name of a user-defined library.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name SEARCH_PATH <value>
1.2.105. SECONDARY_TOP_LEVEL_ENTITY
Specifies the name of an entity that needs to be considered as top-level entity for analysis and elaboration but is not the main top-level entity.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECONDARY_TOP_LEVEL_ENTITY <value>
1.2.106. SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL
Allows the Compiler to find a group of shift registers of the same length that can be replaced with the altshift_taps megafunction. The shift registers must all use the same aclr signals, must not have any other secondary signals, and must have equally spaced taps that are at least three registers apart. To use this option, you must turn on the Auto Shift Register Replacement logic option.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL <value> set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL -entity <entity name> <value> set_instance_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name shift_register_recognition_aclr_signal off set_instance_assignment -name shift_register_recognition_aclr_signal off -to foo
1.2.107. SIZE_OF_IGNORED_POWER_UP_REPORT
Allows you to specify the maximum number of registers with ignored power-up settings reported in synthesis report.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SIZE_OF_IGNORED_POWER_UP_REPORT <value>
Default Value
500
Example
set_global_assignment -name SIZE_OF_IGNORED_POWER_UP_REPORT 200
1.2.108. SIZE_OF_LATCH_REPORT
Allows you to specify the maximum number of latches that the Synthesis Report should display.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SIZE_OF_LATCH_REPORT <value>
Default Value
100
Example
set_global_assignment -name SIZE_OF_LATCH_REPORT 200
1.2.109. SIZE_OF_PR_INITIAL_CONDITIONS_REPORT
Allows you to specify the maximum number of registers that the PR Initial Conditions Report should display.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SIZE_OF_PR_INITIAL_CONDITIONS_REPORT <value>
Default Value
100
Example
set_global_assignment -name SIZE_OF_PR_INITIAL_CONDITIONS_REPORT 200
1.2.110. SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES
Allows the Compiler to skip the fitting stage during smart recompilation when design changes may affect timing requirements. This option is available only for changes to Cyclone, Stratix, and Stratix GX PLL parameters, and Stratix GX gigabit transceiver block (GXB) parameters.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES <value>
Default Value
Off
1.2.111. STATE_MACHINE_PROCESSING
Specifies the processing style used to compile a state machine. You can use your own 'User-Encoded' style, or select 'One-Hot', 'Minimal Bits', 'Gray', 'Johnson', 'Sequential' or 'Auto' (Compiler-selected) encoding.
Type
Enumeration
Values
- Auto
- Gray
- Johnson
- Minimal Bits
- One-Hot
- Sequential
- User-Encoded
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name STATE_MACHINE_PROCESSING -entity <entity name> <value> set_instance_assignment -name STATE_MACHINE_PROCESSING -to <to> -entity <entity name> <value> set_global_assignment -name STATE_MACHINE_PROCESSING <value>
Default Value
Auto
Example
set_global_assignment -name state_machine_processing "one-hot" set_instance_assignment -name state_machine_processing "one-hot" -to foo
See Also
Extract Verilog State Machines Extract VHDL State Machines
1.2.112. STRICT_RAM_RECOGNITION
When this option is ON, the Compiler is only allowed to replace RAM if the hardware matches the design exactly.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name STRICT_RAM_RECOGNITION <value> set_global_assignment -name STRICT_RAM_RECOGNITION -entity <entity name> <value> set_instance_assignment -name STRICT_RAM_RECOGNITION -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name strict_ram_recognition on set_global_assignment -name strict_ram_recognition on -to foo
1.2.113. SYNCHRONIZATION_REGISTER_CHAIN_LENGTH
This setting specifies the maximum number of registers in a row to be considered as a synchronization chain. Synchronization chains are sequences of registers with the same clock, no fanout in between, such that the first register is fed by a pin, or by logic in another clock domain. These registers will be considered for metastability analysis (available for some families), and are also protected from optimizations such as retiming. When gate-level retiming is turned on, these registers will not be moved. The default length is device-specific.
Old Name
ADV_NETLIST_OPT_METASTABLE_REGS
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH <value> set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -entity <entity name> <value> set_instance_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH -to <to> -entity <entity name> <value>
1.2.114. SYNTHESIS_AVAILABLE_RESOURCE_MULTIPLIER
Specify a global resource multiplier for synthesis. Applies to RAM, DSP, and LUT resources.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTHESIS_AVAILABLE_RESOURCE_MULTIPLIER <value>
Default Value
1
Example
set_global_assignment -name synthesis_available_resource_multiplier 2
1.2.115. SYNTHESIS_EFFORT
Controls the synthesis trade-off between compilation speed and performance and area. The default is 'Auto'. You can select 'Fast' for faster compilation speed at the cost of performance and area.
Type
Enumeration
Values
- Auto
- Fast
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTHESIS_EFFORT <value>
Default Value
Auto
Example
set_global_assignment -name synthesis_effort fast
1.2.116. SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER
When this option is set to On, synthesis will keep the synchronous clear/preset behavior when remap I/O wysiwyg primitives (from other device families) using DDIO INPUT feature to the targeted device family.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER -entity <entity name> <value> set_instance_assignment -name SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER -to <to> -entity <entity name> <value> set_global_assignment -name SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER <value>
Example
set_global_assignment -name synthesis_keep_synch_clear_preset_behavior_in_unmapper on set_instance_assignment -name synthesis_keep_synch_clear_preset_behavior_in_unmapper on -to foo
1.2.117. SYNTHESIS_S10_MIGRATION_CHECKS
Option to enable/disable Arria 10 to Stratix 10 Synthesis Migration Checks.
Type
Boolean
Device Support
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS <value>
Default Value
Off
Example
set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS on
1.2.118. SYNTH_CLOCK_MUX_PROTECTION
Causes the multiplexers in the clock network to be decomposed to 2to1 multiplexer trees, and protected from being merged with, or transferred to, other logic. This option helps the Timing Analyzer to understand clock behavior.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION <value>
Default Value
On
Example
set_global_assignment -name synth_clock_mux_protection off
1.2.119. SYNTH_GATED_CLOCK_CONVERSION
Automatically converts gated clocks in the design to use clock enable pins if clock enable pins are not used in the original design. Clock gating logic can contain AND, OR, MUX, and NOT gates. Turning on this option may increase memory use and overall run time. You must use the Timing Analyzer for timing analysis, and you must define all base clocks in Synopsys Design Constraints (SDC) format.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION -entity <entity name> <value> set_instance_assignment -name SYNTH_GATED_CLOCK_CONVERSION -to <to> -entity <entity name> <value> set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION <value>
Default Value
Off
Example
set_global_assignment -name synth_gated_clock_conversion on set_instance_assignment -name synth_gated_clock_conversion on -to foo
1.2.120. SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK
Identifies the signal as a base clock during gated clock conversion. Only has an impact if SYNTH_GATED_CLOCK_CONVERSION is also enabled.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK -entity <entity name> <value> set_instance_assignment -name SYNTH_GATED_CLOCK_CONVERSION_BASE_CLOCK -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name synth_gated_clock_conversion_base_clock on -to foo
See Also
Auto Gated Clock Conversion
1.2.121. SYNTH_MESSAGE_LEVEL
Specifies the type of Analysis & Synthesis messages you want to view. Setting this option to 'Low' allows you to view only the most important Analysis & Synthesis messages. Setting this option to 'Medium' allows you to view most Analysis & Synthesis messages, but hides the detailed messages in Analysis & Synthesis report. Setting this option to 'High' allows you to view all Analysis & Synthesis messages.
Type
Enumeration
Values
- High
- Low
- Medium
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTH_MESSAGE_LEVEL <value>
Default Value
Medium
1.2.122. SYNTH_PROTECT_SDC_CONSTRAINT
Causes SDC constraint checking in register merging. It helps to maintain the validity of SDC constraints through compilation.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT <value>
Default Value
Off
Example
set_global_assignment -name synth_protect_sdc_constraint on
1.2.123. SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM
Specifies whether RAM, ROM, and shift-register inference should take the design and device resources into account.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM <value>
Example
set_global_assignment -name synth_resource_aware_inference_for_block_ram on
1.2.124. SYNTH_TIMING_DRIVEN_SYNTHESIS
Allows synthesis to use timing information during synthesis to better optimize the design.
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS <value> set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -entity <entity name> <value> set_instance_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -to <to> -entity <entity name> <value>
Example
set_global_assignment -name synth_timing_driven_synthesis on
1.2.125. TOP_LEVEL_ENTITY
Specifies the full hierarchichal path of the entity that is the focus of the current compilation or simulation.
Old Name
FOCUS_ENTITY_NAME
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name TOP_LEVEL_ENTITY <value>
1.2.126. UNCONNECTED_OUTPUT_PORT_MESSAGE_LEVEL
Tells the compiler whether to show a warning, and error or no message at all when an output port in a module does not have a driver.
Type
Enumeration
Values
- Error
- Off
- Warning
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name UNCONNECTED_OUTPUT_PORT_MESSAGE_LEVEL <value> set_global_assignment -name UNCONNECTED_OUTPUT_PORT_MESSAGE_LEVEL -entity <entity name> <value> set_instance_assignment -name UNCONNECTED_OUTPUT_PORT_MESSAGE_LEVEL -to <to> -entity <entity name> <value>
Default Value
Warning
Example
set_global_assignment -name unconnected_output_port_message_level warning set_instance_assignment -name unconnected_output_port_message_level error -to accel
1.2.127. USER_LIBRARIES
Specifies the pathnames of user-defined libraries.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name USER_LIBRARIES <value>
1.2.128. USE_GENERATED_PHYSICAL_CONSTRAINTS
Specifies the physical constraints file generated by the resynthesis tool to be used by the Quartus Prime software
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS -section_id <section identifier> <value> set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier
1.2.129. VERILOG_CONSTANT_LOOP_LIMIT
Defines the iteration limit for Verilog loops with loop conditions that evaluate to compile-time constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust memory or trap the software in an actual infinite loop.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT <value> set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -entity <entity name> <value> set_instance_assignment -name VERILOG_CONSTANT_LOOP_LIMIT -to <to> -entity <entity name> <value>
Default Value
5000
Example
set_global_assignment -name verilog_constant_loop_limit 3000
1.2.130. VERILOG_INPUT_VERSION
Specifies the language dialect to use when processing Verilog Design Files: Verilog-1995 (IEEE Std. 1364-1995), Verilog-2001 (IEEE Std. 1364-2001), SystemVerilog-2005 (IEEE Std. 1800-2005), or SystemVerilog-2009 (IEEE Std. 1800-2009). Verilog 2001 is the default dialect.
Type
Enumeration
Values
- SystemVerilog_2005
- SystemVerilog_2009
- SystemVerilog_2012
- Verilog_1995
- Verilog_2001
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VERILOG_INPUT_VERSION <value>
Default Value
Verilog_2001
1.2.131. VERILOG_LMF_FILE
Specifies the default Library Mapping File (.lmf) for the current compilation.
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VERILOG_LMF_FILE <value>
1.2.132. VERILOG_MACRO
Defines Verilog HDL macro - same as `define directive
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name VERILOG_MACRO <value>
1.2.133. VERILOG_NON_CONSTANT_LOOP_LIMIT
Defines the iteration limit for Verilog loops with loop conditions that do not evaluate to compile-time constants on each loop iteration. This limit exists primarily to identify potential infinite loops before they exhaust memory or trap the software in an actual infinite loop.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT <value> set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -entity <entity name> <value> set_instance_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT -to <to> -entity <entity name> <value>
Default Value
250
Example
set_global_assignment -name verilog_non_constant_loop_limit 3000
1.2.134. VERILOG_SHOW_LMF_MAPPING_MESSAGES
Determines whether to display messages describing the mappings used in the Library Mapping File.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES <value>
1.2.135. VHDL_INPUT_LIBRARY
Specifies the logical name of a user-defined VHDL design library : physical name.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name VHDL_INPUT_LIBRARY -to <to> <value>
1.2.136. VHDL_INPUT_VERSION
Specifies the language dialect to use when processing VHDL Design Files: VHDL-1987 (IEEE Std 1076-1987), VHDL-1993 (IEEE Std 1076-1993) or VHDL-2008 (IEEE Std 1076-2008). VHDL-1993 is the default dialect.
Type
Enumeration
Values
- VHDL_1987
- VHDL_1993
- VHDL_2008
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VHDL_INPUT_VERSION <value>
Default Value
VHDL_1993
1.2.137. VHDL_LMF_FILE
Specifies the default Library Mapping File (.lmf) for the current compilation.
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VHDL_LMF_FILE <value>
1.2.138. VHDL_SHOW_LMF_MAPPING_MESSAGES
Determines whether to display messages describing the mappings used in the Library Mapping File.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES <value>
1.3. Assembler Assignments
1.3.1. ANTI_TAMPER_RESPONSE
Device Cleaning clears configuration information from the FPGA, HPS caches, and on-chip RAM. Device Cleaning and Zeroization also clears the AES key stored in BBRAM and zeros out memory. Device Cleaning, Zeroization, BBRAM key cleaning disables all security features and Clears BBRAM registers and the BBRAM key. Disabled does not respond to tampering events. Kill eFuse permanently disables the FPGA. Refer to the Stratix 10 Device Security User Guide more detailed information about these choices.
Type
Enumeration
Values
- DISABLED
- Device Cleaning
- Device Cleaning Zeroization BBRAM key cleaning
- Device Cleaning and Zeroization
- Kill eFuse
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ANTI_TAMPER_RESPONSE <value>
Default Value
DISABLED
1.3.2. AUTO_RESTART_CONFIGURATION
Directs the device to restart the configuration process automatically if a data error is encountered. If this option is turned off, you must externally direct the device to restart the configuration process if an error occurs.
Old Name
Auto restart on configuration error
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_RESTART_CONFIGURATION <value>
Default Value
On
1.3.3. CLOCK_SOURCE
Specifies whether the configuration device generates an internal clock or applies an external clock.
Type
Enumeration
Values
- External
- Internal
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name CLOCK_SOURCE <value>
Default Value
Internal
1.3.4. COMPRESSION_MODE
Allows you to compress SRAM Object Files (.sof) stored in a Programmer Object File (.pof) for a configuration device.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name COMPRESSION_MODE <value>
Default Value
Off
1.3.5. CONFIGURATION_CLOCK_DIVISOR
Specifies the clock frequency divisor, which is used to determine the period of the system clock.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR <value>
Default Value
1
1.3.6. CONFIGURATION_CLOCK_FREQUENCY
Specifies the clock frequency of the configuration device.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY <value>
Default Value
10 MHz
1.3.7. ENABLE_ADV_SEU_DETECTION
Allows you to enable the Advanced SEU Detection compiler to generate design SEU sensitivity map file. If this option is turned on, the SMH file will be generated.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name ENABLE_ADV_SEU_DETECTION <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_ADV_SEU_DETECTION ON
See Also
PARTITION_ASD_REGION_ID
1.3.8. ENABLE_AUTONOMOUS_PCIE_HIP
Directs the device to release the PCIe HIP after the periphery is configured and before core configuration is completed. This option doesn't take effect in CvP Init mode since the periphery automatically comes up first, all other modes bring the PCIe HIP up first when this option is selected.
Old Name
Auto restart on configuration error
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP <value>
Default Value
Off
1.3.9. ENABLE_FREQUENCY_TAMPER_DETECTION
Enable frequency tamper detection
Type
Boolean
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_FREQUENCY_TAMPER_DETECTION <value>
Default Value
Off
1.3.10. ENABLE_OCT_DONE
This option controls whether the INIT_DONE signal will be gated by OCT_DONE signal which indicates the Power-Up OCT calibration is completed. If this option is turned off, the INIT_DONE signal is not gated by the OCT_DONE signal.
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_OCT_DONE <value>
Default Value
Off
1.3.11. ENABLE_PR_POF_ID
Enable PR POF ID for bitstream compatibility check.
Type
Boolean
Device Support
- Intel® Stratix® 10
Notes
Syntax
set_global_assignment -name ENABLE_PR_POF_ID <value> set_instance_assignment -name ENABLE_PR_POF_ID -to <to> <value>
Default Value
On
1.3.12. ENABLE_TEMPERATURE_TAMPER_DETECTION
Enable temperature tamper detection
Type
Boolean
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_TEMPERATURE_TAMPER_DETECTION <value>
Default Value
Off
1.3.13. ENABLE_VCCL_SDM_VOLTAGE_TAMPER_DETECTION
When enabled, triggers an anti-tamper response when the VCCL_SDM voltage differs by more than the Voltage tamper detection trigger percentage you specify.
Type
Boolean
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_VCCL_SDM_VOLTAGE_TAMPER_DETECTION <value>
Default Value
Off
1.3.14. ENABLE_VCCL_VOLTAGE_TAMPER_DETECTION
When enabled, triggers an anti-tamper response when the VCCL voltage differs by more than the Voltage tamper detection trigger percentage you specify.
Type
Boolean
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_VCCL_VOLTAGE_TAMPER_DETECTION <value>
Default Value
Off
1.3.15. ENABLE_VOLTAGE_TAMPER_DETECTION
Enable voltage tamper detection
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_VOLTAGE_TAMPER_DETECTION <value>
Default Value
Off
1.3.16. ENCRYPT_PROGRAMMING_BITSTREAM
Enable configuration bitstream encryption.
Type
Boolean
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENCRYPT_PROGRAMMING_BITSTREAM <value> set_instance_assignment -name ENCRYPT_PROGRAMMING_BITSTREAM -to <to> <value>
Default Value
Off
1.3.17. EPROM_USE_CHECKSUM_AS_USERCODE
Uses the checksum value from the Programmer Object File (.pof) as the JTAG user code.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE <value>
Default Value
Off
1.3.18. FREQUENCY_TAMPER_DETECTION_RANGE
Specifies the maximum percentage frequency difference allowed between the OSC_CLK_1 input clock and the internal oscillator. Percentage differences larger than the value you specify trigger an anti-tamper response when you have enabled a response.
Type
Integer
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name FREQUENCY_TAMPER_DETECTION_RANGE <value>
Default Value
0
1.3.19. GENERATE_COMPRESSED_SOF
Allows you to enable the SOF compression and generate compressed SOF file
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name GENERATE_COMPRESSED_SOF <value>
Default Value
Off
Example
set_global_assignment -name GENERATE_COMPRESSED_SOF ON
1.3.20. GENERATE_HEX_FILE
Generates a Hexadecimal (Intel-format) Output File (.hexout) containing configuration data that can be programmed into a parallel data source, such as an EPROM or a mass storage device, which then in turn configures the target device.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GENERATE_HEX_FILE <value>
Default Value
Off
1.3.21. GENERATE_PMSF_FILES
Generates a Partial-Masked SOF file (.pmsf) containing both configuration data and region definitions that can be used to re-configure a device region. If this option is turned on, the Partial-Masked SOF files (.pmsf) will be generated instead of Mask Settings files (.msf).
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Syntax
set_global_assignment -name GENERATE_PMSF_FILES <value>
Default Value
On
Example
set_global_assignment -name GENERATE_PMSF_FILES ON
See Also
GENERATE_PMSF_FILES
1.3.22. GENERATE_PR_RBF_FILE
Generates a Partial Reconfiguration Raw Binary File (.rbf) containing configuration data that an intelligent external controller can use to reconfigure the portion of target device.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name GENERATE_PR_RBF_FILE <value>
1.3.23. GENERATE_RBF_FILE
Generates a Raw Binary File (.rbf) containing configuration data that an intelligent external controller can use to configure the target device.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GENERATE_RBF_FILE <value>
Default Value
Off
1.3.24. GENERATE_TTF_FILE
Generates a Tabular Text File (.ttf) containing configuration data that an intelligent external controller can use to configure the target device.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GENERATE_TTF_FILE <value>
Default Value
Off
1.3.25. HEXOUT_FILE_COUNT_DIRECTION
Specifies the count direction for the data in a Hexadecimal (Intel-Format) Output File (.hexout) as up or down.
Old Name
HEX_FILE_COUNT_UP_DOWN
Type
Enumeration
Values
- Down
- Up
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION <value>
Default Value
Up
1.3.26. HEXOUT_FILE_START_ADDRESS
Specifies the starting memory address for a Hexadecimal (Intel-Format) Output File (.hexout).
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name HEXOUT_FILE_START_ADDRESS <value>
Default Value
0
1.3.27. HPS_DAP_NO_CERTIFICATE
Allow HPS debug without certificate.
Type
Boolean
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name HPS_DAP_NO_CERTIFICATE <value> set_instance_assignment -name HPS_DAP_NO_CERTIFICATE -to <to> <value>
Default Value
Off
1.3.28. HPS_DAP_SPLIT_MODE
Enables the HPS debug access port (DAP) pins. When HPS JTAG pins are selected, these HPS JTAG pins are shared with other HPS uses and with user logic.
Type
Enumeration
Values
- Disabled
- HPS Pins
- SDM Pins
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name HPS_DAP_SPLIT_MODE <value>
Default Value
Disabled
1.3.29. HPS_INITIALIZATION
Selects the order in which the Hard Processor System (HPS) and the FPGA are configured.
Type
Enumeration
Values
- After INIT_DONE
- HPS First
- When requested by FPGA
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name HPS_INITIALIZATION <value>
1.3.30. HPS_RETAIN_DDR_CONTENT
Determine the condition for the DDR content be retained.
Type
Boolean
Device Support
- Diamond Mesa
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name HPS_RETAIN_DDR_CONTENT <value>
Default Value
Off
1.3.31. ON_CHIP_BITSTREAM_DECOMPRESSION
Allows the device to accept and decompress bitstreams during configuration. Produces compressed bitstreams and enables bitstream decompression.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION <value>
Default Value
On
1.3.32. PERMITTED_OWNER_CANCELLATION_ID
Specifies owner cancellation IDs for the cancellation IDs you are using in your design. Specify a list of integers in the range 0 to 31. For example, the string, \"0,1,4,31\" enables fuse programming for owner cancellation IDs 0,1,4 and 31.
Type
String
Device Support
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PERMITTED_OWNER_CANCELLATION_ID <value>
1.3.33. PROGRAMMING_BITSTREAM_ENCRYPTION_CNOC_SCRAMBLING
Limits potential side-channel exposure when you store the AES key in eFuses.
Type
Boolean
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_CNOC_SCRAMBLING <value> set_instance_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_CNOC_SCRAMBLING -to <to> <value>
Default Value
Off
1.3.34. PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT
Configuration bitstream encryption key storage location.
Type
Enumeration
Values
- Battery Backup RAM
- Quad SPI Intrinsic ID PUF-wrapped
- eFuses
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT <value> set_instance_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_KEY_SELECT -to <to> <value>
1.3.35. PROGRAMMING_BITSTREAM_ENCRYPTION_UPDATE_RATIO
Configuration bitstream encryption update ratio. Inserts new keys to limit the amount of data encrypted by a given key to the specified ratio.
Type
Integer
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_UPDATE_RATIO <value> set_instance_assignment -name PROGRAMMING_BITSTREAM_ENCRYPTION_UPDATE_RATIO -to <to> <value>
Default Value
0
1.3.36. PR_BASE_MSF
Specify block name and path of base revision MSF file for mask comparison in a PR project.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name PR_BASE_MSF <value>
1.3.37. PR_BASE_SOF
Specify path of base revision SOF file for bit settings comparison in a PR project.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name PR_BASE_SOF <value>
1.3.38. PR_SKIP_BASE_CHECK
Disable mask comparison and logic verification for a reconfigurable partition in a PR project.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name PR_SKIP_BASE_CHECK <value>
1.3.39. PWRMGT_ADV_CLOCK_DATA_FALL_TIME
Specify fall time of clock and data signals in nanoseconds. Integer value between 0 and 65535. The relevant SMBus requirement is tf as detailed in the SMBus AC Specifications. This is for PMBus Master mode.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_ADV_CLOCK_DATA_FALL_TIME <value>
Default Value
0
1.3.40. PWRMGT_ADV_CLOCK_DATA_RISE_TIME
Specify rise time of clock and data signals in nanoseconds. Integer value between 0 and 65535. The relevant SMBus requirement is tf as detailed in the SMBus AC Specifications. This is for PMBus Master mode.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_ADV_CLOCK_DATA_RISE_TIME <value>
Default Value
0
1.3.41. PWRMGT_ADV_DATA_HOLD_TIME
Specify data hold time in nanoseconds. Integer value between 0 and 65535. This parameter is used to control the hold time of SDA during transmit in both PMBus Master and PMBus Slave mode. The relevant SMBus requirement is tHD:DAT as detailed in the SMBus AC Specifications.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_ADV_DATA_HOLD_TIME <value>
Default Value
0
1.3.42. PWRMGT_ADV_DATA_SETUP_TIME
Specify data setup time in nanoseconds. Integer value between 0 and 65535. The amount of time delay introduced in the rising edge of SCL relative to SDA changing when a read-request is serviced. The relevant SMBus requirement is tSU:DAT as detailed in the SMBus AC Specifications. This is for PMBus slave mode.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_ADV_DATA_SETUP_TIME <value>
Default Value
0
1.3.43. PWRMGT_ADV_FPGA_RELEASE_DELAY
When operation mode is PMBus Slave mode, specify value in unassigned decimal value between 0 and 255 for delay duration in milliseconds before starting FPGA after first successful VOUT_COMMAND is responded.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_ADV_FPGA_RELEASE_DELAY <value>
Default Value
10
1.3.44. PWRMGT_ADV_INITIAL_DELAY
When operation mode is PMBus Master mode, specify value in unassigned decimal value between 0 and 255 for delay duration in milliseconds before first command is used.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_ADV_INITIAL_DELAY <value>
Default Value
0
1.3.45. PWRMGT_ADV_VOLTAGE_STABLE_DELAY
When operation mode is PMBus Master mode, specify value in unassigned decimal value between 0 and 255 for delay duration in milliseconds for voltage to stablize after each voltage update.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_ADV_VOLTAGE_STABLE_DELAY <value>
Default Value
10
1.3.46. PWRMGT_ADV_VOUT_READING_ERR_MARGIN
Specify power level feedback reading error margin index at 0.25% granularity, used by the controller to determine if target VID is achieved. 0: +/-1.00%, 1: +/-1.25%, ... 8: +/-3.00%
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_ADV_VOUT_READING_ERR_MARGIN <value>
Default Value
8
1.3.47. PWRMGT_BUS_SPEED_MODE
Specifies bus speed mode in PMBus Master mode
Type
Enumeration
Values
- 100 KHz
- 400 KHz
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_BUS_SPEED_MODE <value>
Default Value
100 KHz
1.3.48. PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE
Specifies 7 bit Hexadecimal value without leading prefix 0x for address, for instance 7F, for device address assignment when in PMBus Slave mode. It must be non-zero address.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_DEVICE_ADDRESS_IN_PMBUS_SLAVE_MODE <value>
Default Value
00
1.3.49. PWRMGT_DIRECT_FORMAT_COEFFICIENT_B
Specifies direct format coefficient b when in PMBus Master mode. Signed integer between -32768 and 32767. Coefficient b is the offset. This value is supplied by the PMBus devices manufacturer in the product literature. User must set this parameter when output voltage format of PMBus device is Direct formator or auto discovery format.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B <value>
Default Value
0
1.3.50. PWRMGT_DIRECT_FORMAT_COEFFICIENT_M
Specifies direct format coefficient m when in PMBus Master mode. Signed integer between -32768 and 32767. Coefficient m is the slope coefficient. This value is supplied by the PMBus devices manufacturer in the product literature. User must set this parameter when output voltage format of PMBus device is Direct format or auto discovery format. It must be a non-zero value when output voltage format of PMBus device is Direct format.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M <value>
Default Value
0
1.3.51. PWRMGT_DIRECT_FORMAT_COEFFICIENT_R
Specify direct format coefficient R when in PMBus Master mode. Signed integer between -128 and 127. Coefficient R is the exponent. This value is supplied by the PMBus devices manufacturer in the product literature. User must set this parameter when output voltage format of PMBus device is Direct format or auto discovery format.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R <value>
Default Value
0
1.3.52. PWRMGT_LINEAR_FORMAT_N
Specify linear format N when in PMBus Master mode. Signed integer between -16 and 15. This is exponent for for the mantissa for output voltage related command when VOUT format is set to Linear format. This value is supplied by the PMBus devices manufacturer in the product literature. A nonzero value must be specified when linear voltage output format is chosen.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N <value>
Default Value
0
1.3.53. PWRMGT_PAGE_COMMAND_ENABLE
By enabling PAGE command, the FPGA PMBus master will use PAGE command to set all output channels on registered regulator modules to respond to VOUT_COMMAND.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_PAGE_COMMAND_ENABLE <value>
Default Value
Off
1.3.54. PWRMGT_PAGE_COMMAND_PAYLOAD
By enabling PAGE command, the FPGA PMBus master will use PAGE command to set all output channels on registered regulator modules to respond to VOUT_COMMAND. If only specified output channels on registered regulator modules need to respond to VOUT_COMMAND, please enter the corresponding page value.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_PAGE_COMMAND_PAYLOAD <value>
Default Value
255
1.3.55. PWRMGT_SLAVE_DEVICE0_ADDRESS
Specifies 7 bit Hexadecimal value without leading prefix 0x, for instance 7F, for slave address of the voltage regulator when in PMBus Master mode. It must be non-zero address.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS <value>
Default Value
00
1.3.56. PWRMGT_SLAVE_DEVICE1_ADDRESS
Specifies 7 bit Hexadecimal value without leading prefix 0x, for instance 7F, for slave address of the voltage regulator when in PMBus Master mode.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS <value>
Default Value
00
1.3.57. PWRMGT_SLAVE_DEVICE2_ADDRESS
Specifies 7 bit Hexadecimal value without leading prefix 0x, for instance 7F, for slave address of the voltage regulator when in PMBus Master mode.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS <value>
Default Value
00
1.3.58. PWRMGT_SLAVE_DEVICE3_ADDRESS
Specifies 7 bit Hexadecimal value without leading prefix 0x, for instance 7F, for slave address of the voltage regulator when in PMBus Master mode.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS <value>
Default Value
00
1.3.59. PWRMGT_SLAVE_DEVICE4_ADDRESS
Specifies 7 bit Hexadecimal value without leading prefix 0x, for instance 7F, for slave address of the voltage regulator when in PMBus Master mode.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS <value>
Default Value
00
1.3.60. PWRMGT_SLAVE_DEVICE5_ADDRESS
Specifies 7 bit Hexadecimal value without leading prefix 0x, for instance 7F, for slave address of the voltage regulator when in PMBus Master mode.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS <value>
Default Value
00
1.3.61. PWRMGT_SLAVE_DEVICE6_ADDRESS
Specifies 7 bit Hexadecimal value without leading prefix 0x, for instance 7F, for slave address of the voltage regulator when in PMBus Master mode.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS <value>
Default Value
00
1.3.62. PWRMGT_SLAVE_DEVICE7_ADDRESS
Specifies 7 bit Hexadecimal value without leading prefix 0x, for instance 7F, for slave address of the voltage regulator when in PMBus Master mode.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS <value>
Default Value
00
1.3.63. PWRMGT_SLAVE_DEVICE_TYPE
Specifies the slave device type when the target FPGA device is in PMBus master mode
Type
Enumeration
Values
- ED8401
- EM21XX
- EM22XX
- ISL82XX
- LTM4677
- Other
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE <value>
Default Value
LTM4677
1.3.64. PWRMGT_TABLE_VERSION
Power table version. 0 is a reserved value to indicate the power table is invalid. 1 is used for Nadder and FM until Quartus version 20.x. 2 indicates the version after addition of PAGE command payload field.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_TABLE_VERSION <value>
Default Value
2
1.3.65. PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT
Specifies the output voltage format when in PMBus Master mode.
Type
Enumeration
Values
- Millivolts
- Volts
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT <value>
Default Value
Volts
1.3.66. PWRMGT_VOLTAGE_OUTPUT_FORMAT
Specifies the output voltage format when in PMBus Master mode.
Type
Enumeration
Values
- Auto discovery
- Direct format
- Linear format
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT <value>
Default Value
Auto discovery
1.3.67. QKY_FILE
Specify a Quartus key file.
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name QKY_FILE <value> set_instance_assignment -name QKY_FILE -to <to> <value>
1.3.68. RBF_FILE_GENERATION_FOR_SUPR
PR RBF generation fo specified SUPR partition.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name RBF_FILE_GENERATION_FOR_SUPR <value> set_instance_assignment -name RBF_FILE_GENERATION_FOR_SUPR -to <to> <value>
Default Value
On
1.3.69. RELEASE_CLEARS_BEFORE_TRI_STATES
Directs the device to release the clear signal on registered logic cells and I/O cells before releasing the output enable override on tri-state buffers. If this option is turned off, the output enable signals are released before the clear overrides are released.
Old Name
Release clears before tri-states
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES <value>
Default Value
Off
1.3.70. RSU_MAX_RETRY_COUNT
Specify the maximum number of times that the current image will be retried in Remote System Update before giving up and starting failover flow. The valid values are 1, 2 and 3.
Type
Integer
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name RSU_MAX_RETRY_COUNT <value> set_instance_assignment -name RSU_MAX_RETRY_COUNT -to <to> <value>
Default Value
1
1.3.71. RUN_CONFIG_CPU_FROM_INT_OSC
When set, the configuration CPU is run from the internal oscillator.
Type
Boolean
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name RUN_CONFIG_CPU_FROM_INT_OSC <value>
Default Value
Off
1.3.72. SECU_OPTION_DISABLE_ENCRYPTION_KEY_IN_BBRAM
When set, the device does not use an AES key stored in BBRAM. Disabling the storage locations that you are not using may prevent an attack that uses a different storage location for the encryption key.
Type
Enumeration
Values
- OFF
- ON
- On check
- On sticky
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECU_OPTION_DISABLE_ENCRYPTION_KEY_IN_BBRAM <value>
Default Value
OFF
1.3.73. SECU_OPTION_DISABLE_ENCRYPTION_KEY_IN_EFUSES
When set, the device does not use an AES key stored in eFuses. Disabling the storage locations that you are not using may prevent an attack that uses a different storage location for the encryption key.
Type
Enumeration
Values
- OFF
- ON
- On check
- On sticky
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECU_OPTION_DISABLE_ENCRYPTION_KEY_IN_EFUSES <value>
Default Value
OFF
1.3.74. SECU_OPTION_DISABLE_HPS_DEBUG
When set, permanently disables debugging using JTAG to access the HPS.
Type
Enumeration
Values
- OFF
- ON
- On check
- On sticky
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECU_OPTION_DISABLE_HPS_DEBUG <value>
Default Value
OFF
1.3.75. SECU_OPTION_DISABLE_JTAG
When set, disables JTAG command and configuration. Setting this eFuse eliminates JTAG as mode of attack, but also eliminates boundary scan.
Type
Enumeration
Values
- OFF
- ON
- On check
- On sticky
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECU_OPTION_DISABLE_JTAG <value>
Default Value
OFF
1.3.76. SECU_OPTION_DISABLE_PUF_WRAPPED_ENCRYPTION_KEY
When set, the device does not use a a PUF-wrapped AES key stored in Quad SPI. Disabling the storage locations that you are not using may prevent an attack that uses a different storage location for the encryption key.
Type
Enumeration
Values
- OFF
- ON
- On check
- On sticky
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECU_OPTION_DISABLE_PUF_WRAPPED_ENCRYPTION_KEY <value>
Default Value
OFF
1.3.77. SECU_OPTION_DISABLE_VIRTUAL_EFUSES
Security option to disable virtual eFuses.
Type
Enumeration
Values
- OFF
- ON
- On check
- On sticky
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECU_OPTION_DISABLE_VIRTUAL_EFUSES <value>
Default Value
OFF
1.3.78. SECU_OPTION_FORCE_ENCRYPTION_KEY_UPDATE
When set, all encrypted bitstreams must specify the Encryption Update Ratio.
Type
Enumeration
Values
- OFF
- ON
- On check
- On sticky
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECU_OPTION_FORCE_ENCRYPTION_KEY_UPDATE <value>
Default Value
OFF
1.3.79. SECU_OPTION_FORCE_SDM_CLOCK_TO_INT_OSC
When set, disables an external clock source for the SDM for bitstream configuration. Forcing the SDM to use an internal oscillator helps to limit potential interruptions or attacks by modifying an external clock during configuration.
Type
Enumeration
Values
- OFF
- ON
- On check
- On sticky
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECU_OPTION_FORCE_SDM_CLOCK_TO_INT_OSC <value>
Default Value
OFF
1.3.80. SECU_OPTION_LOCK_SECURITY_EFUSES
Programming this fuse prevents the future programming of any owner-accessible security policy fuses, not including key cancellation ID fuses.
Type
Enumeration
Values
- OFF
- ON
- On check
- On sticky
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name SECU_OPTION_LOCK_SECURITY_EFUSES <value>
Default Value
OFF
1.3.81. STRATIXII_CONFIGURATION_DEVICE
Specifies the configuration device that you want to use as the means of configuring the target device.
Old Name
STRATIX_II_CONFIGURATION_DEVICE
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE <value>
Default Value
Auto
1.3.82. STRATIX_JTAG_USER_CODE
Specifies user-defined information about the target device. The JTAG user code is an extension of the option register. This data can be read with the JTAG USERCODE instruction.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Diamond Mesa
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name STRATIX_JTAG_USER_CODE <value>
Default Value
FFFFFFFF
1.3.83. TEMPERATURE_TAMPER_LOWER_BOUND
Specifies a signed fixed-point decimal value for the lower bound of the device temperature. Temperatures that exceed the lower bound you specify trigger an anti-tamper response when you have enabled a response.
Type
Integer
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name TEMPERATURE_TAMPER_LOWER_BOUND <value>
Default Value
-40
1.3.84. TEMPERATURE_TAMPER_UPPER_BOUND
Specifies a signed fixed-point decimal value for the upper bound of the device temperature. Temperatures that exceed the upper bound you specify trigger an anti-tamper response when you have enabled a response.
Type
Integer
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name TEMPERATURE_TAMPER_UPPER_BOUND <value>
Default Value
110
1.3.85. UNINITIALIZED_RAM_CONTENT_PATTERN
Set specified pattern for uninitialized RAM content pattern on specified instance
Type
Enumeration
Values
- 0000
- 0101
- 1010
- 1111
- OFF
- ON
- RANDOM
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_instance_assignment -name UNINITIALIZED_RAM_CONTENT_PATTERN -to <to> <value>
Example
set_instance_assignment -name UNINITIALIZED_RAM_CONTENT_PATTERN on -to ram_inst
1.3.86. USE_CHECKSUM_AS_USERCODE
Sets the JTAG user code to match the checksum value of the device programming file. The programming file is a Programmer Object File (.pof) for non-volatile devices, such as MAX II devices, or an SRAM Object File (.sof) for SRAM-based devices. If you turn this option on, the JTAG user code option is not available.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name USE_CHECKSUM_AS_USERCODE <value>
Default Value
On
1.3.87. USE_CONFIGURATION_DEVICE
Specifies that you intend to use a configuration device(s) such as the EPC2 as the means of configuring the target device. This option directs the Compiler to create a Programmer Output File (.pof) for programming the configuration device. If multiple configuration devices are needed, one POF is created for each device, with names of the following format: name.pof, name_1.pof, name_2.pof, etc.
Type
Boolean
Device Support
- EPC1
- EPC2
- Enhanced Configuration Devices
- Flash Memory
- Virtual JTAG TAP
Notes
None
Syntax
set_global_assignment -name USE_CONFIGURATION_DEVICE <value>
1.3.88. VCCL_SDM_VOLTAGE_DIFFERENCE_TRIGGER
Specify voltage difference trigger value on VCCL_SDM for tamper detection. It must be a valid 16-bit non-negative integer
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name VCCL_SDM_VOLTAGE_DIFFERENCE_TRIGGER <value>
Default Value
0
1.3.89. VCCL_VOLTAGE_DIFFERENCE_TRIGGER
Specify voltage difference trigger value on VCCL for tamper detection. It must be a valid 16-bit non-negative integer
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name VCCL_VOLTAGE_DIFFERENCE_TRIGGER <value>
Default Value
0
1.3.90. VOLTAGE_TAMPER_DETECTION_TRIGGER
Specifies a voltage difference trigger value in percentage on all tamper detection power rails you enable. The percentage must be a valid 8-bit non-negative integer.
Type
Integer
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name VOLTAGE_TAMPER_DETECTION_TRIGGER <value>
Default Value
5
1.4. Classic Timing Assignments
1.4.1. ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS
Directs the Timing Analyzer to analyze latches as synchronous elements, rather than as combinational elements. Although latches continue to be implemented as a LUT feeding back onto itself, turning on this option directs the Timing Analyzer to analyze all latches as synchronous elements. Specifically, the clock enable is analyzed as an inverted clock. The Timing Analyzer reports the results of setup and hold analysis on these latches
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS <value>
Default Value
On
1.4.2. CUT_OFF_IO_PIN_FEEDBACK
Cuts off feedback from I/O pins during timing analysis. Cutting off I/O pin feedback is especially useful when a bidirectional pin is connected directly or indirectly to both the input and the output of a latch. This type of feedback path is continuous because it is not interrupted by any clocked logic primitives.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK <value>
Default Value
On
1.4.3. CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS
Cuts the paths between registers clocked by unrelated clocks. This option makes the timing analysis reporting similar to MAX+PLUS II timing analysis reporting.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS <value>
Default Value
On
1.4.4. CUT_OFF_READ_DURING_WRITE_PATHS
Cuts the path from the write enable register through the ESB to a destination register.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS <value>
Default Value
On
1.4.5. DEFAULT_HOLD_MULTICYCLE
Determines the default hold multicycle. The 'Same as Multicycle' setting ensures that the signal is latched on the final edge only. The 'One' setting assumes that the design can latch on any edge, up to and including the final edge. The 'Same as Multicycle' setting will give fewer hold time violation warnings. The 'One' setting is more restrictive, but it is the default setting for the Timing Analyzer and other third-party timing analyzers. This setting can be overridden on specific nodes with the Hold Multicycle option.
Type
Enumeration
Values
- One
- Same as Multicycle
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE <value>
Default Value
Same as Multicycle
Example
set_global_assignment -name default_hold_multicycle "Same as Multicycle" set_global_assignment -name default_hold_multicycle "One"
See Also
MULTICYCLE, SRC_MULTICYCLE, HOLD_MULTICYCLE, SRC_HOLD_MULTICYCLE, SETUP_RELATIONSHIP, HOLD_RELATIONSHIP
1.4.6. EMIF_SOC_PHYCLK_ADVANCE_MODELING
Instructs routing annotation to adjust the AV-SoC Phyclk delays.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING <value>
Default Value
Off
1.4.7. ENABLE_HPS_INTERNAL_TIMING
Enable HPS Internal Timing Characteristics
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING <value>
Default Value
Off
1.4.8. FLOW_ENABLE_TIMING_ANALYZER_AFTER_PLAN_STAGE
Allows you to turn on or turn off running the Timing Analyzer after Plan stage during compilation
Old Name
FLOW_ENABLE_TIMEQUEST_AFTER_PLAN_STAGE
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name FLOW_ENABLE_TIMING_ANALYZER_AFTER_PLAN_STAGE <value>
Default Value
Off
1.4.9. IMPLEMENTS_FREE_RUNNING_CLOCK
Specifies if timing analysis should consider if a node implements a free-running clock versus assuming the node implement a clock that could be arbitrarily gated. The setting has implications on how end-of-life effects are applied.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports wildcards.
This assignment is copied to any duplicated nodes.
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
The value of this assignment must be a node name.
Syntax
set_instance_assignment -name IMPLEMENTS_FREE_RUNNING_CLOCK -to <to> -entity <entity name> <value>
1.4.10. INPUT_TRANSITION_TIME
Specifies the input transition time. This assignment is used in Quartus to adjust the timing of the I/O buffers for all families that support AIOT. It is also used when generating the PrimeTime script that it is used by the HardCopy back end. This assignment gets converted as a set_input_transition SDC command. If the assignment does not exist, Quartus will generate a set_input_transition using 80% of VCCN * 1V/ns where VCCN depends on the I/O Standard used
Type
Time
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
This assignment is copied to any duplicated nodes.
Syntax
set_instance_assignment -name INPUT_TRANSITION_TIME -to <to> -entity <entity name> <value>
1.4.11. MAX_CORE_JUNCTION_TEMP
This is the maximum core junction temperature that will be encountered during operation. Specified in degrees Celsius
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name MAX_CORE_JUNCTION_TEMP <value>
1.4.12. MIN_CORE_JUNCTION_TEMP
This is the minimum core junction temperature that will be encountered during operation. Specified in degrees Celsius
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name MIN_CORE_JUNCTION_TEMP <value>
1.4.13. MIN_MTBF_REQUIREMENT
Specifies the minimum acceptable Mean Time Between Failures (MTBF), either globally for the design or for a specific synchronizer chain (if applied to the head register of a synchronizer chain). The MTBF value used will be 10 to the power of this setting value, in years. If the MTBF of a synchronizer chain is less than this value, it will be marked as a dangerous, asynchronous transfer that is in need of additional synchronization registers to help avoid metastability.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
INTEGER_RANGE
-8, 9
Notes
This assignment supports wildcards.
Syntax
set_global_assignment -name MIN_MTBF_REQUIREMENT <value> set_instance_assignment -name MIN_MTBF_REQUIREMENT -to <to> -entity <entity name> <value>
Default Value
9
1.4.14. NOMINAL_CORE_SUPPLY_VOLTAGE
Specifies the voltage for the core power supply. For Stratix III devices, the core supply voltage applies only to the VCCL power rail. Refer to the device datasheet for the current device family for more details.
Type
String
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE <value>
1.4.15. PACKAGE_SKEW_COMPENSATION
Indicates that that the package skew for the signal has been compensated by the board trace delays.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION -to <to> -entity <entity name> <value>
1.4.16. PLL_EXTERNAL_FEEDBACK_BOARD_DELAY
Specifies an external board delay between a feedback output pin and a feedback input pin (fbin) for a PLL in external feedback mode. This option is ignored if it is assigned to anything other than the fbin pin of a PLL.
Type
Time
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
None
Syntax
set_instance_assignment -name PLL_EXTERNAL_FEEDBACK_BOARD_DELAY -to <to> -entity <entity name> <value> set_global_assignment -name PLL_EXTERNAL_FEEDBACK_BOARD_DELAY <value>
1.4.17. STA_AUTO_REPORT_SETUP_SUMMARY
Directs the Timing Analyzer to automatically generate Setup Summary report whenever this project is opened in an interactive Timing Analyzer session.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name STA_AUTO_REPORT_SETUP_SUMMARY <value>
Default Value
On
1.4.18. STA_AUTO_UPDATE_TIMING_NETLIST
Directs the Timing Analyzer to automatically create the timing netlist, read SDC constraints, and update the timing netlist whenever this project is opened in an interactive Timing Analyzer session.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name STA_AUTO_UPDATE_TIMING_NETLIST <value>
Default Value
On
1.4.19. TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT
Instructs the Fitter to aggressively optimize for hold timing closure.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT <value>
Default Value
Off
1.4.20. TIMING_ANALYZER_DO_CCPP_REMOVAL
Directs the Timing Analyzer to remove common clock path pessimism (CCPP) during slack computation.
Old Name
TIMEQUEST_DO_CCPP_REMOVAL
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- EPC1
- EPC2
- Enhanced Configuration Devices
- Flash Memory
- Intel® Stratix® 10
- Virtual JTAG TAP
Notes
None
Syntax
set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL <value>
1.4.21. TIMING_ANALYZER_DO_REPORT_CDC_VIEWER
Directs the Timing Analyzer to report a table of all clock domain transfers for each analysis.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_CDC_VIEWER <value>
Default Value
Off
1.4.22. TIMING_ANALYZER_DO_REPORT_TIMING
Directs the Timing Analyzer to report the worst-case path per clock domain and analysis.
Old Name
TIMEQUEST_DO_REPORT_TIMING
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING <value>
Default Value
Off
1.4.23. TIMING_ANALYZER_MULTICORNER_ANALYSIS
Directs the Timing Analyzer to perform multicorner timing analysis, which analyzes the design against best-case and worst-case operating conditions. Turning on this option does not enable multicorner analysis in the Fitter.
Old Name
TIMEQUEST_MULTICORNER_ANALYSIS
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- EPC1
- EPC2
- Enhanced Configuration Devices
- Flash Memory
- Intel® Stratix® 10
- Virtual JTAG TAP
Notes
None
Syntax
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS <value>
1.4.24. TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS
Specifies the maximum number of worst-case timing paths for the Timing Analyzer to report per clock domain and analysis.
Old Name
TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
INTEGER_RANGE
1, 100000
Notes
None
Syntax
set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS <value>
Default Value
10
1.4.25. TIMING_ANALYZER_REPORT_SCRIPT
Specifies the name of the tcl script that will be used to overwrite the default Timing Analyzer report panels created during a normal compile.
Old Name
TIMEQUEST_REPORT_SCRIPT
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT <value>
1.4.26. TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
Directs the Timing Analyzer to perform default timing analysis prior to running the user-specified report script specified by TIMING_ANALYZER_REPORT_SCRIPT.
Old Name
TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS <value>
Default Value
On
1.4.27. TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS
Directs the Timing Analyzer to report worst-case timing paths per clock domain and analysis.
Old Name
TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- EPC1
- EPC2
- Enhanced Configuration Devices
- Flash Memory
- Intel® Stratix® 10
- Virtual JTAG TAP
Notes
None
Syntax
set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS <value>
Default Value
On
1.4.28. TIMING_ANALYZER_SIMULTANEOUS_MULTICORNER_ANALYSIS
When multicorner timing analysis is enabled, directs the Timing Analyzer to analyze all corners at once, rather than only analyzing corners that are explicitly asked for. This can save time when it is known that analysis of multiple corners will be needed at some point. If analysis is only needed for a single corner, turning off this setting will save memory.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name TIMING_ANALYZER_SIMULTANEOUS_MULTICORNER_ANALYSIS <value>
Default Value
On
1.4.29. TIMING_ANAYZER_REPORT_WORST_CASE_TIMING_PATHS_SHOW_ROUTING
Toggles detailed routing information for each timing path.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name TIMING_ANAYZER_REPORT_WORST_CASE_TIMING_PATHS_SHOW_ROUTING <value>
Default Value
Off
1.4.30. USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
Instructs STA to take DLL frequency into account while calculating phase shift of DQS delay chain
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN <value>
Default Value
Off
1.5. Compiler Assignments
1.5.1. ALLOW_REGISTER_DUPLICATION
Controls whether the Compiler is allowed to duplicate registers to improve design performance. When register duplication is allowed, the Compiler may perform optimizations that create a second copy of a register and move a portion of its fan-out to this new node, in order to improve routability and/or reduce the total routing wire required to route a net with many fan-outs.\r\n\r\nIf register duplication is disabled, optimizations that retime registers will also be disabled.\r\n\r\nThis setting affects Analysis & Synthesis and the Fitter.
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
This assignment is included in the Fitter report.
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ALLOW_REGISTER_DUPLICATION <value>
Default Value
On
Example
set_global_assignment -name allow_register_duplication on
1.5.2. ALLOW_REGISTER_MERGING
Controls whether the Compiler is allowed to remove registers that are identical to other registers in the design. When register merging is allowed, in cases where two registers generate the same logic, one may be deleted and the remaining one will be made to also fan-out to the deleted register's destinations. This option is useful if you wish to prevent the Compiler from removing duplicate registers that you have used deliberately.\r\n\r\nIf register merging is disabled, optimizations that retime registers will also be disabled.\r\n\r\nThis setting affects Analysis & Synthesis and the Fitter.
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
This assignment is included in the Fitter report.
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name ALLOW_REGISTER_MERGING <value>
Default Value
On
Example
set_global_assignment -name allow_register_merging off
1.5.3. ALLOW_REGISTER_RETIMING
Controls whether the Compiler is allowed to retime registers to improve design performance. When register retiming is allowed, the Compiler may perform optimizations that move combinational logic across register boundaries, maintaining the overall logic of the design component but also balancing the data path delays between each register.\r\n\r\nThis setting affects the Fitter.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ALLOW_REGISTER_RETIMING <value> set_instance_assignment -name ALLOW_REGISTER_RETIMING -to <to> -entity <entity name> <value>
Default Value
On
Example
set_global_assignment -name allow_register_retiming on
1.5.4. OPTIMIZATION_MODE
Controls the Compiler's high-level optimization strategy. By default, the Quartus Prime Compiler optimizes in a balanced mode, targeting the design's timing constraints. The alternate modes cause the Compiler to prioritize a particular optimization metric. High effort modes primarily enable additional optimizations that increase compilation time. Superior and Aggressive modes may increase compilation time and also make trade-offs that may harm the other optimization metrics (performance, area, etc.).\r\n\r\n'High Performance Effort' mode will cause the compiler to target increased positive timing margin, increase the timing optimization effort applied during placement and routing, and enable timing-related Physical Synthesis optimizations (as allowed by the register optimization settings below). Each of these additional optimizations can increase compilation time. 'Superior Performance' mode enables the same optimizations as 'High Performance Effort' mode, and additionally enables options during Analysis & Synthesis to maximize design performance at a potential increase to logic area. If design utilization is already very high, this option may lead to difficulty in fitting which could also negatively affect overall optimization quality. Modes with Maximum Placement Effort increase placement optimization effort by an additional amount.\r\n\r\n'High Routability Effort' modes guide Placement or Packing to spend additional compilation time reducing routing utilization, which can improve routability and also saves dynamic power. 'Optimize Netlist for Routability' mode makes netlist modifications to increase routability at the possible expense of performance. In 'Aggressive Power' mode, the Compiler will further target reducing the routing usage of signals with the highest specified (via Signal Activity File) or estimated toggle rates, saving additional dynamic power but potentially affecting performance.\r\n\r\n'Aggressive Area' mode instructs the Compiler to target an area minimal solution, even if this reduces overall timing performance.\r\n\r\n'Aggressive Compile Time' mode instructs the Compiler to reduce performance optimization effort and perform minimal reporting in order to save compile time.\r\n\r\nThis setting affects Analysis & Synthesis and the Fitter.
Type
Enumeration
Values
- Aggressive Area
- Aggressive Compile Time
- Aggressive Power
- Balanced
- High Packing Routability Effort
- High Performance Effort
- High Performance Effort with Maximum Placement Effort
- High Placement Routability Effort
- High Power Effort
- High Routability Effort
- Optimize Netlist for Routability
- Superior Performance
- Superior Performance with Maximum Placement Effort
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
This assignment is included in the Analysis & Synthesis report.
Syntax
set_global_assignment -name OPTIMIZATION_MODE <value>
Default Value
Balanced
1.6. Design Assistant Assignments
1.6.1. CLK_RULE_CLKNET_CLKSPINES_THRESHOLD
Specifies the threshold value for clock net not mapped to clock spines rule.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD <value>
Default Value
25
1.6.2. DA_CUSTOM_RULE_FILE
Used to set the path for DA custom rule file
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name DA_CUSTOM_RULE_FILE <value>
1.6.3. DESIGN_ASSISTANT_EXCLUDE
Specify that a Design Assistant rule should ignore the target of the assignment. If set on an instance, the exclusion applies to the whole contents of that instance, regardless of any DESIGN_ASSISTANT_INCLUDE assignments targeting any sub-instance. If the assignment is global, or if it's set on the design root, it can be overridden by DESIGN_ASSISTANT_INCLUDE assignments to instances.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports wildcards.
This assignment is copied to any duplicated nodes.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name DESIGN_ASSISTANT_EXCLUDE <value> set_instance_assignment -name DESIGN_ASSISTANT_EXCLUDE -to <to> -entity <entity name> <value>
1.6.4. DESIGN_ASSISTANT_INCLUDE
Specify that a Design Assistant rule should not ignore the target of the assignment. It can only be used to override a DESIGN_ASSISTANT_EXCLUDE assignment set globally or on the design root.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports wildcards.
This assignment is copied to any duplicated nodes.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name DESIGN_ASSISTANT_INCLUDE <value> set_instance_assignment -name DESIGN_ASSISTANT_INCLUDE -to <to> -entity <entity name> <value>
1.6.5. DRC_DEADLOCK_STATE_LIMIT
Specifies the maximum number of states that you want the Design Assistant to detect as a deadlock condition. A larger number will results in longer processing time.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT <value>
Default Value
2
1.6.6. DRC_DETAIL_MESSAGE_LIMIT
Specifies the maximum number of detail messages that you want the Design Assistant to report.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT <value>
Default Value
10
1.6.7. DRC_FANOUT_EXCEEDING
Specifies the minimum amount of fan-out that a node must have to be reported by the Design Assistant.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name DRC_FANOUT_EXCEEDING <value>
Default Value
30
1.6.8. DRC_GATED_CLOCK_FEED
Specifies the minimum amount of clock port a gated clock must feed so that it's an acceptable gated clock.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name DRC_GATED_CLOCK_FEED <value>
Default Value
30
1.6.9. DRC_REPORT_FANOUT_EXCEEDING
Directs the Design Assistant to report all nodes with more than the specified amount of fan-out.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name DRC_REPORT_FANOUT_EXCEEDING <value>
1.6.10. DRC_REPORT_TOP_FANOUT
Directs the Design Assistant to report the specified number of nodes with the highest fan-out.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name DRC_REPORT_TOP_FANOUT <value>
1.6.11. DRC_TOP_FANOUT
Specifies the number of nodes with the highest fan-out that you want the Design Assistant to report.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name DRC_TOP_FANOUT <value>
Default Value
50
1.6.12. DRC_VIOLATION_MESSAGE_LIMIT
Specifies the maximum number of violation messages that you want the Design Assistant to report.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT <value>
Default Value
30
1.6.13. HARDCOPY_FLOW_AUTOMATION
Specifies which HardCopy flow will be run in HardCopy timing wizard
Type
Enumeration
Values
- COMPILE_NEW_PROJECT
- FULL_COMPILATION
- MIGRATION_ONLY
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION <value>
Default Value
MIGRATION_ONLY
1.6.14. HARDCOPY_NEW_PROJECT_PATH
Specifies the directory path for the new/migrated HardCopy project.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name HARDCOPY_NEW_PROJECT_PATH <value>
1.6.15. HCPY_CAT
Direct Design Assistant to detect HardCopy rules on the design. All HardCopy rules apply to HardCopy devices only.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name HCPY_CAT <value>
1.6.16. HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES
Direct Design Assistant to detect PLL that feeds multiple clock network types.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES <value>
1.6.17. HCPY_VREF_PINS
Direct Design Assistant to detect VREF pins on the design. This rule applies to HardCopy devices only.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name HCPY_VREF_PINS <value>
1.7. Design Partition Assignments
1.7.1. ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS
Allows the Compiler to optimize connections from a partition's outputs to its inputs by making the path internal to the partition. You must also enable the cross-boundary optimizations feature for this partition using the CROSS_BOUNDARY_OPTIMIZATIONS assignment.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier and entity name
1.7.2. AUTOMATIC_DANGLING_PORT_TIEOFF
Disable automatic tie-off of dangling boundary ports in the partition rooted at the specified instance.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name AUTOMATIC_DANGLING_PORT_TIEOFF -to <to> <value>
1.7.3. CROSS_BOUNDARY_OPTIMIZATIONS
This setting specifies whether the Compiler should optimize across the partition's boundary. If enabled, the Compiler may be able to optimize the logic inside the partition by applying various cross-boundary optimizations, such as constant propagation and dangling logic removal. Specific cross-boundary optimizations are enabled by individual assignments.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier and entity name
1.7.4. EMPTY
Directs the compiler to empty a partition.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
Syntax
set_instance_assignment -name EMPTY -to <to> -entity <entity name> <value>
1.7.5. ENABLE_LAB_SHARING_WITH_PARENT_PARTITION
Allows logic from the target partition to share LAB resources with the immediate parent partition.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
Syntax
set_instance_assignment -name ENABLE_LAB_SHARING_WITH_PARENT_PARTITION -to <to> -entity <entity name> -section_id <section identifier> <value>
1.7.6. ENTITY_REBINDING
Entity Re-binding binds the Partial Reconfiguration/Reserved Core partition instance to its corresponding entity.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name ENTITY_REBINDING -to <to> -entity <entity name> <value>
1.7.7. EXPORT_BLOCK_NAME_OBFUSCATION
Obfuscate all names under this hierarchy during export.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_instance_assignment -name EXPORT_BLOCK_NAME_OBFUSCATION -to <to> <value>
1.7.8. IGNORE_PARTITIONS
Specifies whether the compiler should ignore partition assignments in the project.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is not copied when you create a companion revision for HardCopy II devices.
Syntax
set_global_assignment -name IGNORE_PARTITIONS <value>
Default Value
Off
1.7.9. INCREMENTAL_COMPILATION_EXPORT_FLATTEN
Specifies whether the netlist exported to the QXP file should flatten sub-partitions
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is not copied when you create a companion revision for HardCopy II devices.
Syntax
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_FLATTEN <value>
1.7.10. INCREMENTAL_COMPILATION_EXPORT_POST_FIT
Specifies whether the exported QXP file contains the post-fit netlist
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is not copied when you create a companion revision for HardCopy II devices.
Syntax
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_POST_FIT <value>
1.7.11. INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH
Specifies whether the exported QXP file contains the post-synthesis netlist
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is not copied when you create a companion revision for HardCopy II devices.
Syntax
set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH <value>
1.7.12. INSERT_BOUNDARY_WIRE_LUTS
Enables wire lut insertion for boundary ports in the given partition (the partition is named by hierarchy path). This ensures that the inputs and outputs can have their locations preserved, which is useful for partial reconfiguration and compiling a design containing a blackbox.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
Syntax
set_instance_assignment -name INSERT_BOUNDARY_WIRE_LUTS -to <to> -entity <entity name> <value>
1.7.13. MERGE_EQUIVALENT_BIDIRS
Allows the Compiler to merge electrically equivalent bidirectional inputs. You must also enable the cross-boundary optimizations feature for this partition using the CROSS_BOUNDARY_OPTIMIZATIONS assignment.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name MERGE_EQUIVALENT_BIDIRS -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier and entity name
1.7.14. MERGE_EQUIVALENT_INPUTS
Allows the Compiler to merge inputs connected to the same source. You must also enable the cross-boundary optimizations feature for this partition using the CROSS_BOUNDARY_OPTIMIZATIONS assignment.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name MERGE_EQUIVALENT_INPUTS -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name MERGE_EQUIVALENT_INPUTS -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier and entity name
1.7.15. PARTIAL_RECONFIGURATION_PARTITION
Specifies if this partition in the design is partially reconfigurable.
Old Name
PR_PARTITION
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
Syntax
set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION -to <to> -entity <entity name> <value>
1.7.16. PARTITION
Creates a partition rooted at the specified instance. When an instance is defined as a partition, its hierarchical boundaries are fixed, allowing it to be independently exported or imported in many cases. The value of this assignment is the name of the design block that contains the implementation for the partition. The partition name must be unique in the complete design across all hierarchies.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name PARTITION -to <to> -entity <entity name> <value>
1.7.17. PARTITION_ALWAYS_USE_QXP_NETLIST
Specifies whether to always use the netlist in the QXP file associated with the partition, either because the QXP file is imported into the partition, or is specified as a source file for the partition. Setting defaults to off.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is not copied when you create a companion revision for HardCopy II devices.
Syntax
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier and entity name
1.7.18. PARTITION_ASD_REGION
Specifies the advanced SEU detection region assignment for this partition.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
Syntax
set_instance_assignment -name PARTITION_ASD_REGION -to <to> -entity <entity name> <value>
1.7.19. PARTITION_ASD_REGION_ID
Indicates the advanced sensitivity detection region assignment for this partition.
Type
Integer
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
This assignment is not copied when you create a companion revision for HardCopy II devices.
Syntax
set_global_assignment -name PARTITION_ASD_REGION_ID -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name PARTITION_ASD_REGION_ID -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
1, requires section identifier and entity name
1.7.20. PARTITION_IGNORE_SOURCE_FILE_CHANGES
Specifies whether to use the requested post-synthesis or post-fit netlist when it is available, even when source file changes are present. Setting defaults to off.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is not copied when you create a companion revision for HardCopy II devices.
Syntax
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier and entity name
1.7.21. PARTITION_PRESERVE_HIGH_SPEED_TILES
Specifies whether to preserve the high-speed tiles in the post-fit netlist, if applicable.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is not copied when you create a companion revision for HardCopy II devices.
Syntax
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier and entity name
1.7.22. PRESERVE
Directs the compiler to preserve the existing results of a partition. The value of this assignment is the snapshot to preserve, such as \"final\" or \"placed.\" If the specified snapshot does not exist, the compiler will exit with an error message. By default, the partition's results will not be preserved unless the only results available for the partition are later than the stage currently being compiled. For example, if the only snapshot for a partition is the \"placed\" snapshot, the Fitter will preserve the partition until the end of placement, and will not attempt to preserve it during routing.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name PRESERVE -to <to> -entity <entity name> <value>
1.7.23. PROPAGATE_CONSTANTS_ON_INPUTS
Allows the Compiler to use constants on a partition input to optimize the logic in the partition. You must also enable the cross-boundary optimizations feature for the partition using the CROSS_BOUNDARY_OPTIMIZATIONS assignment.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier and entity name
1.7.24. PROPAGATE_INVERSIONS_ON_INPUTS
Specifies that the Compiler should push inversions into partition inputs when possible. This cross-boundary optimization is especially important when inverted clock or asynchronous signals are connected to a partition input. Without this optimization, the Compiler may need to implement the inversion with a logic cell, introducing skew on the clock or reset path. The partition must also have enabled cross-boundary optimizations with the CROSS_BOUNDARY_OPTIMIZATIONS assignment.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier and entity name
1.7.25. QDB_FILE_PARTITION
Similar to the PARTITION assignment, this assignment creates a partition rooted at the specified instance. When an instance is defined as a partition, its hierarchical boundaries are fixed, allowing it to be independently exported or imported in many cases. The value of the assignment is the QDB partition archive that will be imported into the partition during Synthesis.\n\nIf a PARTITION and QDB_FILE_PARTITION assignment target the same instance then the PARTITION assignment determines the partition's name. If no PARTITION assignment exists then the partition name will be automatically created.
Type
File name
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name QDB_FILE_PARTITION -to <to> -entity <entity name> <value>
1.7.26. QDB_PATH
Specify path to read and write compiler generated database to a directory other than project directory.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name QDB_PATH <value>
1.7.27. REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS
Allows the Compiler to remove logic connected to dangling partitions outputs. You must also enable the cross-boundary optimizations feature for this partition using the CROSS_BOUNDARY_OPTIMIZATIONS assignment.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS -entity <entity name> -section_id <section identifier> <value> set_instance_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS -to <to> -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier and entity name
1.7.28. RESERVED_CORE
Specifies that a core design partition can be compiled with preserved periphery from a Partition Database File (.qdb).
Old Name
PERIPHERY_REUSE_CORE
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
Syntax
set_instance_assignment -name RESERVED_CORE -to <to> -entity <entity name> <value>
1.8. EDA Netlist Writer Assignments
1.8.1. EDA_BOARD_BOUNDARY_SCAN_OPERATION
Specify the BSDL file operation either for pre-configuration or post-configuration
Type
Enumeration
Values
- POST_CONFIG
- PRE_CONFIG
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION -section_id <section identifier> <value>
Default Value
PRE_CONFIG, requires section identifier
1.8.2. EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL
Specifies the boundary scan format used for board level boundary scan testing.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL <value> set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL -entity <entity name> <value>
Default Value
<None>
1.8.3. EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL
Specifies the EDA third-party tool used for board level signal integrity analysis.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL <value> set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL -entity <entity name> <value>
Default Value
<None>
1.8.4. EDA_BOARD_DESIGN_SYMBOL_TOOL
Specifies the EDA third-party tool used for board level schematic design.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL <value> set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL -entity <entity name> <value>
Default Value
<None>
1.8.5. EDA_BOARD_DESIGN_TIMING_TOOL
Specifies the EDA third-party tool used for board level timing analysis.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL <value> set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL -entity <entity name> <value>
Default Value
<None>
1.8.6. EDA_BOARD_DESIGN_TOOL
Specifies the EDA third-party tool used for board level design and analysis.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_BOARD_DESIGN_TOOL <value> set_global_assignment -name EDA_BOARD_DESIGN_TOOL -entity <entity name> <value>
Default Value
<None>
1.8.7. EDA_DESIGN_EXTRA_ALTERA_SIM_LIB
Specify additional ALTERA simulation model libraries required is used by the design files
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_DESIGN_EXTRA_ALTERA_SIM_LIB -section_id <section identifier> <value>
1.8.8. EDA_DESIGN_INSTANCE_NAME
Specify the instance name of the design in the test bench
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME -section_id <section identifier> <value>
1.8.9. EDA_ENABLE_GLITCH_FILTERING
Write logic to filter glitches in the simulation netlist.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING -section_id <section identifier> <value> set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.10. EDA_ENABLE_IPUTF_MODE
Allows you to simulate designs containing hw.tcl based IP cores. This may require adding .sip files to your Quartus Prime project. This variable may be removed in future releases.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_ENABLE_IPUTF_MODE -section_id <section identifier> <value> set_global_assignment -name EDA_ENABLE_IPUTF_MODE -entity <entity name> -section_id <section identifier> <value>
Default Value
On, requires section identifier
1.8.11. EDA_EXTRA_ELAB_OPTION
Additional custom simulation elaboration options for one or more simulators.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_EXTRA_ELAB_OPTION -section_id <section identifier> <value> set_global_assignment -name EDA_EXTRA_ELAB_OPTION -entity <entity name> -section_id <section identifier> <value>
Default Value
"", requires section identifier
1.8.12. EDA_FLATTEN_BUSES
Flattens all buses when creating the VHDL Output File (.vho). You should turn on this option if your third-party EDA environment does not support buses.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_FLATTEN_BUSES -section_id <section identifier> <value> set_global_assignment -name EDA_FLATTEN_BUSES -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.13. EDA_FORCE_GATE_LEVEL_REG_INIT_X
Modifies output gate level simulation netlist to force all registers to initialize to X (don't care) and propagate X
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_FORCE_GATE_LEVEL_REG_INIT_X -section_id <section identifier> <value> set_global_assignment -name EDA_FORCE_GATE_LEVEL_REG_INIT_X -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.14. EDA_FORMAL_VERIFICATION_ALLOW_RETIMING
Allow register retiming to be turned on for formal verification
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING -section_id <section identifier> <value> set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.15. EDA_FORMAL_VERIFICATION_TOOL
Specifies the EDA third-party tool used for formal verification.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL <value> set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL -entity <entity name> <value>
Default Value
<None>
1.8.16. EDA_FV_HIERARCHY
Determines how the hierarchy of design entities is to be processed during compilation. 'BLACKBOX' setting causes the entity to be handled as a black-box in the EDA flow. 'NONE' setting is the default and means no special handling to be done. The option applies only to the design entity to which it is assigned; lower-level entities do not inherit their parent entity's setting for this option.
Type
Enumeration
Values
- BLACKBOX
- Off
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_FV_HIERARCHY -entity <entity name> <value> set_instance_assignment -name EDA_FV_HIERARCHY -to <to> -entity <entity name> <value>
1.8.17. EDA_GENERATE_POWER_INPUT_FILE
Generates a Power Input File (.pwf) to perform power analysis in the Quartus Prime software when using third-party simulation tools.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE -section_id <section identifier> <value> set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.18. EDA_GENERATE_SDF_FOR_POWER
Enable generation of SDO file containing delay estimates back-annotated on design netlist for improved accuracy of power estimates. This is only supported for Verilog Output simulation in ModelSim
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name EDA_GENERATE_SDF_FOR_POWER -section_id <section identifier> <value> set_global_assignment -name EDA_GENERATE_SDF_FOR_POWER -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.19. EDA_GENERATE_TIMING_CLOSURE_DATA
Generates back-annotation data for performing in-place optimization with the LeonardoSpectrum software.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA -section_id <section identifier> <value> set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.20. EDA_IBIS_EXTENDED_MODEL_SELECTOR
Enable or disable information about related IO Standards in the model selector section of IBIS files. Will turn on EDA_IBIS_MODEL_SELECTOR when set to true.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR -section_id <section identifier> <value> set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.21. EDA_IBIS_MODEL_SELECTOR
Enable or disable model selector feature for IBIS Writer
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR -section_id <section identifier> <value> set_global_assignment -name EDA_IBIS_MODEL_SELECTOR -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.22. EDA_IBIS_MUTUAL_COUPLING
Allows you to print the per pin RLC package model with mutual coupling when generating IBIS Output Files (.ibs) with the EDA Netlist Writer. The lumped RLC package model information appears in the IBIS Output File.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING -section_id <section identifier> <value> set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.23. EDA_IBIS_SPECIFICATION_VERSION
Specifies the IBIS Specification version.
Type
Enumeration
Values
- 4p2
- 5p0
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Syntax
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION -section_id <section identifier> <value>
Default Value
4p2, requires section identifier
1.8.24. EDA_IPFS_FILE
Specifies the library to which IPFS file should be compiled
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_IPFS_FILE -section_id <section identifier> <value>
1.8.25. EDA_LAUNCH_CMD_LINE_TOOL
Allows you to launch third-party EDA tools in the command-line mode rather than opening the graphical user interface.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL -section_id <section identifier> <value> set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.26. EDA_MAP_ILLEGAL_CHARACTERS
Maps the vertical bar (|), tilde (~), and colon (:) characters in Quartus Prime hierarchical node names to the legal Verilog HDL characters z, x, and underscore (_), respectively, in Verilog Output Files. Turning on this option also maps other illegal non-alphanumeric characters, including brackets [], parentheses, (), angle brackets <>, and braces {} to underscores (_).
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -section_id <section identifier> <value> set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.27. EDA_NATIVELINK_GENERATE_SCRIPT_ONLY
Allows you to generate the script for a third-party EDA tool without running the EDA tool.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.28. EDA_NATIVELINK_PORTABLE_FILE_PATHS
Specifies that the file paths in the generated third-party EDA tool command scripts should be written out using relative paths for design and testbench files, and by using a variable to refer to Quartus Prime simulation library path.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS -section_id <section identifier> <value> set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.29. EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT
Specify the script for EDA Tool. After compiling models, design files and test bench files, Native Link uses this script to set up the simulation
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT -section_id <section identifier> <value>
1.8.30. EDA_NATIVELINK_SIMULATION_TEST_BENCH
Specify the active logical name of the test bench, that will be used to perform NativeLink Simulation
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH -section_id <section identifier> <value>
1.8.31. EDA_NETLIST_WRITER_OUTPUT_DIR
Specify the output directory for EDA Netlist Writer
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR -section_id <section identifier> <value>
1.8.32. EDA_RESYNTHESIS_TOOL
Specifies the EDA tool used for resynthesis.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_RESYNTHESIS_TOOL <value> set_global_assignment -name EDA_RESYNTHESIS_TOOL -entity <entity name> <value>
Default Value
<None>
1.8.33. EDA_RTL_SIMULATION_RUN_SCRIPT
Specifies the script file for performing RTL simulation using third-party simulation software.
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_RTL_SIMULATION_RUN_SCRIPT -section_id <section identifier> <value> set_global_assignment -name EDA_RTL_SIMULATION_RUN_SCRIPT -entity <entity name> -section_id <section identifier> <value>
1.8.34. EDA_RTL_SIM_MODE
Enables the Advanced Options - VHDL or Verilog Simulation options for Test Bench mode or Command/macro mode.
Type
Enumeration
Values
- COMMAND_MACRO_MODE
- NOT_USED
- TEST_BENCH_MODE
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_RTL_SIM_MODE -section_id <section identifier> <value> set_global_assignment -name EDA_RTL_SIM_MODE -entity <entity name> -section_id <section identifier> <value>
Default Value
NOT_USED, requires section identifier
1.8.35. EDA_RTL_TEST_BENCH_FILE_NAME
Specifies the RTL simulation test bench file name for Test Bench Mode. File type can be a VHDL Test Bench File (.vht), VHDL File (.vhd), Verilog HDL Test Bench File (.vt), or Verilog HDL file (.v).
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_RTL_TEST_BENCH_FILE_NAME -entity <entity name> -section_id <section identifier> <value>
1.8.36. EDA_RTL_TEST_BENCH_NAME
Specifies the name of top-level test bench in RTL simulation test bench file.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_RTL_TEST_BENCH_NAME -entity <entity name> -section_id <section identifier> <value>
1.8.37. EDA_RTL_TEST_BENCH_RUN_FOR
Specifies the time duration for RTL simulation using third-party simulation.
Type
Time
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_RTL_TEST_BENCH_RUN_FOR -section_id <section identifier> <value> set_global_assignment -name EDA_RTL_TEST_BENCH_RUN_FOR -entity <entity name> -section_id <section identifier> <value>
1.8.38. EDA_SDC_FILE_NAME
Name of Design Constraints file to be sourced in scripts generated for third party tools
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_SDC_FILE_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_SDC_FILE_NAME -entity <entity name> -section_id <section identifier> <value>
1.8.39. EDA_SIMULATION_RUN_SCRIPT
Specifies the script file for running a third-party simulation in Command/macro mode.
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT -section_id <section identifier> <value> set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT -entity <entity name> -section_id <section identifier> <value>
1.8.40. EDA_SIMULATION_TOOL
Specifies the third-party EDA tool used for simulation.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_SIMULATION_TOOL <value> set_global_assignment -name EDA_SIMULATION_TOOL -entity <entity name> <value>
Default Value
<None>
1.8.41. EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
Specifies the instance name of the design entity in the test bench file.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_TEST_BENCH_DESIGN_INSTANCE_NAME -entity <entity name> -section_id <section identifier> <value>
1.8.42. EDA_TEST_BENCH_ENABLE_STATUS
Enables the Advanced Options - VHDL or Verilog Simulation options for Test Bench mode or Command/macro mode.
Type
Enumeration
Values
- COMMAND_MACRO_MODE
- NOT_USED
- TEST_BENCH_MODE
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS -section_id <section identifier> <value> set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS -entity <entity name> -section_id <section identifier> <value>
Default Value
NOT_USED, requires section identifier
1.8.43. EDA_TEST_BENCH_ENTITY_MODULE_NAME
Specifies the top-level design entity in the test bench file.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_TEST_BENCH_ENTITY_MODULE_NAME -entity <entity name> -section_id <section identifier> <value>
1.8.44. EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB
Tells NativeLink to add extra simulation libraries to the specified module. This is required by the memory controllers (both new and legacy).
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB -section_id <section identifier> <value>
1.8.45. EDA_TEST_BENCH_FILE
Associates a test bench file with the logical test bench name
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_FILE -section_id <section identifier> <value>
1.8.46. EDA_TEST_BENCH_FILE_NAME
Specifies the test bench file name for Test Bench Mode. File type can be a VHDL Test Bench File (.vht), Verilog HDL Test Bench File (.vt), or another design file type.
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_FILE_NAME -section_id <section identifier> <value> set_global_assignment -name EDA_TEST_BENCH_FILE_NAME -entity <entity name> -section_id <section identifier> <value>
1.8.47. EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY
Specify the simulation library to which Gate Level Netlist will be compiled
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY -section_id <section identifier> <value>
1.8.48. EDA_TEST_BENCH_MODULE_NAME
Associates a test bench file with the logical test bench name
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME -section_id <section identifier> <value>
1.8.49. EDA_TEST_BENCH_NAME
Define a logical name for test bench. Each test bench logical name has associated section, containing test bench information, and section_id being the logical test bench name.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_TEST_BENCH_NAME -section_id <section identifier> <value>
1.8.50. EDA_TEST_BENCH_RUN_FOR
Specifies the simulation run time for a third-party simulation in Test Bench Mode.
Type
Time
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_TEST_BENCH_RUN_FOR -section_id <section identifier> <value> set_global_assignment -name EDA_TEST_BENCH_RUN_FOR -entity <entity name> -section_id <section identifier> <value>
1.8.51. EDA_TEST_BENCH_RUN_SIM_FOR
Specify the time interval for running EDA Simulation
Type
Time
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR -section_id <section identifier> <value>
1.8.52. EDA_TIME_SCALE
Specifies the time unit used to represent timing delays in each Verilog Output File. The value for the Time Scale option may be between 0.001 ns and 10ns, and should be a multiple of 10.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_TIME_SCALE -section_id <section identifier> <value> set_global_assignment -name EDA_TIME_SCALE -entity <entity name> -section_id <section identifier> <value>
1.8.53. EDA_TIMING_ANALYSIS_TOOL
Specifies the EDA third-party tool used for timing analysis.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL <value> set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL -entity <entity name> <value>
Default Value
<None>
1.8.54. EDA_TRUNCATE_LONG_HIERARCHY_PATHS
Truncate hierarchical node names to 80 characters.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS -section_id <section identifier> <value> set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.55. EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY
Specify the directory where you store the library generated with the EDA Simulation Library Compiler tool. Note: Do not use this option to specify the directory for ModelSim - Intel FPGA precompiled libraries or Active-HDL precompiled libraries.
Type
File name
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY -section_id <section identifier> <value>
Default Value
<None>, requires section identifier
1.8.56. EDA_VHDL_ARCH_NAME
Specify the name of Architecture in the generated VHDL simulation netlist.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_VHDL_ARCH_NAME -section_id <section identifier> <value>
Default Value
structure, requires section identifier
1.8.57. EDA_WAIT_FOR_GUI_TOOL_COMPLETION
Specifies that NativeLink should wait for the EDA tool GUI launched by it to finish.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.58. EDA_WRITER_DONT_WRITE_TOP_ENTITY
Do not write top-level entity in VHDL Output File (.vho).
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.59. EDA_WRITE_DEVICE_CONTROL_PORTS
Add the devpor, devclrn, and devoe signals in the design as input ports in the top-level design hierarchy in the Verilog or VHDL simulation netlist for the project.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -section_id <section identifier> <value> set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS -entity <entity name> -section_id <section identifier> <value>
Default Value
Off, requires section identifier
1.8.60. EDA_WRITE_NODES_FOR_POWER_ESTIMATION
Write script for Simulation tool to generate VCD file for outputs for power estimation.
Type
Enumeration
Values
- ALL_NODES
- NO_COMBINATIONAL_OUTPUT
- Off
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION -section_id <section identifier> <value> set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION -entity <entity name> -section_id <section identifier> <value>
Default Value
OFF, requires section identifier
1.9. Equivalence Checker Assignments
1.9.1. EQC_AUTO_BREAK_CONE
Enable EQC for auto cone break when compare is abort.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_AUTO_BREAK_CONE <value>
Default Value
On
1.9.2. EQC_AUTO_COMP_LOOP_CUT
Enable EQC for auto cut comp loop.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT <value>
Default Value
On
1.9.3. EQC_AUTO_INVERSION
Enable EQC for auto check inversion level.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_AUTO_INVERSION <value>
Default Value
On
1.9.4. EQC_AUTO_PORTSWAP
Enable EQC auto swap the port.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_AUTO_PORTSWAP <value>
Default Value
On
1.9.5. EQC_AUTO_TERMINATE
Enable auto terminates when conclusion(not equivalent or undecided) is met.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_AUTO_TERMINATE <value>
Default Value
On
1.9.6. EQC_BBOX_MERGE
Enable EQC automatic merge black box.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_BBOX_MERGE <value>
Default Value
On
1.9.7. EQC_CONSTANT_DFF_DETECTION
Enable EQC automatic constant DFF detection
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION <value>
Default Value
On
1.9.8. EQC_DETECT_DONT_CARES
Enable EQC detect don't cares.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_DETECT_DONT_CARES <value>
Default Value
On
1.9.9. EQC_DFF_SS_EMULATION
Enable EQC DFF secondary signal emulation.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_DFF_SS_EMULATION <value>
Default Value
On
1.9.10. EQC_DUPLICATE_DFF_DETECTION
Enable EQC automatic duplicate DFF detection
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION <value>
Default Value
On
1.9.11. EQC_LVDS_MERGE
Enable EQC automatic merge LVDS.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_LVDS_MERGE <value>
Default Value
On
1.9.12. EQC_MAC_REGISTER_UNPACK
Enable EQC for auto unpack MAC register.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_MAC_REGISTER_UNPACK <value>
Default Value
On
1.9.13. EQC_PARAMETER_CHECK
Enable EQC check parameter.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_PARAMETER_CHECK <value>
Default Value
On
1.9.14. EQC_POWER_UP_COMPARE
Enable EQC for comparing on the power-up level .
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_POWER_UP_COMPARE <value>
Default Value
Off
1.9.15. EQC_RAM_REGISTER_UNPACK
Enable EQC for auto unpack RAM register.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_RAM_REGISTER_UNPACK <value>
Default Value
On
1.9.16. EQC_RAM_UNMERGING
Enable EQC automatic unmerge RAM.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_RAM_UNMERGING <value>
Default Value
On
1.9.17. EQC_RENAMING_RULES
Enable EQC use renaming rules.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_RENAMING_RULES <value>
Default Value
On
1.9.18. EQC_RENAMING_RULES_LIST
Store eqc renaming rules
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
Syntax
set_global_assignment -name EQC_RENAMING_RULES_LIST <value>
1.9.19. EQC_SET_PARTITION_BB_TO_VCC_GND
Enable EQC for set partition Black-box unconnected input to VCC or GND.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND <value>
Default Value
On
1.9.20. EQC_SHOW_ALL_MAPPED_POINTS
Enable EQC show all mapped points.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS <value>
Default Value
Off
1.9.21. EQC_STRUCTURE_MATCHING
Enable EQC for map using structure matching.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_STRUCTURE_MATCHING <value>
Default Value
On
1.9.22. EQC_SUB_CONE_REPORT
Enable EQC show sub cone report.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name EQC_SUB_CONE_REPORT <value>
Default Value
Off
1.10. Fitter Assignments
1.10.1. ACTIVE_SERIAL_CLOCK
Specifies the clock source for Fast Active Serial programming.
Type
Enumeration
Values
- AS_FREQ_100MHZ
- AS_FREQ_108MHZ
- AS_FREQ_115MHZ_IOSC
- AS_FREQ_125MHZ
- AS_FREQ_133MHZ
- AS_FREQ_166_6MHZ
- AS_FREQ_25MHZ
- AS_FREQ_25MHZ_IOSC
- AS_FREQ_38MHZ_IOSC
- AS_FREQ_50MHZ
- AS_FREQ_58MHZ_IOSC
- AS_FREQ_71_5MHZ
- AS_FREQ_77MHZ_IOSC
- AS_FREQ_80MHZ
- CLKUSR
- FREQ_100MHz
- FREQ_12_5MHz
- FREQ_20MHz
- FREQ_25MHz
- FREQ_40MHz
- FREQ_50MHz
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ACTIVE_SERIAL_CLOCK <value>
Example
set_global_assignment -name active_serial_clock "CLKUSR"
See Also
USER_START_UP_CLOCK
1.10.2. ALLOW_ROUTING_TO_PERIPHERY_THROUGH_GLOBAL_NETWORK
Specifies that a signal can be routed from an IO pin to periphery destinations using global routing paths. This allows the router to consider global and non-global routing paths and does not guarantee that a signal will be routed using global routing paths. Additionally, this will not route the signal to its destinations in a skew balanced manner. Only supported for Stratix 10 devices.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name ALLOW_ROUTING_TO_PERIPHERY_THROUGH_GLOBAL_NETWORK -to <to> <value> set_instance_assignment -name ALLOW_ROUTING_TO_PERIPHERY_THROUGH_GLOBAL_NETWORK -from <from> -to <to> <value>
Example
set_instance_assignment -name ALLOW_ROUTING_TO_PERIPHERY_THROUGH_GLOBAL_NETWORK ON -to clk
1.10.3. ALLOW_SEU_FAULT_INJECTION
Allow SEU fault injection.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name ALLOW_SEU_FAULT_INJECTION <value>
Example
set_global_assignment -name ALLOW_SEU_FAULT_INJECTION ON
1.10.4. ALLOW_VCCR_VCCT_PER_BANK
Allow VCCR VCCT power supply to be set per-six-bank instead of per-Crete
Type
Boolean
Device Support
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name ALLOW_VCCR_VCCT_PER_BANK <value>
Default Value
Off
Example
set_global_assignment -name ALLOW_VCCR_VCCT_PER_BANK ON
1.10.5. ALM_REGISTER_PACKING_EFFORT
This guides how aggressively the Fitter will pack ALMs when trying to place registers into desired LAB locations. Specifically, this option can be used to increase the usage of secondary register locations during placement. Increasing ALM packing density may lower the number of ALMs needed to fit the design but it may also reduce routing flexibility and timing performance. It should also be noted that this setting is used as a hint for the Fitter only. Low - The Fitter will avoid ALM packing configurations that combine LUTs and registers which have no direct connectivity. Avoiding these configurations may improve timing performance but will increase the number of ALMs used to implement the design. Medium - The Fitter allows some configurations that combine unconnected LUTs and registers to be implemented in ALM locations. The Fitter will make more usage of secondary register locations within the ALM.> High - The Fitter enables all legal and desired ALM packing configurations. In dense designs, the Fitter will automatically increase the ALM register packing effort as required to enable the design to fit.
Type
Enumeration
Values
- High
- Low
- Medium
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT <value>
Default Value
Medium
1.10.6. ANTI_TAMPER_RESPONSE_FAILED
Output to indicate an anti-tampering response failed.
Type
String
Device Support
- Intel® Agilex™
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ANTI_TAMPER_RESPONSE_FAILED <value>
Default Value
Off
1.10.7. AUTO_DELAY_CHAINS
Allows the Fitter to choose the optimal delay chain to meet tsu and tco timing requirements for all I/O elements. Turning on this option may reduce the number of tsu violations while introducing a minimal number of th violations. Turning on this option does not override delay chain settings on individual nodes.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_DELAY_CHAINS <value>
1.10.8. AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS
Allows the Fitter to choose how to optimize the delay chains for high fanout input pins. You must enable the Auto Delay Chains option for this option to work. Enabling this option may reduce the number of tsu violation, but the compile time increases significantly, as the Fitter tries to optimize the settings for all fanouts.
Type
Enumeration
Values
- Off
- On
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS <value>
Default Value
OFF
1.10.9. AUTO_GLOBAL_CLOCK
Allows the Compiler to choose the signal that feeds the most clock inputs to flipflops as a global clock signal that is made available throughout the device on the global routing paths. If you want to prevent the Compiler from automatically selecting a particular signal as global clock, set the Global Signal option to 'Off' on that signal.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- EPC1
- EPC2
- Enhanced Configuration Devices
- Flash Memory
- Intel® Stratix® 10
- Virtual JTAG TAP
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_GLOBAL_CLOCK <value> set_global_assignment -name AUTO_GLOBAL_CLOCK -entity <entity name> <value> set_instance_assignment -name AUTO_GLOBAL_CLOCK -to <to> -entity <entity name> <value>
Default Value
On
1.10.10. AUTO_GLOBAL_REGISTER_CONTROLS
Allows the Compiler to choose the signals that feed the most control signal inputs to flipflops (excluding clock signals) as global signals that are made available throughout the device on the global routing paths. Depending on the target device family, these control signals can include asynchronous clear and load, synchronous clear and load, clock enable, and preset signals.If you want to prevent the Compiler from automatically selecting a particular signal as global register control signal, set the Global Signal option to 'Off' on that signal.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- EPC1
- EPC2
- Enhanced Configuration Devices
- Flash Memory
- Intel® Stratix® 10
- Virtual JTAG TAP
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS <value> set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -entity <entity name> <value> set_instance_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS -to <to> -entity <entity name> <value>
Default Value
On
1.10.11. AUTO_RESERVE_CLKUSR_FOR_CALIBRATION
Automatically reserve CLKUSR pin for calibration purposes
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION <value>
Default Value
On
Example
set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF
1.10.12. BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
Directs the Compiler to base the Pin-Out File (.pin) and floorplan package views on the largest selected SameFrame device.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE <value>
Default Value
Off
1.10.13. BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES
Controls whether RAMs implemented in MLAB cells must have equivalent pause read capabilities as RAMs implemented in block RAM. Pausing a read is the ability to keep around the last read value when reading is disabled. Allowing differences in paused read capabilities will provide the fitter more flexibility in implementing RAMs using MLAB cells. If this option is set to 'Don't Care', the Fitter may convert RAMs to MLAB cells even if they won't have equivalent paused read capabilities to a block RAM implementation. The Fitter will also output an information message notifying the user of RAMs with different paused read capabilities. If this option is set to 'Care', the Fitter will not convert RAMs to MLAB cells unless they have the equivalent paused read capabilities to a block RAM implementation. To allow the fitter the most flexibility in deciding which RAMs are implemented using MLAB cells, set this option to 'Don't Care'.
Type
Enumeration
Values
- Care
- Dont Care
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES <value> set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES -entity <entity name> <value> set_instance_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES -to <to> -entity <entity name> <value>
Default Value
Care
1.10.14. BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS
Controls whether RAMs implemented in MLAB cells must have equivalent power up conditions as RAMs implemented in block RAM. Power up conditions occur when the device is powered up or globally reset. Allowing non-equivalent power up conditions will provide the fitter more flexibility in implementing RAMs using MLAB cells. If this option is set to 'Auto', the Fitter may convert RAMs to MLAB cells even if they won't have equivalent power up conditions to a block RAM implementation. The Fitter will also output a warning message notifying the user of RAMs with non-equivalent power up conditions. If this option is set to 'Don't Care', the same behavior as 'Auto' applies, but the warning message will instead be an information message. If this option is set to 'Care', the Fitter will not convert RAMs to MLAB cells unless they have equivalent power up conditions to a block RAM implementation. To allow the fitter the most flexibility in deciding which RAMs are implemented using MLAB cells, set this option to 'Auto' or 'Don't Care'.
Type
Enumeration
Values
- Auto
- Care
- Dont Care
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS <value> set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS -entity <entity name> <value> set_instance_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS -to <to> -entity <entity name> <value>
Default Value
Auto
1.10.15. BLOCK_RAM_TO_MLAB_CELL_CONVERSION
Controls whether the fitter is able to convert RAMs to use LAB locations when those RAMs use 'Auto' as the selected block type. If this option is changed to 'Off' then only MLAB cells in the design or RAM cells with a block type setting of 'MLAB' will use LAB locations to implement memory.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION <value> set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION -entity <entity name> <value> set_instance_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION -to <to> -entity <entity name> <value>
Default Value
On
1.10.16. CDR_BANDWIDTH_PRESET
Specifies the CDR (clock data recovery) bandwidth preset setting.
Type
Enumeration
Values
- Auto
- High
- Low
- Medium
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_instance_assignment -name CDR_BANDWIDTH_PRESET -to <to> -entity <entity name> <value>
1.10.17. CKN_CK_PAIR
Specifies the pairing of a CKn pin to a CK pin. The I/O pin of a CK CKn pair must be placed on a differential pin pair. This option is ignored if is assigned to anything other than an I/O pad, input buffer, or output buffer.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name CKN_CK_PAIR -from <from> -to <to> -entity <entity name> <value>
1.10.18. CLOCK_REGION
Specifies the placement of the clock region of a global signal for floorplanning reasons. For example, a Clock Region assignment can be used to ensure that a certain area of the device has access to a global signal, throughout all future design iterations. A Clock Region assignment can also be used in cases of congestion involving global signal resources. By specifying a smaller clock region size, the assignment prevents a signal using spine clock and other clock routing resources in the excluded sectors that may be encountering clock-related congestion.\n\nFor devices up to and including Arria 10, this assignment takes as its value the names of those Global, Regional, Periphery or Spine Clock regions. These region names are visible in Chip Planner by enabling the appropriate Clock Region layer in the Layers Settings dialog box. Examples of valid values include \"Regional Clock Region 1\" or \"Periphery Clock Region 1\". When constraining a global signal to a smaller than normal region, for example, to avoid clock congestion, you may specify a clock region of a different type than the global resources being used. For example, a signal with a Global Signal assignment of \"Global Clock\", but a Clock Region assignment of \"Regional Clock Region 0\", constrains the clock to use global network routing resources, but only to the region covered by Regional Clock Region 0. To provide a finer level of control, you can also list multiple smaller clock regions, separated by commas. For example: \"Periphery Clock Region 0, Periphery Clock Region 1\" constrains a signal to only the area reachable by those two periphery clock networks.\n\nFor Stratix 10 devices, clock regions can be constrained to a rectangle whose dimensions are defined by the sector grid, as seen in the Clock Sector Region layer of the Chip Planner. This assignment specifies the bottom left and top right coordinates of the rectangle in the format \"SX# SY# SX# SY#\". For example, \"SX0 SY0 SX1 SY1\" constrains the clock to a 2x2 region, from the bottom left of sector (0,0) to the top right of sector (1,1). For a constraint spanning only one sector, it is sufficient to specify the location of that sector, for example \"SX1 SY1\". The bounding rectangle can also be specified by the bottom left and top right corners in chip coordinates, for example, \"X37 Y181 X273 Y324\". However, such a constraint should be sector aligned (using sector coordinates guarantees this) or the Fitter automatically snaps to the smallest sector aligned rectangle that still encompasses the original assignment. The \"SX# SY# SX# SY#\"|\"X# Y# X# Y#\" strings are case-insensitive.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports wildcards.
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name CLOCK_REGION -to <to> -entity <entity name> <value> set_instance_assignment -name CLOCK_REGION -from <from> -to <to> -entity <entity name> <value>
1.10.19. CLOCK_SPINE
Specifies the Spine Clock (SCLK) wire index to use for the targeted global signal. Each clock sector contains 32 SCLK resources, and an allocated global clock tree will use the same SCLK index in each driven clock sector. This is an advanced assignment that can potentially be useful to control global signal routing decisions in cases of global resource congestion. When used, this assignment should typically be paired with a Clock Region assignment to ensure the driven clock sectors are also constrained.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
INTEGER_RANGE
0, 31
Notes
This assignment supports wildcards.
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name CLOCK_SPINE -to <to> -entity <entity name> <value> set_instance_assignment -name CLOCK_SPINE -from <from> -to <to> -entity <entity name> <value>
1.10.20. CONFIGURATION_VCCIO_LEVEL
Specifies the VCCIO voltage of the configuration pins for the current configuration scheme on the target device.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL <value>
Default Value
Auto
Example
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V
See Also
FORCE_CONFIGURATION_VCCIO
1.10.21. CONVERT_PR_WARNINGS_TO_ERRORS
Turns PR warnings into errors when enabled.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
Syntax
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS <value>
Default Value
Off
Example
set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS ON
1.10.22. CRC_ERROR_OPEN_DRAIN
Specify open drain on the CRC Error pin should be enabled or not
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name CRC_ERROR_OPEN_DRAIN <value>
Example
set_global_assignment -name crc_error_open_drain on set_global_assignment -name crc_error_open_drain off
See Also
CRC_ERROR_CHECKINGERROR_CHECK_FREQUENCY_DIVISOR
1.10.23. CURRENT_STRENGTH_NEW
Sets the drive strength of a pin. Specify a number (in mA), MIN, or MAX for output or bidirectional pins that support programmable drive strength. Please refer to the family data sheet for which drive strengths are allowed for each I/O standard. This option is ignored if it is applied to anything other than an output or bidirectional pin.
Old Name
CURRENT_STRENGTH
Type
String
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name CURRENT_STRENGTH_NEW -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to output_pin
See Also
IO_STANDARDOUTPUT_TERMINATION
1.10.24. CVP_CONFDONE_OPEN_DRAIN
Specify open drain on the CvP_CONFDONE pin should be enabled or not
Old Name
CVPCIE_CONFDONE_OPEN_DRAIN
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN <value>
Default Value
On
Example
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN on set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN off
See Also
ENABLE_CVP_CONFDONE
1.10.25. CVP_MODE
Specifies the configuration mode for Configuration via Protocol (CvP). In Core initialization mode, the periphery image is stored in an external configuration device and is loaded into the FPGA through the conventional configuration scheme. The core image is stored in a host memory and is loaded into the FPGA through the PCIe link. In core update mode, the FPGA device is initialized after initial system power up by loading the full configuration image from the external local configuration device to the FPGA. User can use the PCIe link to perform one or more FPGA core image update through this mode. In the Off mode, CvP is turned off.
Old Name
CVPCIE_MODE
Type
Enumeration
Values
- Core initialization
- Core initialization and update
- Core update
- Off
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name CVP_MODE <value>
Default Value
Off
Example
set_global_assignment -name CVP_MODE "Power up and subsequent core configuration"
1.10.26. DEVICE
Specifies the device to use.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name DEVICE <value>
1.10.27. DEVICE_INITIALIZATION_CLOCK
In 20nm device families, this specifies the clock source for device initialization (the duration between CONF_DONE signal went high and before INIT_DONE signal goes high). In 14nm or later device families, this specifies the clock source used to run the PLL which produces the clock used by the device configuration and monitoring system.
Type
Enumeration
Values
- INIT_CLKUSR
- INIT_DCLK
- INIT_INTOSC
- OSC_CLK_1_100MHZ
- OSC_CLK_1_125MHZ
- OSC_CLK_1_25MHZ
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Diamond Mesa
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK <value>
Default Value
INIT_INTOSC
Example
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK "CLKUSR"
See Also
USER_START_UP_CLOCK
1.10.28. DEVICE_IO_STANDARD_ALL
Specifies the default I/O standard to be used for pins on the target device.
Old Name
STRATIX_DEVICE_IO_STANDARD, YEAGER_DEVICE_IO_STANDARD
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name DEVICE_IO_STANDARD_ALL <value>
Example
set_global_assignment -name DEVICE_IO_STANDARD_ALL "1.2 V"
See Also
IO_STANDARD
1.10.29. DEVICE_MIGRATION_LIST
Shows the selected migration devices for the current device.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name DEVICE_MIGRATION_LIST <value>
1.10.30. DEVICE_TECHNOLOGY_MIGRATION_LIST
Shows the selected technology migration devices for the current device.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
The value of this assignment is case sensitive.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name DEVICE_TECHNOLOGY_MIGRATION_LIST <value>
1.10.31. DQ_GROUP
Specifies the grouping from a DQS pin to its associated DQ pins and the width (4, 9, 18, or 36) of the group. Setting this option allows the Fitter to view the pins as a DQS/DQ pin group. I/O pins of a DQ pin group must be placed in the DQ pin locations of a single DQS group. This option is ignored if is assigned to anything other than an I/O pad, input buffer, or output buffer.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name DQ_GROUP -from <from> -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name DQ_GROUP 9 -from mem_dqs[0] -to mem_dq[0..7]
See Also
DQSB_DQS_PAIRMEMORY_INTERFACE_DATA_PIN_GROUP
1.10.32. DSP_REGISTER_PACKING
Controls how aggressively the fitter optimizes DSP performance by automatically packing registers into the internal registers of the specified DSP blocks. When the 'Balanced' option is enabled, the Fitter will pack registers into the specified DSP blocks that should improve timing. When 'Always' is enabled, the fitter will aggressively try to pack registers into the specified DSP blocks unless prevented by user constraints or other legality restrictions. When 'Disable' is selected, registers will not be packed into the specified DSP blocks.
Type
Enumeration
Values
- Always
- Balanced
- Disable
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name DSP_REGISTER_PACKING -to <to> -entity <entity name> <value>
1.10.33. DUPLICATE_ATOM
Directs the Compiler to duplicate the source node, and uses the new duplicate node to fan out to the destination node; the original source node no longer fans out to the destination node. Use the 'Value' field to specify the name of the duplicate node.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
This assignment supports Fitter wildcards.
The value of this assignment must be a node name.
Syntax
set_instance_assignment -name DUPLICATE_ATOM -from <from> -to <to> -entity <entity name> <value>
1.10.34. DUPLICATE_REGISTER
Directs the Compiler to create a number of duplicates of a register, including the original, and redistribute the fanouts of the original register among the duplicates.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
INTEGER_RANGE
1, 1000000
Notes
The value of this assignment is case sensitive.
This assignment is copied to any duplicated nodes.
This assignment supports Fitter wildcards.
The value of this assignment must be a node name.
Syntax
set_instance_assignment -name DUPLICATE_REGISTER -to <to> -entity <entity name> <value>
1.10.35. ENABLE_BUS_HOLD_CIRCUITRY
Enables bus-hold circuitry during device operation. If this option is turned on, a pin will retain its last logic level when it is not driven, and will not go to a high impedance logic level. The 'Enable Bus-Hold Circuitry' option should not be used at the same time as the 'Weak Pull-Up Resistor' option. This option is ignored if it is applied to anything other than a pin.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY <value> set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY -entity <entity name> <value> set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to pin
1.10.36. ENABLE_CRC_ERROR_PIN
Specifies error detection CRC and CRC_ERROR pin usage for the selected device. If error detection CRC is turned on, the device checks the validity of the programming data in the device. Any changes in the data while the device is in operation generates an error.
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name ENABLE_CRC_ERROR_PIN <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_CRC_ERROR_PIN ON
See Also
ERROR_CHECK_FREQUENCY_DIVISORCRC_ERROR_OPEN_DRAIN
1.10.37. ENABLE_CVP_CONFDONE
Enable the CvP_CONFDONE pin, which indicates that the device finished core programming in Configuration via Protocol mode. If this option is turned off, the CvP_CONFDONE pin is disabled when the device operates in user mode and is available as a user I/O pin.
Old Name
ENABLE_CVPCIE_CONFDONE
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name ENABLE_CVP_CONFDONE <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_CVP_CONFDONE ON
See Also
CVP_CONFDONE_OPEN_DRAIN
1.10.38. ENABLE_DEVICE_WIDE_OE
Enables the DEV_OE pin when the device is in user mode. If this option is turned on, all outputs on the chip operate normally. When the pin is disabled, all outputs are tri-stated. If this option is turned off, the DEV_OE pin is disabled when the device operates in user mode and is available as a user I/O pin.
Old Name
ENABLE_CHIP_WIDE_OE
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name ENABLE_DEVICE_WIDE_OE <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_DEVICE_WIDE_OE ON
1.10.39. ENABLE_DEVICE_WIDE_RESET
Enables the DEV_CLRn pin, which allows all registers of the device to be reset by an external source. If this option is turned off, the DEV_CLRn pin is disabled when the device operates in user mode and is available as a user I/O pin.
Old Name
ENABLE_CHIP_WIDE_RESET
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
1.10.40. ENABLE_ED_CRC_CHECK
Enable the error detection check. The status is SEU_ERROR output SDM_IO. If error detection CRC is turned on, the device checks the validity of the programming data in the device. Any changes in the data while the device is in operation generates an error.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name ENABLE_ED_CRC_CHECK <value>
Example
set_global_assignment -name ENABLE_ED_CRC_CHECK ON
1.10.41. ENABLE_INIT_DONE_OUTPUT
Enables the INIT_DONE pin, which allows you to externally monitor when initialization is completed and the device is in user mode. If this option is turned off, the INIT_DONE pin is disabled when the device operates in user mode and is available as a user I/O pin.
Old Name
Enable INIT_DONE Output
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT OFF
See Also
INIT_DONE_OPEN_DRAIN
1.10.42. ENABLE_INTERMEDIATE_SNAPSHOTS
Turning on this option will generate all intermediate fitter snapshots (planned, placed, routed, retimed) during compilation for design analysis. The option is off by default. If 'Run Fast Forward Timing Closure Recommendations during compilation' is on, then the option is forced on.
Type
Boolean
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_INTERMEDIATE_SNAPSHOTS <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_INTERMEDIATE_SNAPSHOTS on
1.10.43. ENABLE_NCEO_OUTPUT
Enables the nCEO pin. This pin should be connected to the nCE of the succeeding device when multiple devices are being programmed. If this option is turned off, the nCEO pin is disabled when the device operates in user mode and is available as a user I/O pin.
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name ENABLE_NCEO_OUTPUT <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_NCEO_OUTPUT OFF
1.10.44. ENABLE_PR_PINS
Allows you to enable the PR_REQUEST, PR_READY, PR_ERROR, PR_DONE, DCLK, and DATA[31..0] pins. These pins are needed to support partial reconfiguration (PR) with an external host. An external host uses the PR_REQUEST pin to request partial reconfiguration, the PR_READY pin to determine if the device is ready to receive programming data, the PR_ERROR pin to externally monitor programming errors, and the PR_DONE pin to indicate the device finished programming. If this option is turned off, these pins are not available as PR pins when the device operates in user mode and the dual-purpose programming pins are available as user I/O pins.
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name ENABLE_PR_PINS <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_PR_PINS ON
See Also
PR_PINS_OPEN_DRAIN
1.10.45. ENABLE_TIME_BORROWING_OPTIMIZATION
Enables optimal time borrowing algorithm. Turned on automatically for performance optimization mode.
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_TIME_BORROWING_OPTIMIZATION <value>
Default Value
Off
1.10.46. ENABLE_UNUSED_RX_CLOCK_WORKAROUND
Enable workaround for unused RX clock to preserve its performance over time
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND <value> set_instance_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND -to <to> -entity <entity name> <value>
Default Value
Off
Example
set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND ON set_instance_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND ON -to AW34
1.10.47. ERROR_CHECK_FREQUENCY_DIVISOR
Specifies the divide value of the internal clock, which determines the frequency of the CRC. The divide value must be a power of two. Refer to the device handbook to find the frequency of the internal clock for the selected device.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR <value>
Example
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 16
See Also
CRC_ERROR_CHECKING
1.10.48. EXCLUSIVE_IO_GROUP
Assigns an exclusive group number for the specified I/O. I/Os with the different exclusive group number cannot share the same bank.
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name EXCLUSIVE_IO_GROUP -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name "EXCLUSIVE_IO_GROUP" -to pin
1.10.49. FINAL_PLACEMENT_OPTIMIZATION
Specifies whether the Fitter performs final placement optimizations. Performing final placement optimizations may improve timing and routability, but may also require longer compilation time. The default setting of Automatically can be used with the Auto Fit Fitter Effort Level (also the default) to let the fitter decide whether these optimizations should run based on the routability and timing requirements of the design.
Type
Enumeration
Values
- Always
- Automatically
- Never
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION <value>
Default Value
Automatically
1.10.50. FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION
Specifies whether the Fitter aggressively optimizes for routability. Performing aggressive routability optimizations may decrease design speed, but may also reduce routing wire usage and routing time. The default setting of Automatically lets the fitter decide whether to perform these optimizations based on the routability and timing requirements of the design.
Type
Enumeration
Values
- Always
- Automatically
- Never
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION <value>
Default Value
Automatically
1.10.51. FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN
Specifies the amount of worst-case slack margin the fitter should try to maintain when the Fitter Effort option is set to 'Auto Fit'. If the design is likely to have at least this much slack on every path, the fitter will reduce optimization effort to reduce compilation time. Otherwise, its behavior will be the same as it is with the 'Standard Fit' Fitter Effort setting.
Type
Time
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN <value>
Default Value
0ns
1.10.52. FITTER_EARLY_RETIMING
Allows the Compiler to run global retiming early in the fitter.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name FITTER_EARLY_RETIMING <value>
Example
set_global_assignment -name FITTER_EARLY_RETIMING on
1.10.53. FITTER_EFFORT
Controls the fitter's trade-off between performance and compilation speed. Auto Fit adjusts the fitter optimization effort to minimize compilation time, while still achieving the design timing requirements. The Auto Fit Effort Desired Slack Margin option can be used to request that Auto Fit apply sufficient optimization effort to achieve additional timing margin. Standard Fit will use maximum effort regardless of the design's requirements, leading to higher compilation time and more margin on easier designs. For difficult designs, Auto Fit and Standard Fit will both use maximum effort. Fast Fit will decrease optimization effort to reduce compilation time, which may degrade design performance.
Type
Enumeration
Values
- Auto Fit
- Fast Fit
- Standard Fit
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name FITTER_EFFORT <value>
Default Value
Auto Fit
1.10.54. FLEX10K_MAX_PERIPHERAL_OE
Sets the limit on the number of peripheral OE buses that can be used.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name FLEX10K_MAX_PERIPHERAL_OE <value>
1.10.55. FORCE_CONFIGURATION_VCCIO
Forces the VCCIO voltage of the configuration pins to be the same as the configuration device I/O voltage.
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name FORCE_CONFIGURATION_VCCIO <value>
Default Value
Off
Example
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
See Also
CONFIGURATION_VCCIO_LEVEL
1.10.56. GLOBAL_PLACEMENT_EFFORT
Controls how much effort the fitter spends during advanced physical placement optimization. High, Optimized and Maxmimum effort settings spend additional compile time to further optimization the placement solution. The setting Optimize for High Utilization will perform targeted optimization to reduce core logic utilization, which may help address placement or routing issues in high utilization designs.
Type
Enumeration
Values
- High Effort
- Maximum Effort
- Normal
- Optimized Effort
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name GLOBAL_PLACEMENT_EFFORT <value>
Default Value
Normal
1.10.57. GLOBAL_SIGNAL
Specifies whether the signal should be routed using global routing paths. Global signals can be both pin- and logic-driven, and can be any signal in the design. In Arria 10 and Cyclone 10 GX devices, setting this option for a pin or a single-output logic function signal is equivalent to feeding the signal through a GLOBAL buffer of the specified type. In all other families, the buffer type is not specified. Rather, a setting of \"On\" specifies that the signal must use global routing to route to all destinations (or specified subset). Alternatively, a setting of \"On - Auto Promote Fanout\" on the source specifies that global routing must be used for all destinations, except those that the fitter would normally not consider automatically. In all families, turning this option off for a particular signal will prevent any of the Auto Global options from using the signal as an automatic global signal.
Type
Enumeration
Values
- Dual-Fast Regional Clock
- Dual-Regional Clock
- Fast Regional Clock
- Global Clock
- Large Periphery Clock
- Off
- On
- On - Auto Promote Fanout
- Periphery Clock
- Regional Clock
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- EPC1
- EPC2
- Enhanced Configuration Devices
- Flash Memory
- Intel® Stratix® 10
- Virtual JTAG TAP
Notes
This assignment supports wildcards.
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name GLOBAL_SIGNAL -to <to> -entity <entity name> <value> set_instance_assignment -name GLOBAL_SIGNAL -from <from> -to <to> -entity <entity name> <value>
1.10.58. GNDIO_CURRENT_1PT8V
For user to override GNDIO current of 1.8-V io standard. Original current is 2mA
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_1PT8V <value>
1.10.59. GNDIO_CURRENT_2PT5V
For user to override GNDIO current of 2.5-V io standard. Original current is 2mA
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_2PT5V <value>
1.10.60. GNDIO_CURRENT_GTL
For user to override GNDIO current of GTL. Not yet supported in MAX7000.
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_GTL <value>
1.10.61. GNDIO_CURRENT_GTL_PLUS
For user to override GNDIO current of GTL+. Original current is 50mA
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_GTL_PLUS <value>
1.10.62. GNDIO_CURRENT_LVCMOS
For user to override GNDIO current of LVCMOS. Original current is 2mA
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_LVCMOS <value>
1.10.63. GNDIO_CURRENT_LVTTL
For user to override GNDIO current of LVTTL. Original current is 4mA
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_LVTTL <value>
1.10.64. GNDIO_CURRENT_PCI
For user to override GNDIO current of PCI. Original current is 4mA
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_PCI <value>
1.10.65. GNDIO_CURRENT_SSTL2_CLASS1
For user to override GNDIO current of SSTL2_CLASS1. Original current is 14mA
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_SSTL2_CLASS1 <value>
1.10.66. GNDIO_CURRENT_SSTL2_CLASS2
For user to override GNDIO current of SSTL2_CLASS2. Original current is 21mA
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_SSTL2_CLASS2 <value>
1.10.67. GNDIO_CURRENT_SSTL3_CLASS1
For user to override GNDIO current of SSTL3_CLASS1. Original current is 18mA
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_SSTL3_CLASS1 <value>
1.10.68. GNDIO_CURRENT_SSTL3_CLASS2
For user to override GNDIO current of SSTL3_CLASS2. Original current is 25mA
Type
Integer
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Notes
None
Syntax
set_global_assignment -name GNDIO_CURRENT_SSTL3_CLASS2 <value>
1.10.69. GXB_0PPM_CORECLK
Specifies core clocks that have zero PPM difference. Follow the Intel High Speed I/O Applications Technical Support recommendations when using this assignment.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name GXB_0PPM_CORECLK -to <to> -entity <entity name> <value>
1.10.70. HPS_COLD_RESET_PIN_MODE
Use the reset pin as input-only or open-drain bidirectional.
Type
Enumeration
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name HPS_COLD_RESET_PIN_MODE <value>
Default Value
BIDIRECTIONAL
1.10.71. HPS_WARM_RESET_PIN_MODE
Use the reset pin as input-only or open-drain bidirectional.
Type
Enumeration
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name HPS_WARM_RESET_PIN_MODE <value>
Default Value
BIDIRECTIONAL
1.10.72. HSSI_PARAMETER
A logic option that allows you to set the parameter settings of the transmitter/receiver channel.
Type
String
Device Support
- Intel® Agilex™
- Intel® Stratix® 10
Notes
The value of this assignment is case sensitive.
Syntax
set_instance_assignment -name HSSI_PARAMETER -to <to> -entity <entity name> <value>
1.10.73. IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS
Ignore the power supply of HSSI column when preserving unused RX/TX channels. By default, any unused RX/TX channels in each HSSI column will be preserved
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment is included in the Fitter report.
Syntax
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS <value>
Default Value
On
Example
set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS OFF
1.10.74. INIT_DONE_OPEN_DRAIN
Specify open drain on the INIT_DONE pin should be enabled or not
Type
Boolean
Device Support
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
Notes
None
Syntax
set_global_assignment -name INIT_DONE_OPEN_DRAIN <value>
Default Value
On
Example
set_global_assignment -name init_done_open_drain on set_global_assignment -name init_done_open_drain off
See Also
ENABLE_INIT_DONE_OUTPUT
1.10.75. INPUT_DELAY_CHAIN
Specifies the propagation delay for Input Delay Chain. This is an advanced option that should be used only after you have compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family. This option is ignored if it is applied to anything other than an input or bidirectional pin.
Old Name
INPUT_DELAY
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
INTEGER_RANGE
0, 63
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name INPUT_DELAY_CHAIN -to <to> -entity <entity name> <value> set_instance_assignment -name INPUT_DELAY_CHAIN -from <from> -to <to> -entity <entity name> <value>
1.10.76. INPUT_TERMINATION
Allows the Compiler to configure the on-chip termination (OCT) and impedance matching for an I/O pin. OCT helps to prevent signal reflections and maintain signal integrity. This option is ignored if it is applied to anything other than an I/O pad, input buffer, or output buffer.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name INPUT_TERMINATION -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to pin_name
See Also
IO_STANDARDOCT_CONTROL_BLOCKOUTPUT_OCT_VALUE
1.10.77. INTERNAL_SCRUBBING
Specifies internal scrubbing usage for the selected device. If internal scrubbing is turned on, the device corrects single error or double adjacent error within the core configuration memory while the device is still running.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
None
Syntax
set_global_assignment -name INTERNAL_SCRUBBING <value>
Default Value
Off
Example
set_global_assignment -name INTERNAL_SCRUBBING ON
1.10.78. IO_12_LANE_INPUT_DATA_DELAY_CHAIN
Specifies the propagation delay for IO_12_LANE Input Data Delay Chain. This is an advanced option that should be used only after you have compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family. This option is ignored if it is applied to anything other than an input or bidirectional pin.
Old Name
IO_12_LANE_INPUT_DATA_DELAY
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name IO_12_LANE_INPUT_DATA_DELAY_CHAIN -to <to> -entity <entity name> <value> set_instance_assignment -name IO_12_LANE_INPUT_DATA_DELAY_CHAIN -from <from> -to <to> -entity <entity name> <value>
1.10.79. IO_12_LANE_INPUT_STROBE_DELAY_CHAIN
Specifies the propagation delay for IO_12_LANE Input Strobe Delay Chain. This is an advanced option that should be used only after you have compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family. This option is ignored if it is applied to anything other than an input or bidirectional pin.
Old Name
IO_12_LANE_INPUT_STROBE_DELAY
Type
Integer
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name IO_12_LANE_INPUT_STROBE_DELAY_CHAIN -to <to> -entity <entity name> <value> set_instance_assignment -name IO_12_LANE_INPUT_STROBE_DELAY_CHAIN -from <from> -to <to> -entity <entity name> <value>
1.10.80. IO_MAXIMUM_TOGGLE_RATE
Specifies the toggle rate of this node. You can specify the desired frequency setting. This option is ignored if it is applied to anything other than pins. This option can be used to direct the Fitter in its toggle-rate checking while allowing a single-ended pin to be placed closer to a differential pin. This assignment is used to analyze signal integrity under worst case conditions (highest possible toggle rate). A different assignment, Power Toggle Rate, is used to specify the expected time-averaged toggle rate rather than worst-case toggle rate, and is used by the Power Analyzer to estimate time-averaged power consumption. Use the Synchronizer Toggle Rate if you want to configure the data rates used for Metastability Reporting in the Timing Analyzer.
Old Name
TOGGLE RATE, TOGGLE_RATE
Type
Frequency
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
Syntax
set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE -to <to> -entity <entity name> <value>
1.10.81. IO_PARTITION_PLACEMENT
Specifies whether the I/O should be put in a preserved partition to preserve I/O settings, or if it should be put in the root. Typically I/Os should be placed in the root to maximize the flexibility for the design. However, for some IPs it is desireable to preserve I/O settings such as I/O Standards, in which case it would need to go in the partition.
Type
Enumeration
Values
- PARTITION
- ROOT
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Stratix® 10
Notes
None
Syntax
set_instance_assignment -name IO_PARTITION_PLACEMENT -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name IO_PARTITION_PLACEMENT PARTITION -to pin
1.10.82. IO_STANDARD
Specifies the I/O standard of a pin. Different device families support different I/O standards, and restrictions apply to placing pins with different I/O standards together. For detailed information, refer to the device family data sheet and to Application Note 117 (Using Selectable I/O Standards in Intel FPGA Devices). This option is ignored if it is applied to anything other than a pin or a top-level design entity.
Type
String
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
This assignment supports synthesis wildcards.
Syntax
set_instance_assignment -name IO_STANDARD -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name IO_STANDARD LVDS -to pin
See Also
DEVICE_IO_STANDARD_ALLCURRENT_STRENGTH_NEWSLEW_RATEOUTPUT_TERMINATIONINPUT_TERMINATIONPROGRAMMABLE_PREEMPHASISPROGRAMMABLE_VOD
1.10.83. LVDS_DIRECT_LOOPBACK_MODE
Enable the LVDS Direct Loop Mode on a True Differential output pin. This assignment should only apply from an input pin to an output pin and both of them should have True Differential I/O standard. When this feature is enabled, data coming in from the adjacent RX pair gets looped back to the TX pair. This feature can be used to verify the Tx and Rx buffer by checking the data transmit and received. This option is ignored if it is applied to anything other than a pin or a top-level design entity.
Type
Boolean
Device Support
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX
- Intel® Stratix® 10
Notes
This assignment supports Fitter wildcards.
This assignment is included in the Fitter report.
Syntax
set_instance_assignment -name LVDS_DIRECT_LOOPBACK_MODE -from <from> -to <to> -entity <entity name> <value>
Example
set_instance_assignment -name LVDS_DIRECT_LOOPBACK_MODE ON -from true_diff_in_pin_p -to true_diff_out_pin_p
See Also
IO_STANDARD
1.10.84. MACRO_HEAD
Specifies the head block of a macro.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_instance_assignment -name MACRO_HEAD -to <to> -entity <entity name> <value>
1.10.85. MACRO_MEMBER
Specifies a block to be placed with respect to its macro head.
Type
String
Device Support
- This setting can be used in projects targeting any Intel FPGA device family.
Syntax
set_global_assignment -name MACRO_MEMBER -entity <entity name> <value> set_instance_assignment -name MACRO_MEMBER -to <to> -entity <entity name> <value> set_instance_assignment -name MACRO_MEMBER -from <from> -to <to> -entity <entity name> <value>
1.10.86. MATCH_PLL_COMPENSATION_CLOCK
Allows you to specify a PLL output clock feeding a clock network as a compensation target for a PLL in NORMAL or SOURCE_SYNCHRONOUS mode. This configures the PLL to match its feedback path to the target's clock network. This option is ignored if it is applied to anything other than a PLL output clock.
Type
Boolean