1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel Stratix 10 FPGA IP User Guide

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UG-20071 | 2019.05.10

About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core

The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core for Intel^® Stratix^® 10 devices (L- and H-tiles) implements the Ethernet protocol as defined in the IEEE 802.3 2005 Standard. It consists of a physical coding sublayer (PCS) function and an embedded physical media attachment (PMA). You can dynamically switch the PHY operating speed.

Note: Intel^® FPGAs implement and support the required Media Access Control (MAC), PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T PHY standard devices. You are required to use an external PHY device to drive any copper media.

Features

Table 1. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP Core Features
Feature	Description
Operating speeds	10M, 100M, 1G, 2.5G, 5G, and 10G.
MAC-side interface	16-bit GMII for 10M/100M/1G/2.5G (MGBASE-T).
	32-bit XGMII for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T).
	64-bit XGMII for 10G (MGBASE-T).
Network-side interface	1.25 Gbps for 1G (MGBASE-T) and 10M/100M/1G (SGMII).
	3.125 Gbps for 2.5G (MGBASE-T).
	10.3125 Gbps for 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T) and 10G (MGBASE-T).
Avalon^® Memory-Mapped ( Avalon^® -MM) interface	Provides access to the configuration registers of the PHY.
Physical Coding Sublayer (PCS) function	1000BASE-X for 1G and 2.5G.
	10GBASE-R for 10G.
	USXGMII PCS for 10M/100M/1G/2.5G/5G/10G (USXGMII).
	SGMII (10M/100M/1G) for 1G/2.5 and 1G/2.5/10G (MGBASE-T).
Auto-negotiation	Implements IEEE 802.3 clause 37. Supported in 1GbE only. USXGMII Auto-negotiation supported in the 10M/100M/1G/2.5G/5G/10G (USXGMII/NBASE-T) configuration. SGMII Auto-negotiation supported in the 10M/100M/1G (SGMII) configuration.
IEEE 1588v2	Provides the required latency to the MAC if the MAC enables the IEEE 1588v2 feature. Supported: 2.5G 1G/2.5G 1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/5G/10G (USXGMII) Note: For the 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration, the provided latency is applicable only for 100M, 1G, 2.5G, 5G, and 10G modes. Not Supported: 10M/100M/1G/2.5G 10M/100M/1G/2.5G/10G (MGBASE-T)
Sync-E	Provides the clock for Sync-E implementation.

Device Family Support

Table 2. Intel^® FPGA IP Core Device Support Levels
Device Support Level	Definition
Advance	The IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
Preliminary	The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
Final	The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Table 3. Device Family Support for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP Core
Device Family	Support Level
Intel^® Stratix^® 10	Advance

Device Speed Grade Support

Table 4. Slowest Supported Device Speed Grades
Speed Mode	Supported Speed Grade
Speed Mode	With 1588 Feature	Without 1588 Feature
2.5G	E2, I2	E3, I3
1G/2.5G	E2, I2	E3, I3
10M/100M/1G/2.5G	-	E3, I3
1G/2.5G/10G (MGBASE-T)	E2, I2	E3, I3
10M/100M/1G/2.5G/10G (MGBASE-T)	-	E3, I3
10M/100M/1G/2.5G/5G/10G (USXGMII)	E2, I2	E3, I3

Resource Utilization

The following estimates are obtained by compiling the PHY IP core for Intel^® Stratix^® 10 devices using Intel^® Quartus^® Prime software.

Table 5. Resource Utilization
Speed	ALMs	ALUTs	Logic Registers	Memory Block (M20K)
1G/2.5G	790	940	1570	2
1G/2.5G with IEEE 1588v2 enabled	1770	2390	3030	2
10M/100M/1G/2.5G	810	980	1610	2
10M/100M/1G/2.5G/10G (MGBASE-T)	1440	1790	2640	6
1G/2.5G/10G (MGBASE-T)	1390	1740	2640	6
1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 enabled	3830	4630	5960	6
10M/100M/1G/2.5G/5G/10G (USXGMII)	920	1120	1830	3
10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588v2 enabled	1760	2540	3510	4

Release Information

Table 6. Release Information
Item	Description
Version	Intel^® Quartus^® Prime Pro Edition 19.1
Release Date	2019.04.01
Ordering Codes	IP-10GMRPHY

Getting Started

The following section explains how to install, parameterize, simulate, and initialize the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core.

Installing and Licensing Intel FPGA IP Cores

The Intel^® Quartus^® Prime software installation includes the Intel^® FPGA IP library. This library provides many useful IP cores for your production use without the need for an additional license. Some Intel^® FPGA IP cores require purchase of a separate license for production use. The Intel^® FPGA IP Evaluation Mode allows you to evaluate these licensed Intel^® FPGA IP cores in simulation and hardware, before deciding to purchase a full production IP core license. You only need to purchase a full production license for licensed Intel^® IP cores after you complete hardware testing and are ready to use the IP in production.

The Intel^® Quartus^® Prime software installs IP cores in the following locations by default:

Figure 1. IP Core Installation Path

Table 7. IP Core Installation Locations
Location	Software	Platform
`<drive>`:\intelFPGA_pro\quartus\ip\altera	Intel^® Quartus^® Prime Pro Edition	Windows*
`<home directory>`:/intelFPGA_pro/quartus/ip/altera	Intel^® Quartus^® Prime Pro Edition	Linux*

Intel FPGA IP Evaluation Mode

The free Intel^® FPGA IP Evaluation Mode allows you to evaluate licensed Intel^® FPGA IP cores in simulation and hardware before purchase. Intel^® FPGA IP Evaluation Mode supports the following evaluations without additional license:

Simulate the behavior of a licensed Intel^® FPGA IP core in your system.
Verify the functionality, size, and speed of the IP core quickly and easily.
Generate time-limited device programming files for designs that include IP cores.
Program a device with your IP core and verify your design in hardware.

Intel^® FPGA IP Evaluation Mode supports the following operation modes:

Tethered—Allows running the design containing the licensed Intel^® FPGA IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial joint test action group (JTAG) cable connected between the JTAG port on your board and the host computer, which is running the Intel^® Quartus^® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Intel^® Quartus^® Prime software, and requires no Intel^® Quartus^® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IP cores in the design support tethered mode, the evaluation time runs until any IP core evaluation expires. If all of the IP cores support unlimited evaluation time, the device does not time-out.
Untethered—Allows running the design containing the licensed IP for a limited time. The IP core reverts to untethered mode if the device disconnects from the host computer running the Intel^® Quartus^® Prime software. The IP core also reverts to untethered mode if any other licensed IP core in the design does not support tethered mode.

When the evaluation time expires for any licensed Intel^® FPGA IP in the design, the design stops functioning. All IP cores that use the Intel^® FPGA IP Evaluation Mode time out simultaneously when any IP core in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP core for production, purchase a full production license for the IP core.

You must purchase the license and generate a full production license key before you can generate an unrestricted device programming file. During Intel^® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit.

Figure 2. Intel^® FPGA IP Evaluation Mode Flow

Note: Refer to each IP core's user guide for parameterization steps and implementation details.

Intel^® licenses IP cores on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receive updates, bug fixes, and technical support beyond the first year. You must purchase a full production license for Intel^® FPGA IP cores that require a production license, before generating programming files that you may use for an unlimited time. During Intel^® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit. To obtain your production license keys, visit the Self-Service Licensing Center.

The Intel^® FPGA Software License Agreements govern the installation and use of licensed IP cores, the Intel^® Quartus^® Prime design software, and all unlicensed IP cores.

Specifying the IP Core Parameters and Options

The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP parameter editor allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Intel^® Quartus^® Prime Pro Edition software:

In the Intel^® Quartus^® Prime Pro Edition, click File > New Project Wizard to create a new Intel^® Quartus^® Prime project, or File > Open Project to open an existing Intel^® Quartus^® Prime project. The wizard prompts you to specify a device.
In the IP Catalog (Tools > IP Catalog), locate and double-click 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core to customize. The New IP Variant window appears.
Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
Click Create. The parameter editor appears.
Specify the parameters for your IP core variation in the parameter editor. Refer to Parameter Settings for information about specific IP core parameters.
Optionally, to generate a MAC+PHY simulation testbench or compilation and hardware design example, follow the instructions in the Low Latency Ethernet 10G MAC Intel^® Stratix^® 10 FPGA IP Design Example User Guide.
Click Generate HDL. The Generation dialog box appears.
Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
Click Finish. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.

Generated File Structure

The Intel^® Quartus^® Prime Pro Edition software generates the following IP core output file structure.

Figure 3. IP Core Generated Files

Table 8. IP Core Generated Files
File Name	Description
<`your_ip`>.ip	The Platform Designer system or top-level IP variation file. <`your_ip`> is the name that you give your IP variation.
<`your_ip`>.cmp	The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files. This IP core does not support VHDL. However, the Intel^® Quartus^® Prime Pro Edition software generates this file.
<`your_ip`>.html	A report that contains connection information, a memory map showing the address of each slave with respect to each master to which it is connected, and parameter assignments.
<`your_ip`>_generation.rpt	IP or Platform Designer generation log file. A summary of the messages during IP generation.
<`your_ip`>.qgsimc	Lists simulation parameters to support incremental regeneration.
<`your_ip`>.qgsynthc	Lists synthesis parameters to support incremental regeneration.
<`your_ip`>.qip	Contains all the required information about the IP component to integrate and compile the IP component in the Intel^® Quartus^® Prime software.
<`your_ip`>.sopcinfo	Describes the connections and IP component parameterizations in your Platform Designer system. You can parse its contents to get requirements when you develop software drivers for IP components. Downstream tools such as the Nios^® II tool chain use this file. The .sopcinfo file and the system.h file generated for the Nios^® II tool chain include address map information for each slave relative to each master that accesses the slave. Different masters may have a different address map to access a particular slave component.
<`your_ip`>.csv	Contains information about the upgrade status of the IP component.
`<your_ip>`.bsf	A Block Symbol File (.bsf) representation of the IP variation for use in Intel^® Quartus^® Prime Block Diagram Files (.bdf).
<`your_ip`>.spd	Required input file for `ip-make-simscript` to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.
<`your_ip`>.ppf	The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner.
<`your_ip`>_bb.v	You can use the Verilog black-box (_bb.v) file as an empty module declaration for use as a black box.
<`your_ip`>_inst.v or _inst.vhd	HDL example instantiation template. You can copy and paste the contents of this file into your HDL file to instantiate the IP variation. This IP core does not support VHDL. However, the Intel^® Quartus^® Prime Pro Edition software generates the _inst.vhd file.
<`your_ip`>.v	HDL files that instantiate each submodule or child IP core for synthesis or simulation.
mentor/	Contains a ModelSim* script msim_setup.tcl to set up and run a simulation.
aldec/	Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a simulation. ls
synopsys/vcs/ synopsys/vcsmx/	Contains a shell script vcs_setup.sh to set up and run a VCS* simulation. Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS MX* simulation.
cadence/	Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSim* simulation.
submodules/	Contains HDL files for the IP core submodules.
<`child IP cores`>/	For each generated child IP core directory, Platform Designer generates synth/ and sim/ sub-directories.

Integrating Your IP Core in Your Design

Pin Assignments

When you integrate your 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core instance in your design, you must make appropriate pin assignments. While compiling the IP core alone, you can create virtual pins to avoid making specific pin assignments for top-level signals. When you are ready to map the design to hardware, you can change to the correct pin assignments.

Adding the Transceiver PLL

1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core requires an external PLL to drive TX serial clock, in order to compile and to function corrrectly in hardware. You must instantiate and connect ATX PLL/fPLL IP core to the 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core.

You can create an external transceiver PLL from the IP Catalog. Select the Intel^® Stratix^® 10 L-Tile/H-Tile Transceiver ATX PLL core or Intel^® Stratix^® 10 L-Tile/H-Tile fPLL core.

Table 9. Instantiate TX PLL
Speed	Reference Clock Frequency (MHz)	PLL Output Clock (MHz)
1G	125	625
2.5G	125	1562.5
10G	644.53125/322.265625	5156.25

Adding the Intel Stratix 10 Transceiver PHY Reset Controller

You must add an Intel^® Stratix^® 10 Transceiver PHY Reset Controller IP core to your design, and connect it to the 1G/2.5/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core reset signals. This block implements a reset sequence that resets the device transceiver correctly.

You can use the IP Catalog to create a transceiver PHY reset controller.

Parameter Settings

You can select the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core for Intel^® Stratix^® 10 devices from the Intel^® Quartus^® Prime Pro Edition IP catalog. To customize the PHY IP core, specify the parameters in the IP parameter editor. The parameter editor dynamically enables the parameter options that apply to the selected operating speed.

Figure 4. 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Parameter Editor

Table 10. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP Core Parameters
Parameter	Options	Description
External PHY
Connect to MGBASE-T PHY	On, Off	Select this option when the external PHY is MGBASE-T compatible. This parameter is enabled for 2.5G, 1G/2.5G, and 1G/2.5G/10G (MGBASE-T) modes.
Connect to NBASE-T PHY	On, Off	Select this option when the external PHY is NBASE-T compatible. This parameter is enabled for 10M/100M/1G/2.5G/5G/10G (USXGMII) modes.
PHY Options
Speed	2.5G 1G/2.5G 1G/2.5G/10G 10M/100M/1G/2.5G/5G/10G	The operating speed of the PHY.
Enable SGMII bridge	On, Off	Select this parameter to enable SGMII 10-Mbps/100-Mbps/1-Gbps. You can enable this parameter for 1G/2.5G, and 1G/2.5G/10G (MGBASE-T) modes.
Enable IEEE 1588 Precision Time Protocol	On, Off	Select this parameter for the PHY to provide latency information to the MAC. The MAC requires this information if it enables the IEEE 1588v2 feature. You can enable this parameter for 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE-T), and 10M/100M/1G/2.5G/5G/10G (USXGMII) modes provided that the SGMII bridge is disabled in 1G/2.5G and 1G/2.5G/10G (MGBASE-T) modes.
PCS Options
PHY ID (32 bit)	32-bit value	An optional 32-bit unique identifier: Bits 3 to 24 of the Organizationally Unique Identifier (OUI) assigned by the IEEE 6-bit model number 4-bit revision number The default value is 0x00000000.
Transceiver Options
VCCR_GXB and VCCT_GXB supply voltage for the transceivers	1.0 V, 1.1 V	This parameter specifies the VCCR_GXB and VCCT_GXB transceiver supply voltage. The default setting is 1.0 V. Use 1.1 V setting if the bank contains transceivers running at 15 Gbps or faster.
Reference clock frequency for 10 GbE (MHz)	322.265625, 644.53125	Specify the frequency of the reference clock for 10GbE. This option is only available for 1G/2.5G/10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) speed modes.
Selected TX PMA local clock division factor for 1 GbE	1, 2, 4, 8	Select the TX local clock division factor for transceiver. The selection is used for 1G Ethernet.
Selected TX PMA local clock division factor for 2.5 GbE	1, 2	Select the TX local clock division factor for transceiver. The selection is used for 2.5G Ethernet.
Dynamic Reconfiguration
Enable Native PHY Debug Master Endpoint (NPDME)	On, Off	When enabled, the Native PHY includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally Avalon^® -MM slave interface. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console.
Enable capability registers	On, Off	Enables capability registers. These registers provide high-level information about the transceiver channel/PLL configuration.
Set user-defined IP identifier	User-specified	Sets a user-defined numeric identifier that can be read from the `user_identifier` offset when the capability registers are enabled.
Enable control and status registers	On, Off	Enables soft registers for reading status signals and writing control signals on the PHY /PLL interface through the NPDME or reconfiguration interface.
Enable PRBS soft accumulators	On, Off	Enables soft logic to perform PRBS bit and error accumulation when using the hard PRBS generator and checker.

Functional Description

The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core for Intel^® Stratix^® 10 devices implements the 10M to 10Gbps Ethernet PHY in accordance with the IEEE 802.3 Ethernet Standard. This IP core handles the frame encapsulation and flow of data between a client logic and Ethernet network via a 10M to 10GbE PCS and PMA (PHY). You can use the Native PHY IP core to configure the transceiver PHY for your protocol implementation. Refer to the Intel^® Stratix^® 10 L- and H-Tile Transceiver PHY User Guide for more information on using the Native PHY IP core.

Figure 5. Architecture of 2.5G, 1G/2.5G, 10M/100M/1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/10G (MGBASE-T) Configuration

In the transmit direction, the PHY encodes the Ethernet frame as required for reliable transmission over the media to the remote end. In the receive direction, the PHY passes frames to the MAC.

Note: You can generate the MAC and PHY design example using the Low Latency Ethernet 10G MAC Intel^® FPGA IP Parameter Editor.

The IP core includes the following interfaces:

Datapath client-interface:
- 10GbE—XGMII, 64 bits
- 10M/100M/1G/2.5GbE—GMII, 16 bit
- 10M/100M/1G/2.5G/5G/10G (USXGMII)—XGMII, 32 bits
For 1G/2.5/10G (MGBASE-T), select an interface based on the respective operating speed.
Management interface— Avalon^® -MM host slave interface for PHY management.
Datapath Ethernet interface with the following available options:
- 10GbE—Single 10.3125 Gbps serial link
- 2.5GbE—Single 3.125 Gbps serial link
- 10M/100M/1GbE—Single 1.25 Gbps SGMII serial link
- 10M/100M/1G/2.5G/5G/10G (USXGMII) —Single 10.3125 Gbps serial link
For 1G/2.5/10G (MGBASE-T), select an ethernet interface based on the respective operating speed.
Transceiver PHY dynamic reconfiguration interface—an Avalon^® -MM interface to read and write the Intel^® Stratix^® 10 Native PHY IP core registers. This interface supports dynamic reconfiguration of the transceiver. It is used to configure the transceiver operating modes to switch to desired Ethernet operating speeds.

Figure 6. Architecture of 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration

The 10M/100M/1G/2.5G/5G/10G (USXGMII) configuration supports the following features:

USXGMII—10M/100M/1G/2.5G/5G/10G speeds
Full duplex data transmission
USXGMII Auto-Negotiation

Clocking and Reset Sequence

Clocking Requirements:

For 64-bit XGMII, the 156.25 MHz clock must have zero ppm difference with reference clock of 10G transceiver PLL. Therefore, the 156.25 MHz clock must derived from the transceiver 10G reference clock for 1G/2.5G/10G (MGBASE-T) variant.
For 32-bit XGMII, the 312.5 MHz clock must have zero ppm difference with reference clock of 10G transceiver PLL. Therefore, the 312.5 MHz clock must derived from the transceiver 10G reference clock for 10M/100M/1G/2.5G/5G/10G (USXGMII) variant.

Reset sequence for all configurations is handled by the transceiver reset controller. For 1G/2.5G and 1G/2.5G/10G (MGBASE-T), transceiver reset sequence is automatically triggered after completion of speed switching/reconfiguration in the MAC+PHY example design.

The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core for Intel^® Stratix^® 10 devices supports up to ±100 ppm clock frequency difference for a maximum packet length of 16,000 bytes.

Timing Constraints

Constrain the PHY based on the fastest speed. For example, if you configure the PHY as 1G/2.5G, constrain it based on 2.5G.

Table 11. Timing Constraints
PHY Configuration	Constrain PHY for
2.5G	2.5G datapath
1G/2.5G	2.5G datapath
1G/2.5G/10G (MGBASE-T)	10G and 1G/2.5G datapath
10M/100M/1G/2.5G/5G/10G (USXGMII)	10G datapath
10M/100M/1G/2.5G	2.5G datapath
10M/100M/1G/2.5G/10G (SGMII/MGBASE-T)	10G and 1G/2.5G datapath

When you configure the PHY in 1G/2.5G/10G (MGBASE-T) configuration, Intel^® recommends that you add the following constraints in the timing constraint file:

Set false path for the clocks used for the different speed so that the Timing Analyzer ignores paths for clocks that are in different groups. For example:

set_clock_groups -physically_exclusive -group [get_clocks {DUT|CHANNEL_GEN[0].u_channel|phy|alt_mge_phy_0|profile0|*}] \
                                       -group [get_clocks {DUT|CHANNEL_GEN[0].u_channel|phy|alt_mge_phy_0|profile1|*}] \
                                       -group [get_clocks {DUT|CHANNEL_GEN[0].u_channel|phy|alt_mge_phy_0|profile2|*}]

where profile0, profile1, and profile2 are created by the transceiver native PHY Synopsys Design Constraint (SDC) for 1G, 2.5G, and 10G clocks respectively.

Set false path from native PHY 10G clock to 1G/2.5G PHY logic and vice versa. Since the 1G/2.5G PHY logic is not running native PHY 10G clock, you do not need to ensure timing closure for the 1G/2.5G data path at 10G clock. For example:
```
set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile2|*}] \
               -to [get_registers {*|alt_mge16_pcs_pma:*|*}]
set_false_path -from [get_registers {*|alt_mge16_pcs_pma:*|*}] \
               -to [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile2|*}]
```
where the path indicated by profile2 is associated to the native PHY 10G clock, whereas the alt_mge16_pcs_pma path indicates the 1G/2.5G PHY logic.

Set false path from native PHY 1G and 2.5G clock to 10G PHY logic and vice versa. Since the 10G PHY logic is not running the native PHY 1G and 2.5G clocks, you do not need to ensure timing closure for the 10G data path at the native PHY 1G and 2.5G clocks. For example:

set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|* \
                                  DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}] \
               -to [get_registers *|alt_mge_phy_xgmii_pcs:*|*]
set_false_path -from [get_registers *|alt_mge_phy_xgmii_pcs:*|*] \
               -to [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|* \
                                DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}]

where the paths indicated by profile0 and profile1 are associated to the native PHY 1G and 2.5G clocks respectively, whereas the alt_mge_phy_xgmii_pcs path indicates the 10G PHY logic.

When you configure the PHY in 1G/2.5G configuration, Intel^® recommends that you add the following constraint in the timing constraint file:

Set false path for the clocks used for the different speed so that the Timing Analyzer ignores paths for clocks that are in different groups. For example:
```
set_clock_groups -physically_exclusive -group [get_clocks {DUT|CHANNEL_GEN[0].u_channel|phy|alt_mge_phy_0|profile0|*}] \
                                       -group [get_clocks {DUT|CHANNEL_GEN[0].u_channel|phy|alt_mge_phy_0|profile1|*}] 
```
where profile0 and profile1 are created by the transceiver native PHY SDC for the 1G and 2.5G clocks respectively.

Switching Operation Speed

Table 12. Supported Operating Speed
PHY Configurations	Features	10M	100M	1G	2.5G	5G	10G
2.5G	Protocol	—	—	—	1000BASE-X at 2.5x	—	—
	Transceiver Data Rate	—	—	—	3.125 Gbps	—	—
	MAC Interface	—	—	—	16-bit GMII @ 156.25 MHz	—	—
10M/100M/1G/2.5G	Protocol	SGMII 100x data replication	SGMII 10x data replication	1000BASE-X / SGMII	1000BASE-X at 2.5x	—	—
	Transceiver Data Rate	1.25 Gbps	1.25 Gbps	1.25 Gbps	3.125 Gbps	—	—
	MAC Interface	16-bit GMII @ 62.5 MHz	16-bit GMII @ 62.5 MHz	16-bit GMII @ 62.5 MHz	16-bit GMII @ 156.25 MHz	—	—
10M/100M/1G/2.5G/10G (MGBASE-T)	Protocol	SGMII	SGMII 10x data replication	1000BASE-X / SGMII	1000BASE-X at 2.5x	—	10GBASE-R
	Transceiver Data Rate	1.25 Gbps	1.25 Gbps	1.25 Gbps	3.125 Gbps	—	10.3125 Gbps
	MAC Interface	16-bit GMII @ 62.5 MHz	16-bit GMII @ 62.5 MHz	16-bit GMII @ 62.5 MHz	16-bit GMII @ 156.25 MHz	—	64-bit XGMII @ 156.25 MHz
10M/100M/1G/2.5G/5G/10G (USXGMII)	Protocol	10GBASE-R 1000x data replication	10GBASE-R 100x data replication	10GBASE-R 10x data replication	10GBASE-R 4x data replication	10GBASE-R 2x data replication	10GBASE-R No data replication
	Transceiver Data Rate¹	10.3125 Gbps	10.3125 Gbps	10.3125 Gbps	10.3125 Gbps	10.3125 Gbps	10.3125 Gbps
	MAC Interface	32-bit XGMII @ 312.5 MHz	32-bit XGMII @ 312.5 MHz	32-bit XGMII @ 312.5 MHz	32-bit XGMII @ 312.5 MHz	32-bit XGMII @ 312.5 MHz	32-bit XGMII @ 312.5 MHz

You can change the PHY speed using the reconfiguration block in the MAC+PHY example design.

Initiates the speed change by writing to the corresponding register of the reconfiguration block.²
The reconfiguration block performs the following steps:
1. Sets the xcvr_mode signal of the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core to the requested speed.
2. Reads the generated .mif file for the configuration settings and configures the transceiver accordingly.
3. Selects the corresponding transceiver PLL.
4. Triggers the transceiver recalibration.
The reconfiguration block triggers the PHY reset through the transceiver reset controller.

¹ With oversampling for lower data rates.

² You can change the speed within SGMII (10M/100M/1G) and USXGMII (10M/100M/1G/2.5G/5G/10G) through CSR. It doesn't require reconfiguration block.

Configuration Registers

Register Map

You can access the 16-bit/32-bit configuration registers ³ via the Avalon^® -MM interface.

Table 13. Register Map Overview
Address Range	Usage	Register Width	Configuration
0x00–0x1F	1000BASE-X/SGMII	16	2.5G, 1G/2.5G, 10M/100M/1G/2.5G, 10M/100M/1G/2.5G/10G (MGBASE-T), 1G/2.5G/10G (MGBASE-T)
0x400–0x41F	USXGMII	32	10M/100M/1G/2.5G/5G/10G (USXGMII)
0x461	Serial Loopback	32	10M/100M/1G/2.5G/5G/10G (USXGMII)

³ These registers are identical to the Intel^® Arria^® 10 variation of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core.

Register Definitions

Observe the following guidelines when accessing the registers:

Do not write to reserved or undefined registers.
When writing to the registers, perform read-modify-write operation to ensure that reserved or undefined register bits are not overwritten.

Table 14. Types of Register Access
Access	Definition
RO	Read only.
RW	Read and write.
RWC	Read, write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP core clears the bit(s) upon executing the instruction.

Table 15. PHY Registers
Address	Name	Description	Access	HW Reset Value
0x00	`control`	Bit [15]: `RESET`. Set this bit to 1 to trigger a soft reset. The PHY clears the bit when the reset is completed. The register values remain intact during the reset.	RWC	0
		Bit[14]: `LOOPBACK`. Set this bit to 1 to enable loopback on the serial interface.	RW	0
		Bit [12]: `AUTO_NEGOTIATION_ENABLE`. Set this bit to 1 to enable auto-negotiation. Auto-negotiation is supported only in 1GbE. Therefore, set this bit to 0 when you switch to a speed other than 1GbE.	RW	0
		Bit [9]: `RESTART_AUTO_NEGOTIATION`. Set this bit to 1 to restart auto-negotiation. The PHY clears the bit as soon as auto-negotiation is restarted.	RWC	0
		All other bits are reserved.	—	—
0x01	`status`	Bit [5]: `AUTO_NEGOTIATION_COMPLETE`. A value of "1" indicates that the auto-negotiation is completed.	RO	0
		Bit [3]: `AUTO_NEGOTIATION_ABILITY`. A value of "1" indicates that the PCS function supports auto-negotiation.	RO	1
		Bit [2]: `LINK_STATUS`. A value of "0" indicates that the link is lost. A value of "1" indicates that the link is established.	RO	0
		All other bits are reserved.	—	—
0x02:0x03	`phy_identifier`	The value set in the PHY_IDENTIFIER parameter.	RO	Value of PHY_IDENTIFIER parameter
0x04	`dev_ability`	Use this register to advertise the device abilities during auto-negotiation.	—	—
		Bits [13:12]: `RF`. Specify the remote fault. 00: No error. 01: Link failure. 10: Off-line. 11: Auto-negotiation error.	RW	00
		Bits [8:7]: `PS`. Specify the PAUSE support. 00: No PAUSE. 01: Symmetric PAUSE. 10: Asymmetric PAUSE towards the link partner. 11: Asymmetric and symmetric PAUSE towards the link device.	RW	11
		Bit [5]: `FD`. Ensure that this bit is always set to 1.	RW	1
		All other bits are reserved.	—	—
0x05 (1000BASE-X mode)	`partner_ability`	The device abilities of the link partner during auto-negotiation.	—	—
		Bit [14]: `ACK`. A value of "1" indicates that the link partner has received three consecutive matching ability values from the device.	RO	0
		Bits [13:12]: `RF`. The remote fault. 00: No error. 01: Link failure. 10: Off-line. 11: Auto-negotiation error.	RO	0
		Bits [8:7]: `PS`. The PAUSE support. 00: No PAUSE. 01: Symmetric PAUSE. 10: Asymmetric PAUSE towards the link partner. 11: Asymmetric and symmetric PAUSE towards the link device.	RO	0
		Bit [6]: `HD`. A value of "1" indicates that half-duplex is supported.	RO	0
		Bit [5]: `FD`. A value of "1" indicates that full-duplex is supported.	RO	0
		All other bits are reserved.	—	—
0x05 (SGMII mode)	`partner_ability`	The device abilities of the link partner during auto-negotiation.	—	—
		Bit [11:10]: `COPPER_SPEED` Link partner speed: 00: copper interface speed is 10 Mbps 01: copper interface speed is 100 Mbps 10: copper interface speed is 1 Gigabit 11: reserved	RO	00
		Bit [12]: `COPPER_DUPLEX_STATUS` Link partner capability: 1: copper interface is capable of full-duplex operation 0: copper interface is capable of half-duplex operation	RO	0
		Bit [14]: `ACK`. Link partner acknowledge. A value of 1 indicates that the device received three consecutive matching ability values from its link partner.	RO	0
		Bit [15]: `COPPER_LINK_STATUS` Link partner status: 1: copper interface link is up 0: copper interface link is down	RO	0
		All other bits are reserved.	—	—
0x06	`an_expansion`	The PCS capabilities and auto-negotiation status.	—	—
		Bit [1]: `PAGE_RECEIVE`. A value of "1" indicates that the partner_ability register has been updated. This bit is automatically cleared once it is read.	RO	0
		Bit [0]: `LINK_PARTNER_AUTO_NEGOTIATION_ABLE`. A value of "1" indicates that the link partner supports auto-negotiation.	RO	0
0x07	`device_next_page`	The PHY does not support the next page feature. These registers are always set to 0.	RO	0
0x08	`partner_next_page`		RO	0
0x09:0x0F	Reserved	—	—	—
0x10	`scratch`	Provides a memory location to test read and write operations.	RW	0
0x10	`scratch`	Bit [31:16]: Reserved	—	—
0x11	`rev`	The current version of the PHY IP core.	RO	Current version of the PHY
0x11	`rev`	Bit [31:16]: Reserved	—	—
0x12:0x13	`link_timer`	21-bit auto-negotiation link timer spans across two 16-bit registers, which have offset 0x12 and offset 0x13. Offset 0x12: link_timer[15:0]. Bits [8:0] are always be set to 0. Offset 0x13: link_timer[20:16] occupies the lower 5 bits. The remaining 11 bits are reserved and must always be set to 0.	RW	0
0x14	`if_mode`	Interface Mode Register	—	—
		Bit [0]: `SGMII_ENA` Determines the PCS function operating mode. Setting this bit to 1b'1 enables SGMII mode. Setting this bit to 1b'0 enables 1000BASE-X gigabit mode.	RW	0
		Bit [1]: `USE_SGMII_AN` In SGMII mode, setting this bit to 1b'1 configures the PCS with the link partner abilities advertised during auto-negotiation. If this bit is set to 1b'0, the PCS function should be configured with the `SGMII_SPEED` bits.	RW	0
		Bit [3:2]: `SGMII_SPEED` When the PCS operates in SGMII mode (`SGMII_ENA` = 1) and is not programmed for automatic configuration (`USE_SGMII_AN` = 0), the following encodings specify the speed: 2'b00: 10 Mbps 2'b01: 100 Mbps 2'b10: Gigabit 2'b11: Reserved These bits are not used when `SGMII_ENA` = 0 or `USE_SGMII_AN` = 1.	RW	0
		All other bits are reserved.	—	—
0x15:0x1F	Reserved	—	—	—
0x400	`usxgmii_control`	Control Register	—	—
		Bit [0]: `USXGMII_ENA`: 0: 10GBASE-R mode 1: USXGMII mode	RW	0
		Bit [1]: `USXGMII_AN_ENA` is used when `USXGMII_ENA` is set to 1: 0: Disables USXGMII Auto-Negotiation and manually configures the operating speed with the `USXGMII_SPEED` register. 1: Enables USXGMII Auto-Negotiation, and automatically configures operating speed with link partner ability advertised during USXGMII Auto-Negotiation.	RW	1
		Bit [4:2]: `USXGMII_SPEED` is the operating speed of the PHY in USXGMII mode and `USE_USXGMII_AN` is set to 0. 3’b000: 10M 3’b001: 100M 3’b010: 1G 3’b011: 10G 3’b100: 2.5G 3’b101: 5G 3’b110: Reserved 3’b111: Reserved	RW	0
		Bit [8:5]: Reserved	—	—
		Bit [9]: RESTART_AUTO_NEGOTIATION Write 1 to restart Auto-Negotiation sequence The bit is cleared by hardware when Auto-Negotiation is restarted.	RWC	0
		Bit [31:10]: Reserved	—	—
0x401	`usxgmii_status`	Status Register	—	—
		Bit [1:0]: Reserved	—	—
		Bit [2]: `LINK_STATUS` indicates link status for USXGMII all speeds 1: Link is established 0: Link synchronization is lost, a 0 is latched	RO	0
		Bit [4:3]: Reserved	—	—
		Bit [5]: `AUTO_NEGOTIATION_COMPLETE` A value of 1 indicates the Auto-Negotiation process is completed.	RO	0
		Bit [31:6]: Reserved	—	—
0x402:0x404	Reserved	—	—	—
0x405	`usxgmii_partner_ability`	Device abilities advertised to the link partner during Auto-Negotiation	—	—
		Bit [6:0]: Reserved	—	—
		Bit [7]: `EEE_CLOCK_STOP_CAPABILITY` Indicates whether or not energy efficient Ethernet (EEE) clock stop is supported. 0: Not supported 1: Supported	RO	0
		Bit [8]: `EEE_CAPABILITY` Indicates whether or not EEE is supported. 0: Not supported 1: Supported	RO	0
		Bit [11:9]: `SPEED` 3'b000: 10M 3'b001: 100M 3'b010: 1G 3'b011: 10G 3'b100: 2.5G 3'b101: 5G 3'b110: Reserved 3'b111: Reserved	RO	0
		Bit [12]: `DUPLEX` Indicates the duplex mode. 0: Half duplex 1: Full duplex	RO	0
		Bit [13]: Reserved	—	—
		Bit [14]: `ACKNOWLEDGE` A value of 1 indicates that the device has received three consecutive matching ability values from its link partner.	RO	0
		Bit [15]: `LINK` Indicates the link status. 0: Link down 1: Link up	RO	0
		Bit [31:16]: Reserved	—	—
0x406:0x411	Reserved	—	—	—
0x412	`usxgmii_link_timer`	Auto-Negotiation link timer. Sets the link timer value in bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensure that it matches the link timer value of the external NBASE-T PHY IP Core. The reset value sets the link timer to approximately 1.6 ms. Bits [13:0] are reserved and always set to 0.	[19:14]: RW [13:0]: RO	[19:14]: 1F [13:0]: 0
0x413:0x41F	Reserved	—	—	—
0x461	`phy_serial_loopback`	Configures the transceiver serial loopback in the PMA from TX to RX.	—	—
		Bit [0] 0: Disables the PHY serial loopback 1: Enables the PHY serial loopback	RW	0
		Bit [31:1]: Reserved	—	—

Interface Signals

Figure 7. Interface Signals

Clock and Reset Signals

Table 16. Clock and Reset Signals
Signal Name	Direction	Width	Description	PHY Configurations
Clock signals
`tx_clkout`	Output	1	GMII TX clock, derived from `tx_serial_clk[1:0]`. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE; 6.25 MHz for 100M; 0.625 MHz for 10M.	2.5G 1G/2.5G 10M/100M/1G,2.5G 1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/10G (MGBASE-T)
`rx_clkout`	Output	1	GMII RX clock, derived from `tx_serial_clk[1:0]`. Provides 156.25 MHz timing reference for 2.5GbE; 62.5 MHz for 1GbE; 6.25 MHz for 100M; 0.625 MHz for 10M.	2.5G 1G/2.5G 10M/100M/1G/2.5G 1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/10G (MGBASE-T)
`csr_clk`	Input	1	Clock for the Avalon^® -MM control and status interface. Intel recommends 125 – 156.25 MHz for this clock.	All
`xgmii_tx_coreclkin`	Input	1	XGMII TX clock. Provides 156.25 MHz timing reference for 10GbE and 312.5 MHz for 10M/100M/1G/2.5G/5G/10G (USXGMII) mode. Synchronous to `tx_serial_clk` with zero ppm.	1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/5G/10G (USXGMII)
`xgmii_rx_coreclkin`	Input	1	XGMII RX clock. Provides 156.25 MHz timing reference for 10GbE and 312.5 MHz for 10M/100M/1G/2.5G/5G/10G (USXGMII) mode.	1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/5G/10G (USXGMII)
`latency_measure_clk`	Input	1	Sampling clock for measuring the latency of the 16-bit GMII datapath. This clock operates at 80 MHz and is available only when the IEEE 1588v2 feature is enabled.	2.5G 1G/2.5G 1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
`latency_sclk`	Input	1	Sampling clock for measuring the latency of the transceiver AIB datapath. The clock period is 6.5 ns. It is available only when the IEEE 1588v2 feature is enabled.	2.5G 1G/2.5G 1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature 10M/100M/1G/2.5G/5G/10G (USXGMII)
Serial interface clock signals
`tx_serial_clk`	Input	1-3	Serial clock from transceiver PLLs. 2.5GbE: Connect bit [0] to the transceiver PLL. This clock operates at 1562.5 MHz. 1GbE: Connect bit [1] to the transceiver PLL. This clock operates at 625 MHz. 10GbE: Connect bit [2] to the transceiver PLL. This clock operates at 5156.25 MHz. 10M/100M/1G/2.5G/5G/10G (USXGMII) mode: Connect bit [0] to 5156.25 MHz.	All
`rx_cdr_refclk`	Input	1	125-MHz RX CDR reference clock for 1GbE and 2.5GbE	2.5G 1G/2.5G, 10M/100M/1G/2.5G 1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/10G (MGBASE-T)
`rx_cdr_refclk_1`	Input	1	RX CDR reference clock for 10G of 1G/2.5G/10G (MGBASE-T) and all speeds of USXGMII. The frequency of this clock can be either 322.265625 MHz or 644.53125 MHz, as specified by the Reference clock frequency for 10 GbE (MHz) parameter setting.	1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/5G/10G (USXGMII)
`rx_pma_clkout`	Output	1	Recovered clock from CDR, operates at the following frequency: 10M/100M/1G/2.5G/5G/10G (USXGMII) speed mode: All speeds: 156.25 MHz Other speed modes: 1GbE: 125 MHz 2.5GbE: 312.5 MHz 10GbE: 156.25 MHz	All
Reset signals
`reset`	Input	1	Active-high global reset. Assert this signal to trigger an asynchronous global reset.	All
`tx_analogreset`	Input	1	Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the analog block on the TX path.	All
`tx_analogreset_stat`	Output	1	Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.	All
`tx_digitalreset`	Input	1	Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the TX path.	All
`tx_digitalreset_stat`	Output	1	Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.	All
`rx_analogreset`	Input	1	Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the receiver CDR.	All
`rx_analogreset_stat`	Output	1	Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.	All
`rx_digitalreset`	Input	1	Connect this signal to the Transceiver PHY Reset Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the RX path.	All
`rx_digitalreset_stat`	Output	1	Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.	All

Transceiver Mode and Operating Speed Signals

Table 17. Transceiver Mode and Operating Speed Signals
Signal Name	Direction	Width	Description	PHY configurations
`xcvr_mode`	Input	2	Connect this signal to the reconfiguration block. Use the following values to set the speed: 0x0 = 1G 0x1 = 2.5G 0x3 = 10G	2.5G 1G/2.5G 10M/100M/1G/2.5G 1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/10G (MGBASE-T)
`operating_speed`	Output	3	Connect this signal to the MAC. This signal provides the current operating speed of the PHY: 0x0 = 10G 0x1 = 1G 0x2 = 100M 0x3 = 10M 0x4 = 2.5G 0x5 = 5G	All

Serial Interface Signals

The serial interface connects to an external device.

Table 18. Serial Interface Signals
Signal Name	Direction	Width	Description	PHY Configurations
`tx_serial_data`	Output	1	Transmit data	All
`rx_serial_data`	Input	1	Receive data	All

GMII Signals

The 16-bit TX and RX GMII supports 1GbE and 2.5GbE at 62.5 MHz and 156.25 MHz respectively.

Table 19. GMII Signals
Signal Name	Direction	Width	Description	PHY Configurations
TX GMII signals — synchronous to `tx_clkout`
`gmii16b_tx_d`	Input	16	TX data from the MAC. The MAC sends the lower byte first followed by the upper byte.	2.5G 1G/2.5G 10M/100M/1G/2.5G 1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/10G (MGBASE-T)
`gmii16b_tx_en`	Input	2	When asserted, indicates the start of a new frame from the MAC. Bit[0] corresponds to `gmii16b_tx_d`[7:0]; bit[1] corresponds to `gmii16b_tx_d`[15:8]. This signal remains asserted until the PHY receives the last byte of the data frame.
`gmii16b_tx_err`	Input	2	When asserted, indicates an error. Bit[0] corresponds to `gmii16b_tx_err`[7:0]; bit[1] corresponds to `gmii16b_tx_err`[15:8]. The bits can be asserted at any time during a frame transfer to indicate an error in the current frame.
`gmii16b_tx_latency`	Output	22	The latency of the PHY excluding the PMA block on the TX datapath: Bits [21:10]: The number of clock cycles. Bits [9:0]: The fractional number of clock cycles. This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.	2.5G 1G/2.5G with IEEE 1588v2 feature 1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
`tx_clkena`	Output	1	TX clock enable for SGMII 10M/100M operating speeds. In 1 Gbps mode, this signal is always asserted; in 100 Mbps mode, this signal is asserted once every 10 clock cycles; in 10 Mbps mode, this signal is asserted once every 100 clock cycles. For 100M mode, `tx_clkout` is divided to 6.25 MHz. For 10M mode, `tx_clkout` is divided to 0.625 MHz. This signal is available when only the Enable SGMII bridge parameter is selected.	10M/100M/1G/2.5G 10M/100M/1G/2.5G/10G (MGBASE-T)
RX GMII signals — synchronous to `rx_clkout`
`gmii16b_rx_d`	Output	16	RX data to the MAC. The PHY sends the lower byte first followed by the upper byte. Rate matching is done by the PHY on the RX data from the RX recovered clock to `rx_clkout`.	2.5G 1G/2.5G 10M/100M/1G/2.5G 1G/2.5G/10G (MGBASE-T) 10M/100M/1G/2.5G/10G(MGBASE-T)
`gmii16b_rx_err`	Output	2	When asserted, indicates an error. Bit[0] corresponds to `gmii16b_rx_err`[7:0]; bit[1] corresponds to `gmii16b_rx_err`[15:8]. The bits can be asserted at any time during a frame transfer to indicate an error in the current frame.
`gmii16b_rx_dv`	Output	2	When asserted, indicates the start of a new frame. Bit[0] corresponds to `gmii16b_rx_d`[7:0]; bit[1] corresponds to `gmii16b_rx_d`[15:8]. This signal remains asserted until the PHY sends the last byte of the data frame.
`gmii16b_rx_latency`	Output	22	The latency of the PHY excluding the PMA block on the RX datapath: Bits [21:10]: The number of clock cycles. Bits [9:0]: The fractional number of clock cycles. This signal is available only when the Enable IEEE 1588 Precision Time Protocol parameter is selected.	2.5G 1G/2.5G with IEEE 1588v2 feature 1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
`rx_clkena`	Output	1	RX clock enable for SGMII 10M/100M operating speeds. In 1 Gbps mode, this signal is always asserted; in 100Mbps mode, this signal is asserted once every 10 clock cycles; in 10 Mbps mode, this signal is asserted once every 100 clock cycles. For 100M mode, `rx_clkout` is divided to 6.25 MHz. For 10M mode, `rx_clkout` is divided to 0.625 MHz. This signal is available when only the Enable SGMII bridge parameter is selected.	10M/100M/1G/2.5G 10M/100M/1G/2.5G/10G (MGBASE-T)

XGMII Signals

The XGMII supports 10GbE at 156.25 MHz.

Table 20. XGMII Signals

Signal Name

Direction

Width

Description

PHY Configurations

TX XGMII signals — synchronous to xgmii_tx_coreclkin

xgmii_tx_data

Input

64, 32

TX data from the MAC. The MAC sends the data in the following order: bits [7:0], bits [15:8], bit [23:16], and so on.

The width is:

64 bits for 1G/2.5G/10G (MGBASE-T) configurations.
32 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.

1G/2.5G/10G (MGBASE-T)
10M/100M/1G/2.5G/10G (MGBASE-T)
10M/100M/1G/2.5G/5G/10G (USXGMII)

xgmii_tx_control

Input

8, 4

TX control from the MAC. The xgmii_tx_control bit corresponds to the xgmii_tx_data bits. For example, xgmii_tx_control[0] corresponds to xgmii_tx_data[7:0], xgmii_tx_control[1]corresponds to xgmii_tx_data[15:8], and so on.

The width is:

8 bits for 1G/2.5G/10G (MGBASE-T) configurations.
4 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.

xgmii_tx_valid

Input

Indicates valid data on xgmii_tx_control and xgmii_tx_data from the MAC.

Your logic/MAC must toggle the valid data as shown below:

Speed	Toggle Rate
10M	Asserted once every 1000 clock cycles
100M	Asserted once every 100 clock cycles
1G	Asserted once every 10 clock cycles
2.5G	Asserted once every 4 clock cycles
5G	Asserted once every 2 clock cycles
10G	Asserted on every clock cycle

10M/100M/1G/2.5G/5G/10G (USXGMII)

xgmii_tx_latency

Output

16, 24

The latency of the PHY excluding the PMA block on the TX datapath:

Bits [15:10] and [23:10]: The number of clock cycles.
Bits [9:0]: The fractional number of clock cycles.

The width is:

16 bits for 1G/2.5G/10G (MGBASE-T) with IEEE 1588 configurations.
24 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.

This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.

Note: For USXGMII configuration, the latency value may be unstable for the first three transmitted packets times (at least 64 bytes). You should not use the latency value within this period.

1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
10M/100M/1G/2.5G/5G/10G (USXGMII)

RX XGMII signals — synchronous to xgmii_rx_coreclkin

xgmii_rx_data

Output

64, 32

RX data to the MAC. The PHY sends the data in the following order: bits [7:0], bits [15:8], bit [23:16], and so on.

The width is:

64 bits for 1G/2.5G/10G (MGBASE-T) configurations.
32 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.

1G/2.5G/10G (MGBASE-T)
10M/100M/1G/2.5G/10G (MGBASE-T)
10M/100M/1G/2.5G/5G/10G (USXGMII)

xgmii_rx_control

Output

8, 4

RX control to the MAC. The xgmii_rx_control bit corresponds to the xgmii_rx_data bits. For example, xgmii_rx_control[0] corresponds to xgmii_rx_data[7:0], xgmii_rx_control[1] corresponds to xgmii_rx_data[15:8], and so on.

The width is:

8 bits for 1G/2.5G/10G (MGBASE-T) configurations.
4 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.

xgmii_rx_valid

Output

Indicates valid data on xgmii_rx_control and xgmii_rx_data from the MAC.

The toggle rate from the PHY is shown in the table below.

Speed	Toggle Rate
10M	Asserted once every 1000 clock cycles
100M	Asserted once every 100 clock cycles
1G	Asserted once every 10 clock cycles
2.5G	Asserted once every 4 clock cycles
5G	Asserted once every 2 clock cycles
10G	Asserted on every clock cycle

Note: The toggle rate may vary when the start of a packet is received or when rate match occurs inside the PHY. You should not expect the valid data pattern to be fixed.

10M/100M/1G/2.5G/5G/10G (USXGMII)

xgmii_rx_latency

Output

16, 24

The latency of the PHY excluding the PMA block on the TX datapath:

Bits [15:10]: The number of clock cycles.
Bits [9:0]: The fractional number of clock cycles.

The width is:

16 bits for 1G/2.5G/10G (MGBASE-T) with IEEE 1588 configurations.
24 bits for 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.

This signal is available when only the Enable IEEE 1588 Precision Time Protocol parameter is selected.

Note: For USXGMII configuration, the latency value may be unstable for the first three transmitted packets times (at least 64 bytes). You should not use the latency value within this period.

1G/2.5G/10G (MGBASE-T) with IEEE 1588v2 feature
10M/100M/1G/2.5G/5G/10G (USXGMII)

Avalon -MM Interface Signals

The Avalon^® -MM interface is an Avalon^® -MM slave port. This interface uses word addressing and provides access to the 16-bit configuration registers of the PHY. The following signals are synchronous to csr_clk.

Table 21. Avalon^® -MM Interface Signals
Signal Name	Direction	Width	Description	PHY Configurations
`csr_address`	Input	5, 11	Use this bus to specify the register address to read from or write to. The width is: 5 bits for 2.5G and 1G/2.5G configurations. 11 bits for 1G/2.5G/10G (MGBASE-T) and 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations.	All
`csr_read`	Input	1	Assert this signal to request a read operation.
`csr_readdata`	Output	16, 32	Data read from the specified register. The data is valid only when the `csr_waitrequest` signal is deasserted. The width is: 16 bits for 2.5G and 1G/2.5G configurations. 32 bits for 1G/2.5G/10G (MGBASE-T) and 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations. The upper 16 bits are reserved.
`csr_write`	Input	1	Assert this signal to request a write operation.
`csr_writedata`	Input	16, 32	Data to be written to the specified register. The data is written only when the `csr_waitrequest` signal is deasserted. The width is: 16 bits for 2.5G and 1G/2.5G configurations. 32 bits for 1G/2.5G/10G (MGBASE-T) and 10M/100M/1G/2.5G/5G/10G (USXGMII) configurations. The upper 16 bits are reserved.
`csr_waitrequest`	Output	1	When asserted, indicates that the PHY is busy and not ready to accept any read or write requests. When you have requested for a read or write, keep the control signals to the Avalon^® -MM interface constant while this signal is asserted. The request is complete when it is deasserted. This signal can be high or low during idle cycles and reset. Therefore, the user application must not make any assumption of its assertion state during these periods.

Transceiver Status and Reconfiguration Signals

Table 22. Transceiver Status and Reconfiguration Signals
Signal Name	Direction	Width	Description	PHY Configurations
`rx_is_lockedtodata`	Output	1	Asserted when the CDR is locked to the RX data.	All
`tx_cal_busy`	Output	1	Asserted when TX calibration is in progress.
`rx_cal_busy`	Output	1	Asserted when RX calibration is in progress.
Transceiver reconfiguration signals
`reconfig_clk`	Input	1	Reconfiguration signals connected to the reconfiguration block. The `reconfig_clk` signal provides the timing reference for this interface.	All
`reconfig_reset`	Input	1
`reconfig_address`	Input	11
`reconfig_write`	Input	1
`reconfig_read`	Input	1
`reconfig_writedata`	Input	32
`reconfig_readdata`	Output	32
`reconfig_waitrequest`	Output	1

Status Signals

Table 23. Status Signals

Signal Name

Direction

Clock Domain

Width

Description

PHY Configurations

led_char_err

Output

Synchronous to rx_clkout

Asserted when a 10-bit character error is detected in the RX data. This signal is not applicable for 10GbE.

2.5G
1G/2.5G
10M/100M/1G/2.5G
1G/2.5G/10G (MGBASE-T)
10M/100M/1G/2.5G/10G (MGBASE-T)

led_link

Output

Synchronous to tx_clkout

Asserted when the link synchronization for 1GbE or 2.5GbE is successful. This signal is not applicable for 10GbE.

led_disp_err

Output

Synchronous to rx_clkout

Asserted when a 10-bit running disparity error is detected in the RX data. A running disparity error indicates that more than the previous and perhaps the current received group had an error. This signal is not applicable for 10GbE.

led_an

Output

Synchronous to rx_clkout

Asserted when auto-negotiation is completed. This signal is not applicable for 10GbE.

All

led_panel_link

Output

Synchronous to rx_clkout

When asserted, this signal indicates the following behavior:

Mode	Behavior
1000 Base-X without Auto-negotiation	When asserted, indicates successful link synchronization.
SGMII mode without Auto-negotiation	When asserted, indicates successful link synchronization.
1000 Base-X with Auto-negotiation	Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.
SGMII mode with MAC mode Auto-negotiation	Clause 37 Auto-negotiation status. The PCS function asserts this signal when auto-negotiation completes.

This signal is applicable only when SGMII 10M/100M mode is enabled.

10M/100M/1G/2.5G
10M/100M/1G/2.5G/10G (MGBASE-T)

rx_block_lock

Output

Synchronous to rx_clkout

Asserted when the link synchronization for 10GbE of MGBASE-T and all speeds of USXGMII is successful.

1G/2.5G/10G (MGBASE-T)
10M/100M/1G/2.5G/10G (MGBASE-T)
10M/100M/1G/2.5G/5G/10G (USXGMII)

The latency indicators are connected from PHY to MAC block, where the MAC block uses them to calculate timestamp of the transmitted or received packets. For more information, refer to Low Latency Ethernet 10G MAC Intel^® Stratix^® 10 FPGA IP Design Example User Guide.

1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel Stratix 10 FPGA IP User Guide Archives

If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version	User Guide
18.0	1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® Stratix^® 10 FPGA IP User Guide
17.1	Intel^® Stratix^® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core User Guide

Document Revision History for the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel Stratix 10 FPGA IP User Guide

Document Version	Intel^® Quartus^® Prime Version	Changes
2019.05.10	19.1	Renamed Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME). Updated the Clocking and Reset Sequence topic to state that the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core for Intel^® Stratix^® 10 devices supports up to ±100 ppm clock frequency difference for a maximum packet length of 16,000 bytes.
2019.01.30	18.0	Updated Table: Clock and Reset Signals to update the description for `rx_pma_clkout`.
2018.09.24	18.0	Updated the note in About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP Core topic. Updated Table: Status Signals to include a Clock Domain column. Updated the Functional Description topic. Updated the Timing Constraints topic. Updated Table: XGMII Signals: Corrected the direction of `xgmii_tx_valid`. Updated the toggle rate of 10G speed for `xgmii_tx_valid` and `xgmii_rx_valid`. Renamed topic title Register Access to Register Definitions. Made minor editorial edits.
2018.05.07	18.0	Renamed the document as 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel Stratix 10 FPGA IP User Guide. Renamed "1G/2.5G/5G/10G Multi-rate Ethernet PHY" IP core to "1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP" as per Intel rebranding. Added support for the following variants: 10M/100M/1G/2.5G/5G/10G (USXGMII) 10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588v2 Updated topic title Datasheet to About 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP. Updated the About 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP topic. Updated Table: 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core Features. Updated Table: Resource Utilization: Updated the resource utilization for all configurations. Added resource utilization information for 10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588v2 configuration. Removed a note from the Specifying the IP Core Parameters and Options topic. Updated Table: Slowest Supported Device Speed Grades with supported speed grade for 10M/100M/1G/2.5G/5G/10G (USXGMII) with 1588 feature. Updated Figure: IP Parameter Editor. Updated Table: 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP Core Parameters: Updated descriptions for Connect to MGBASE-T PHY, Connect to NBASE-T PHY, Enable IEEE 1588 Precision Time Protocol, PHY ID (32 bit), and Reference clock frequency for 10 GbE (MHz) parameters. Updated options for Speed parameter. Updated the Functional Description topic. Updated the Clocking and Reset Sequence topic. Updated Table: Timing Constraints to include 10M/100M/1G/2.5G and 10M/100M/1G/2.5G/10G (SGMII/MGBASE-T) configurations. Renamed topic title Register Definitions to Register Access. Updated Table: PHY Registers Definition: Updated the description for Bit [4:2]: `USXGMII_SPEED` of the `usxgmii_control` signal. Updated the description for `link_timer` signal. Updated Figure: Interface Signals. Updated Tables: Clock and Reset Signals, GMII Signals, and XGMII Signals. Updated for latest Intel branding standards. Made editorial updates throughout the document.

Date	Version	Changes
November 2017	2017.11.06	Changed the document title from Intel^® Stratix^® 10 Multi-rate Ethernet PHY IP Core User Guide to Intel^® Stratix^® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core User Guide. Added support for the 1G/2.5G/5G/10G (USXGMII) variant. Added new Table: Slowest Supported Device Speed Grades to include speed grade support. Added resource utilization for 1G/2.5G/5G/10G (USXGMII) configuration. Added new chapter Getting Started explaining how to install, generate and integrate IP core in your design. Added information in Clocking and Reset Sequence to confirm that the Intel^® Stratix^® 10 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core can handle clock frequency difference up to ±100 ppm. Added the PHY configuration information in Interface Signals section.
June 2017	2017.06.05	Added the SGMII (10M/100M/1G) support for 1G/2.5G and 1G/2.5/10G (MGBASE-T). Added resource utilization for 1G/2.5G with IEEE 1588v2 enabled, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G configurations. Added the Enable SGMII bridge parameter and removed the Enable ODI acceleration logic parameter in the Table: 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP Core Parameters. Updated the Table: Supported Operating Speed with SGMII mode information. Added registers for SGMII mode (see address 0x05 (SGMII mode) and 0x14). Added the following signals: `tx_clkena` and `rx_clkena` in Table: GMII Signals. `led_panel_link` in Table: Status Signals.
May 2017	2017.05.08	Initial release.