The Low Latency (LL) Ethernet 10G (10GbE) Media Access Controller (MAC) Intel^® FPGA IP core includes Intel^® Stratix^® 10 and Intel^® Arria^® 10 design examples that are compliant with IEEE 802.3-2008 specification. The interfaces between Intel^® Stratix^® 10 LL 10GbE MAC Intel^® FPGA IP core and physical interface (PHY) IP core are different compared to Intel^® Arria^® 10 LL 10GbE MAC Intel^® FPGA IP core with PHY IP core.

These migration guidelines are meant for those are familiar with Intel^® Arria^® 10 LL 10GbE MAC Intel^® FPGA IP core. Use these migration guidelines if you want to migrate your Intel^® Arria^® 10 LL 10GbE MAC design to use Intel^® Stratix^® 10 devices.

The following table lists all the possible Intel^® Stratix^® 10 and Intel^® Arria^® 10 Ethernet IP configurations.

You can configure the Intel^® Stratix^® 10 Transceiver Native PHY IP core to implement 10GBASE-R PHY with the Ethernet-specific physical layer running at 10.3125 Gbps data rate as defined in Clause 49 of IEEE 802.3-2008 specification. This configuration provides an XGMII to LL 10GbE MAC Intel^® FPGA IP core and implements a single-channel 10.3125Gbps PHY for a direct connection to a small form-factor pluggable plus (SFP+) optical module using the small form-factor interface (SFI) electrical specification.

The following figure illustrates the migration from an Intel^® Arria^® 10 design to a Intel^® Stratix^® 10 design.

1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core for Intel^® Stratix^® 10 devices provides GMII and XGMII to the LL 10GbE MAC Intel^® FPGA IP core. The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core implements a single channel 1G/2.5G/5G/10Gbps serial PHY. The design provides a direct connection to 1G/2.5GbE dual speed SFP+ pluggable modules, MGBASE-T copper external PHY devices, or chip-to-chip interfaces. These IP cores support reconfigurable data rates.

The following figure illustrates then migration from an Intel^® Arria^® 10 design to a Intel^® Stratix^® 10 design.

The following figure illustrates the latest clocking and reset scheme of the 1G/2.5G Ethernet with IEEE 1588v2 feature design example targeted on Intel^® Stratix^® 10 devices. There are differences between this solution and the version that was introduced in the Intel^® Arria^® 10 devices. Modification is needed when migrating design from the Intel^® Arria^® 10 devices to the Intel^® Stratix^® 10 devices.

A new input clock port latency_sclk is available in Intel^® Stratix^® 10 devices. This port is available when you turn on the Enable latency measurement ports parameter in the Intel^® Stratix^® 10 L/H-Tile Transceiver Native PHY IP core or the Enable IEEE 1588 Precision Time Protocol parameter in the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP core. This port is required for deterministic latency measurement model for Intel^® Stratix^® 10 devices. For more information, refer to the Deterministic Latency Use Model chapter in Intel^® Stratix^® 10 L/H-Tile Transceiver PHY User Guide.

To connect an I/O phase-locked loop (IOPLL), add a Intel^® Stratix^® 10 Clock Control (stratix10_clkctrl) IP from the IP Catalog. The IOPLL provides two sampling clocks in this design: 53.33 MHz for 2.5G mode and 80 MHz for 1G mode.

The following figure illustrates the connectivity details based on the 1G/2.5G Ethernet design.

You must ensure that the inclk0x port connects to 2.5G sampling clock and the inclk1x port connects to 1G sampling clock. The output clock port of clock control becomes the latency_sclk port. For design migration from the Intel^® Arria^® 10 devices to the Intel^® Stratix^® 10 devices, you can reuse the similar connectivity between the 1G/2.5G reconfiguration block and transceiver reset controller.

The LL 10GbE MAC Intel^® FPGA IP core for Intel^® Stratix^® 10 devices uses the same register map as LL 10GbE MAC Intel^® FPGA IP core for Intel^® Arria^® 10 devices. The Multi-rate Ethernet PHY and 10GBASE-R PHY presets also use the same register map for both Intel^® Stratix^® 10 and Intel^® Arria^® 10 designs. The LL 10GbE MAC Intel^® FPGA IP core for Intel^® Stratix^® 10 devices still supports backward compatibility with 10GbE IP with 64-bit Avalon Memory-Mapped (MM) adapter.

For LL 10GbE MAC Intel^® FPGA IP core, there are no new signals introduced for Intel^® Stratix^® 10 devices. There are new asynchronous reset status signals introduced in Intel^® Stratix^® 10 L/H-Tile Transceiver Native PHY IP Core. The differences apply to all Ethernet PHY IP cores, which include all variants of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel^® FPGA IP cores and 10GBASE-R PHY Intel^® FPGA IP core.

The following figure illustrates the connectivity of reset status signals for the Intel^® Stratix^® 10 Ethernet 10G subsystem design. This is applicable if you use either the Intel^® Stratix^® 10 L-tile/H-tile Native PHY IP core or the 1G/2.5G/5G/10G Multi-rate PHY Intel^® FPGA IP core.

There are some changes to the ATX PLL and fPLL interface signals for the Intel^® Stratix^® 10 devices compared to the Intel^® Arria^® 10 devices. If you are migrating Ethernet designs from a Intel^® Arria^® 10 device to a Intel^® Stratix^® 10 device, remove the mcgb_rst and pll_powerdown reset signals because they are not available in Intel^® Stratix^® 10.

The following figure illustrates the difference between Intel^® Stratix^® 10 L-Tile/H-Tile ATX PLL and Intel^® Arria^® 10 ATX PLL.

Another change on Intel^® Stratix^® 10 L-Tile/H-Tile Transceiver PHY is the additional 1 bit added to the reconfig_address bus, compared to the Intel^® Arria^® 10 Transceiver PHY version. The same change is required for the Multi-rate PHY as it is created by using the Native PHY as the baseline.

The following figure illustrates how to connect the reconfig_address.

Only Intel^® Quartus^® Prime Pro Edition software offers Intel^® Stratix^® 10 designs. If you are using an Intel^® Arria^® 10 Ethernet design from the Intel^® Quartus^® Prime Standard Edition, you need to migrate to Intel^® Quartus^® Prime Pro Edition version for any Intel^® Stratix^® 10 design.