AN 779: Intel FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report

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AN-779 | 2017.12.18

Intel FPGA JESD204B IP Core and AD9691 Hardware Checkout Report

The Intel^® FPGA JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP).

The JESD204B IP Core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) devices.

This report highlights the interoperability of the JESD204B IP Core with the AD9691 converter evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections describe the hardware checkout methodology and test results.

Hardware Requirements

The hardware checkout test requires the following hardware and software tools:

Intel^® Intel^® Arria^® 10 GX FPGA Development Kit
ADI AD9691 EVM
USB cable
SMA cable
Clock source card capable of generating device clock frequencies

Hardware Setup

Figure 1. Intel^® Arria^® 10 GX FPGA Development Kit Hardware SetupAn Intel^® Arria^® 10 GX FPGA Development Kit is used with the ADI AD9691 daughter card module installed to the development board’s FMC connector.

The AD9691 EVM derives power from 4.5V power adaptor.
The FPGA and ADC device clock is supplied by external clock source card through SMA connectors on AD9691 EVM.
Both FPGA and ADC device clock must be sourced from the same clock source card with two different frequencies, one for FPGA and one for ADC.

For subclass 1, FPGA generates SYSREF for the JESD204B IP as well as the AD9691 device.

The following system-level diagram shows how the different modules connect in this design.

Figure 2. System Diagram

Note: The IOPLL input reference clock is sourcing from device clock through the global clock network. Sourcing reference clock from a cascaded PLL output, global clock or core clock network might introduce additional jitter to the IOPLL and transceiver PLL output. Refer to this KDB Answer for a workaround you should apply to the IP core in your design.

In this setup, where LMF=222, the data rate of transceiver lanes is 12.5 Gbps. An external clock source card provides 312.5 MHz clock to the FPGA and 625 MHz sampling clock to AD9691 device. The Sysref is generated by the FPGA.

Hardware Checkout Methodology

The following section describes the test objectives, procedure, and the passing criteria. The test covers the following areas:

Receiver data link layer
Receiver transport layer
Descrambling
Deterministic latency (Subclass 1)

Receiver Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial frame and lane synchronization.

On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The Signal Tap Logic Analyzer tool monitors the receiver data link layer operation.

Code Group Synchronization (CGS)

Table 1. CGS Test Cases. L in the following table indicates the number of lanes.
Test Case	Objective	Description	Passing Criteria
CGS.1	Check whether sync request is de-asserted after correct reception of four successive /K/ characters.	The following signals in <ip_variant_name>_inst_phy.v are tapped: jesd204_rx_pcs_data[(L32)-1:0] jesd204_rx_pcs_data_valid[L-1:0] jesd204_rx_pcs_kchar_data[(L4)-1:0] (1) The following signals in <ip_variant_name>.v are tapped: rx_dev_sync_n jesd204_rx_int The rxlink_clk is used as the Signal Tap sampling clock. Each lane is represented by 32-bit data bus in jesd204_rx_pcs_data signal. The 32-bit data bus for is divided into 4 octets.	/K/ character or K28.5 (0xBC) is observed at each octet of the jesd204_rx_pcs_data bus. The jesd204_rx_pcs_data_valid signal is asserted to indicate data from the PCS is valid. The jesd204_rx_pcs_kchar_data signal is asserted whenever control characters like /K/, /R/, /Q/ or /A/ characters are observed. The rx_dev_sync_n signal is de-asserted after correct reception of at least four successive /K/ characters. The jesd204_rx_int signal is deasserted if there is no error.
CGS.2	Check full CGS at the receiver after correct reception of another four 8B/10B characters.	The following signals in <ip_variant_name>_inst_phy.v are tapped: jesd204_rx_pcs_errdetect[(L4)-1:0] jesd204_rx_pcs_disperr[(L4)-1:0] (1) The following signal in <ip_variant_name>.v are tapped: jesd204_rx_int The rxlink_clk is used as the Signal Tap sampling clock.	The jesd204_rx_pcs_errdetect, jesd204_rx_pcs_disperr and jesd204_rx_int signals should not be asserted during CGS phase.

Initial Frame and Lane Synchronization

Table 2. Initial Frame and Lane Synchronization Test Cases. L in the following table indicates the number of lanes.
Test Case	Objective	Description	Passing Criteria
ILA.1	Check whether the initial frame synchronization state machine enters FS_DATA state upon receiving non /K/ characters.	The following signals in <ip_variant_name>_inst_phy.v are tapped: jesd204_rx_pcs_data[(L32)-1:0] jesd204_rx_pcs_data_valid[L-1:0] jesd204_rx_pcs_kchar_data[(L4)-1:0] (2) The following signals in <ip_variant_name>.v are tapped: rx_dev_sync_n jesd204_rx_int The rxlink_clk is used as the Signal Tap sampling clock. Each lane is represented by 32-bit data bus in jesd204_rx_pcs_data. The 32-bit data bus for is divided into 4 octets.	/R/ character or K28.0 (0x1C) is observed after /K/ character at the jesd204_rx_pcs_data bus. The jesd204_rx_pcs_data_valid signal must be asserted to indicate that data from the PCS is valid. The rx_dev_sync_n and jesd204_rx_int signals are deasserted. Each multiframe in ILAS phase ends with /A/ character or K28.3 (0x7C). The jesd204_rx_pcs_kchar_data signal is asserted whenever control characters like /K/, /R/, /Q/ or /A/ characters are observed.
ILA.2	Check the JESD204B configuration parameters from ADC in second multiframe.	The following signals in <ip_variant_name>_inst_phy.v are tapped: jesd204_rx_pcs_data[(L*32)-1:0] jesd204_rx_pcs_data_valid[L-1:0] (2) The following signal in <ip_variant_name>.v is tapped: jesd204_rx_int The rxlink_clk is used as the Signal Tap sampling clock. The system console accesses the following registers: ilas_octet0 ilas_octet1 ilas_octet2 ilas_octet3 The content of 14 configuration octets in second multiframe is stored in these 32-bit registers - ilas_octet0, ilas_octet1, ilas_octet2 and ilas_octet3.	/R/ character is followed by /Q/ character or K28.4 (0x9C) at the beginning of second multiframe. The Jesd204_rx_int is deasserted if there is no error. Octets 0-13 read from these registers match with the JESD204B parameters in each test setup.
ILA.3	Check the lane alignment	The following signals in <ip_variant_name>_inst_phy.v are tapped: jesd204_rx_pcs_data[(L*32)-1:0] jesd204_rx_pcs_data_valid[L-1:0] (2) The following signals in <ip_variant_name>.v are tapped: rx_somf[3:0] dev_lane_aligned jesd204_rx_int The rxlink_clk is used as the Signal Tap sampling clock.	The dev_lane_aligned is asserted upon the last /A/ character of the ILAS is received, which is followed by the first data octet. The rx_somf marks the start of multiframe in user data phase. The jesd204_rx_int is deasserted if there is no error.

Receiver Transport Layer

To check the data integrity of the payload data stream through the RX JESD204B IP Core and transport layer, the ADC is configured to output PRBS-9 and Ramp test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP Core. The PRBS checker/Ramp checker in the FPGA fabric checks data integrity for one minute.

This figure shows the conceptual test setup for data integrity checking.

Figure 3. Data Integrity Check Using PRBS/Ramp CheckerThe Signal Tap Logic Analyzer tool monitors the operation of the RX transport layer.

Table 3. Transport Layer Test Cases
Test Case	Objective	Description	Passing Criteria
TL.1	Check the transport layer mapping using Ramp test pattern.	The following signals in altera_jesd204_transport_rx_top.sv are tapped: jesd204_rx_data_valid The following signals in jesd204b_ed.sv are tapped: data_error jesd204_rx_int The rxframe_clk is used as the Signal Tap sampling clock. The data_error signal indicates a pass or fail for the PRBS checker.	The jesd204_rx_data_valid signal is asserted. The data_error and jesd204_rx_int signals are deasserted.
TL.2	Check the transport layer mapping using PRBS-9 test pattern.	The following signals in altera_jesd204_transport_rx_top.sv are tapped: jesd204_rx_data_valid The following signals in jesd204b_ed.sv are tapped: data_error jesd204_rx_int The rxframe_clk is used as the Signal Tap sampling clock. The data_error signal indicates a pass or fail for the PRBS checker.	The jesd204_rx_data_valid signal is asserted. The data_error and jesd204_rx_int signals are deasserted.

Descrambling

The PRBS/Ramp checker at the RX transport layer checks the data integrity of descrambler. The Signal Tap Logic Analyzer tool monitors the operation of the RX transport layer.

Table 4. Descrambler Test Cases
Test Case	Objective	Description	Passing Criteria
SCR.1	Check the functionality of the descrambler using PRBS-9 test pattern.	Enable scrambler at the ADC and descrambler at the RX JESD204B IP Core. The signals that are tapped in this test case are similar to test case TL.1	The jesd204_rx_data_valid signal is asserted. The data_error and jesd204_rx_int signals are deasserted.

Deterministic Latency (Subclass 1)

The figure below shows the block diagram of deterministic latency test setup. A SYSREF generator provides a periodic SYSREF pulse for both the AD9691 and JESD204B IP Core. The SYSREF generator is running in link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.

The deterministic latency measurement block checks deterministic latency. This is done by measuring the number of link clock counts between the start of de-assertion of SYNC to the first user data output (assertion of rx_valid). Figure 2 shows the deterministic latency measurement timing diagram.

Figure 4. Deterministic Latency Test Setup Block Diagram

Figure 5. Deterministic Latency Measurement Timing Diagram

With the setup above, four test cases were defined to prove deterministic latency. By default, the JESD204B IP Core does single SYSREF detection. The SYSREF N-shot mode is enabled on the AD9691 for this deterministic measurement.

Table 5. Deterministic Latency Test Cases
Test Case	Objective	Description	Passing Criteria
DL.1	Check the FPGA SYSREF single detection.	Check that the FPGA detects the first rising edge of SYSREF pulse. Read the status of sysref_singledet (bit[2]) identifier in syncn_sysref_ctrl register at address 0x54.	The value of sysref_singledet identifier should be zero.
DL.2	Check the SYSREF capture.	Check that FPGA and ADC capture SYSREF correctly and restart the LMF counter. Both FPGA and ADC are also repetitively reset. Read the value of rbd_count (bit[10:3]) identifier in rx_status0 register at address 0x80.	If the SYSREF is captured correctly and the LMF counter restarts, for every reset, the rbd_count value should only drift a little due to word alignment.
DL.3	Check the latency from start of SYNC~ deassertion to first user data output.	Check that the latency is fixed for every FPGA and ADC reset and power cycle. Record the number of link clocks count from the start of SYNC~ deassertion to the first user data output, which is the assertion of jesd204_rx_link_valid signal.	Consistent latency from the start of SYNC~ deassertion to the assertion of jesd204_rx_link_valid signal.
DL.4	Check the data latency during user data phase.	Check that the data latency is fixed during user data phase. Observe the ramp pattern from the Signal Tap Logic Analyzer.	The ramp pattern should be in perfect shape with no distortion.

JESD204B IP Core and ADC Configurations

The JESD204B IP Core parameters (L, M and F) in this hardware checkout are natively supported by the AD9691 device's quick configuration register at address 0x570. The transceiver data rate, sampling clock frequency, and other JESD204B parameters comply with the AD9691 operating conditions.

The hardware checkout testing implements the JESD204B IP Core with the following parameter configuration.

Table 6. Parameter Configuration. Global settings for all configuration:

N = 14

N' = 16

CS = 0

CF = 0

FPGA Device Clock = 312.5 MHz (The device clock is used to clock the transceiver.)

FPGA Management Clock = 100 MHz

Character Replacement = Enabled

Data Pattern = PRBS-9, Ramp¹
LMF	HD	S	ADC Sampling Clock (MHz)	FPGA Frame Clock (MHz) ²	FPGA Link Clock (MHz)²	Lane Rate (Gbps)	DDC enabled
112	0	1	625	312.5	312.5	12.5	No
211	1	1	1250	312.5	312.5	12.5	No
212	0	2	1250	312.5	312.5	12.5	No
411	1	2	1250	156.25	156.25	6.25	No
412	0	4	1250	156.25	156.25	6.25	No
811	1	4	1250	78.125	78.125	3.125	No
812	0	8	1250	78.125	78.125	3.125	No
124	0	1	312.5	312.5	312.5	12.5	No
222	0	1	625	312.5	312.5	12.5	No
421	1	1	1250	312.5	312.5	12.5	No
422	0	2	1250	312.5	312.5	12.5	No
821	1	2	1250	156.25	156.25	6.25	No
822	0	4	1250	156.25	156.25	6.25	No
148	0	1	312.5	156.25	312.5	12.5	Yes
244	0	1	625	312.5	312.5	12.5	Yes
442	0	1	1250	312.5	312.5	12.5	Yes
841	1	1	1250	156.25	156.25	6.25	Yes
842	0	2	1250	156.25	156.25	6.25	Yes
288	0	1	312.5	156.25	312.5	12.5	Yes
484	0	1	625	312.5	312.5	12.5	Yes
882	0	1	1250	312.5	312.5	12.5	Yes

¹ Ramp pattern is used in deterministic latency measurement test cases DL.1, DL.2, DL.3 and DL.4 only.

² The frame clock and link clock is derived from the device clock using an internal PLL.

Test Results

The following table contains the possible results and their definition.

Table 7. Results Definition
Result	Definition
PASS	The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments	The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations only a portion of the testing was performed.
FAIL	The DUT was observed to exhibit non-conformant behavior.
Warning	The DUT was observed to exhibit behavior that is not recommended.
Refer to comments	From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock and SYSREF frequencies.

Table 8. Results for Test Cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1
Test	L	M	F	Subclass	SCR	K	Data rate (Gbps)	ADC Sampling Clock (MHz)	Link Clock (MHz)	Result
1	1	1	2	1	0	16	12.5	625	312.5	PASS
2	1	1	2	1	1	16	12.5	625	312.5	PASS
3	1	1	2	1	0	32	12.5	625	312.5	PASS
4	1	1	2	1	1	32	12.5	625	312.5	PASS
5	2	1	1	1	0	20	12.5	1250	312.5	PASS
6	2	1	1	1	1	20	12.5	1250	312.5	PASS
7	2	1	1	1	0	32	12.5	1250	312.5	PASS
8	2	1	1	1	1	32	12.5	1250	312.5	PASS
9	2	1	2	1	0	16	12.5	1250	312.5	PASS
10	2	1	2	1	1	16	12.5	1250	312.5	PASS
11	2	1	2	1	0	32	12.5	1250	312.5	PASS
12	2	1	2	1	1	32	12.5	1250	312.5	PASS
13	4	1	1	1	0	20	6.25	1250	156.25	PASS
14	4	1	1	1	1	20	6.25	1250	156.25	PASS
15	4	1	1	1	0	32	6.25	1250	156.25	PASS
16	4	1	1	1	1	32	6.25	1250	156.25	PASS
17	4	1	2	1	0	16	6.25	1250	156.25	PASS
18	4	1	2	1	1	16	6.25	1250	156.25	PASS
19	4	1	2	1	0	32	6.25	1250	156.25	PASS
20	4	1	2	1	1	32	6.25	1250	156.25	PASS
21	8	1	1	1	0	20	3.125	1250	78.125	PASS
22	8	1	1	1	1	20	3.125	1250	78.125	PASS
23	8	1	1	1	0	32	3.125	1250	78.125	PASS
24	8	1	1	1	1	32	3.125	1250	78.125	PASS
25	8	1	2	1	0	16	3.125	1250	78.125	PASS
26	8	1	2	1	1	16	3.125	1250	78.125	PASS
27	8	1	2	1	0	32	3.125	1250	78.125	PASS
28	8	1	2	1	1	32	3.125	1250	78.125	PASS
29	1	2	4	1	0	16	12.5	312.5	312.5	PASS
30	1	2	4	1	1	16	12.5	312.5	312.5	PASS
31	1	2	4	1	0	32	12.5	312.5	312.5	PASS
32	1	2	4	1	1	32	12.5	312.5	312.5	PASS
33	2	2	2	1	0	16	12.5	625	312.5	PASS
34	2	2	2	1	1	16	12.5	625	312.5	PASS
35	2	2	2	1	0	32	12.5	625	312.5	PASS
36	2	2	2	1	1	32	12.5	625	312.5	PASS
37	4	2	1	1	0	20	12.5	1250	312.5	PASS
38	4	2	1	1	1	20	12.5	1250	312.5	PASS
39	4	2	1	1	0	32	12.5	1250	312.5	PASS
40	4	2	1	1	1	32	12.5	1250	312.5	PASS
41	4	2	2	1	0	16	12.5	1250	312.5	PASS
42	4	2	2	1	1	16	12.5	1250	312.5	PASS
43	4	2	2	1	0	32	12.5	1250	312.5	PASS
44	4	2	2	1	1	32	12.5	1250	312.5	PASS
45	8	2	1	1	0	20	6.25	1250	156.25	PASS
46	8	2	1	1	1	20	6.25	1250	156.25	PASS
47	8	2	1	1	0	32	6.25	1250	156.25	PASS
48	8	2	1	1	1	32	6.25	1250	156.25	PASS
49	8	2	2	1	0	16	6.25	1250	156.25	PASS
50	8	2	2	1	1	16	6.25	1250	156.25	PASS
51	8	2	2	1	0	32	6.25	1250	156.25	PASS
52	8	2	2	1	1	32	6.25	1250	156.25	PASS
53	1	4	8	1	0	16	12.5	312.5	312.5	PASS
54	1	4	8	1	1	16	12.5	312.5	312.5	PASS
55	1	4	8	1	0	32	12.5	312.5	312.5	PASS
56	1	4	8	1	1	32	12.5	312.5	312.5	PASS
57	2	4	4	1	0	16	12.5	625	312.5	PASS
58	2	4	4	1	1	16	12.5	625	312.5	PASS
59	2	4	4	1	0	32	12.5	625	312.5	PASS
60	2	4	4	1	1	32	12.5	625	312.5	PASS
61	4	4	2	1	0	16	12.5	1250	312.5	PASS
62	4	4	2	1	1	16	12.5	1250	312.5	PASS
63	4	4	2	1	0	32	12.5	1250	312.5	PASS
64	4	4	2	1	1	32	12.5	1250	312.5	PASS
65	8	4	1	1	0	20	6.25	1250	156.25	PASS
66	8	4	1	1	1	20	6.25	1250	156.25	PASS
67	8	4	1	1	0	32	6.25	1250	156.25	PASS
68	8	4	1	1	1	32	6.25	1250	156.25	PASS
69	8	4	2	1	0	16	6.25	1250	156.25	PASS
70	8	4	2	1	1	16	6.25	1250	156.25	PASS
71	8	4	2	1	0	32	6.25	1250	156.25	PASS
72	8	4	2	1	1	32	6.25	1250	156.25	PASS
73	2	8	8	1	0	16	12.5	312.5	312.5	PASS with comments
74	2	8	8	1	1	16	12.5	312.5	312.5	PASS with comments
75	2	8	8	1	0	32	12.5	312.5	312.5	PASS with comments
76	2	8	8	1	1	32	12.5	312.5	312.5	PASS with comments
77	4	8	4	1	0	16	12.5	625	312.5	PASS with comments
78	4	8	4	1	1	16	12.5	625	312.5	PASS with comments
79	4	8	4	1	0	32	12.5	625	312.5	PASS with comments
80	4	8	4	1	1	32	12.5	625	312.5	PASS with comments
81	8	8	2	1	0	16	12.5	1250	312.5	PASS with comments
82	8	8	2	1	1	16	12.5	1250	312.5	PASS with comments
83	8	8	2	1	0	32	12.5	1250	312.5	PASS with comments
84	8	8	2	1	1	32	12.5	1250	312.5	PASS with comments

The following table shows the results for test cases DL.1, DL.2, DL.3 and DL.4 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock and SYSREF frequencies.

Table 9. Results for Deterministic Latency Test
Test	L	M	F	Subclass	K	Data rate (Gbps)	Sampling Clock (MHz)	Link Clock (MHz)	Result	Latency (Link Clock Cycles)
DL.1	1	1	2	1	16/32	12.5	625	312.5	PASS	For K=16 DL= 75 For K=32 DL= 115
DL.2	1	1	2	1	16/32	12.5	625	312.5	PASS
DL.3	1	1	2	1	16/32	12.5	625	312.5	PASS
DL.4	1	1	2	1	16/32	12.5	625	312.5	PASS
DL.1	2	1	1	1	20/32	12.5	1250	312.5	PASS	For K=20 DL= 53 For K=32 DL= 67
DL.2	2	1	1	1	20/32	12.5	1250	312.5	PASS
DL.3	2	1	1	1	20/32	12.5	1250	312.5	PASS
DL.4	2	1	1	1	20/32	12.5	1250	312.5	PASS
DL.1	2	1	2	1	16/32	12.5	1250	312.5	PASS	For K=16 DL=67 For K=32 DL=99
DL.2	2	1	2	1	16/32	12.5	1250	312.5	PASS
DL.3	2	1	2	1	16/32	12.5	1250	312.5	PASS
DL.4	2	1	2	1	16/32	12.5	1250	312.5	PASS
DL.1	4	1	1	1	20/32	6.25	1250	156.25	PASS	For K=20 DL=53 For K=32 DL=67
DL.2	4	1	1	1	20/32	6.25	1250	156.25	PASS
DL.3	4	1	1	1	20/32	6.25	1250	156.25	PASS
DL.4	4	1	1	1	20/32	6.25	1250	156.25	PASS
DL.1	4	1	2	1	16/32	6.25	1250	156.25	PASS	For K=16 DL=67 For K=32 DL=99
DL.2	4	1	2	1	16/32	6.25	1250	156.25	PASS
DL.3	4	1	2	1	16/32	6.25	1250	156.25	PASS
DL.4	4	1	2	1	16/32	6.25	1250	156.25	PASS
DL.1	8	1	1	1	20/32	3.125	1250	78.125	PASS	For K=20 DL=53 For K=32 DL=67
DL.2	8	1	1	1	20/32	3.125	1250	78.125	PASS
DL.3	8	1	1	1	20/32	3.125	1250	78.125	PASS
DL.4	8	1	1	1	20/32	3.125	1250	78.125	PASS
DL.1	8	1	2	1	16/32	3.125	1250	78.125	PASS	For K=16 DL=67 For K=32 DL=115
DL.2	8	1	2	1	16/32	3.125	1250	78.125	PASS
DL.3	8	1	2	1	16/32	3.125	1250	78.125	PASS
DL.4	8	1	2	1	16/32	3.125	1250	78.125	PASS
DL.1	1	2	4	1	16/32	12.5	312.5	312.5	PASS	For K=16 DL=99 For K=32 DL=195
DL.2	1	2	4	1	16/32	12.5	312.5	312.5	PASS
DL.3	1	2	4	1	16/32	12.5	312.5	312.5	PASS
DL.4	1	2	4	1	16/32	12.5	312.5	312.5	PASS
DL.1	2	2	2	1	16/32	12.5	625	312.5	PASS	For K=16 DL=67 For K=32 DL=115
DL.2	2	2	2	1	16/32	12.5	625	312.5	PASS
DL.3	2	2	2	1	16/32	12.5	625	312.5	PASS
DL.4	2	2	2	1	16/32	12.5	625	312.5	PASS
DL.1	4	2	1	1	20/32	12.5	1250	312.5	PASS	For K=20 DL=56 For K=32 DL=67
DL.2	4	2	1	1	20/32	12.5	1250	312.5	PASS
DL.3	4	2	1	1	20/32	12.5	1250	312.5	PASS
DL.4	4	2	1	1	20/32	12.5	1250	312.5	PASS
DL.1	4	2	2	1	16/32	12.5	1250	312.5	PASS	For K=16 DL=67 For K=32 DL=99
DL.2	4	2	2	1	16/32	12.5	1250	312.5	PASS
DL.3	4	2	2	1	16/32	12.5	1250	312.5	PASS
DL.4	4	2	2	1	16/32	12.5	1250	312.5	PASS
DL.1	8	2	1	1	20/32	6.25	1250	156.25	PASS	For K=20 DL=52 For K=32 DL=67
DL.2	8	2	1	1	20/32	6.25	1250	156.25	PASS
DL.3	8	2	1	1	20/32	6.25	1250	156.25	PASS
DL.4	8	2	1	1	20/32	6.25	1250	156.25	PASS
DL.1	8	2	2	1	16/32	6.25	1250	156.25	PASS	For K=16 DL=67 For K=32 DL=99
DL.2	8	2	2	1	16/32	6.25	1250	156.25	PASS
DL.3	8	2	2	1	16/32	6.25	1250	156.25	PASS
DL.4	8	2	2	1	16/32	6.25	1250	156.25	PASS
DL.1	1	4	8	1	16/32	12.5	312.5	312.5	PASS	For K=16 DL=195 For K=32 DL=67
DL.2	1	4	8	1	16/32	12.5	312.5	312.5	PASS
DL.3	1	4	8	1	16/32	12.5	312.5	312.5	PASS
DL.4	1	4	8	1	16/32	12.5	312.5	312.5	PASS
DL.1	2	4	4	1	16/32	12.5	625	312.5	PASS	For K=16 DL=115 For K=32 DL=195
DL.2	2	4	4	1	16/32	12.5	625	312.5	PASS
DL.3	2	4	4	1	16/32	12.5	625	312.5	PASS
DL.4	2	4	4	1	16/32	12.5	625	312.5	PASS
DL.1	4	4	2	1	16/32	12.5	1250	312.5	PASS	For K=16 DL=67 For K=32 DL=99
DL.2	4	4	2	1	16/32	12.5	1250	312.5	PASS
DL.3	4	4	2	1	16/32	12.5	1250	312.5	PASS
DL.4	4	4	2	1	16/32	12.5	1250	312.5	PASS
DL.1	8	4	1	1	20/32	6.25	1250	156.25	PASS	For K=20 DL=51 For K=32 DL=67
DL.2	8	4	1	1	20/32	6.25	1250	156.25	PASS
DL.3	8	4	1	1	20/32	6.25	1250	156.25	PASS
DL.4	8	4	1	1	20/32	6.25	1250	156.25	PASS
DL.1	8	4	2	1	16/32	6.25	1250	156.25	PASS	For K=16 DL=67 For K=32 DL=99
DL.2	8	4	2	1	16/32	6.25	1250	156.25	PASS
DL.3	8	4	2	1	16/32	6.25	1250	156.25	PASS
DL.4	8	4	2	1	16/32	6.25	1250	156.25	PASS
DL.1	2	8	8	1	16/32	12.5	312.5	312.5	PASS	For K=16 DL=195 For K=32 DL=67
DL.2	2	8	8	1	16/32	12.5	312.5	312.5	PASS
DL.3	2	8	8	1	16/32	12.5	312.5	312.5	PASS
DL.4	2	8	8	1	16/32	12.5	312.5	312.5	PASS with comments
DL.1	4	8	4	1	16/32	12.5	625	312.5	PASS	For K=16 DL=115 For K=32 DL=195
DL.2	4	8	4	1	16/32	12.5	625	312.5	PASS
DL.3	4	8	4	1	16/32	12.5	625	312.5	PASS
DL.4	4	8	4	1	16/32	12.5	625	312.5	PASS with comments
DL.1	8	8	2	1	16/32	12.5	1250	312.5	PASS	For K=16 DL=67 For K=32 DL=99
DL.2	8	8	2	1	16/32	12.5	1250	312.5	PASS
DL.3	8	8	2	1	16/32	12.5	1250	312.5	PASS
DL.4	8	8	2	1	16/32	12.5	1250	312.5	PASS with comments

The following figure shows the Signal Tap waveform of the clock count from the deassertion of SYNC~ to the assertion of the jesd204_rx_link_valid signal, the first output of the ramp test pattern (DL.3 test case). The clock count measures the first user data output latency.

Figure 6. Deterministic Latency Measurement Ramp Test Pattern Diagram

Test Result Comments

In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until user data phase. No data integrity issue is observed by the PRBS and Ramp checker.

In deterministic measurement test case DL.3, the link clock count in the FPGA depends on the board layout and the LMFC offset value set in the ADC register. The link clock count can vary by only one link clock when the FPGA and ADC are reset or power cycled. The link clock variation in the deterministic latency measurement is caused by word alignment, where the control characters fall into the next cycle of data sometime after realignment. This makes the duration of ILAS phase longer by one link clock sometimes after reset or power cycle.

For modes with 8 converters (M=8), the result is updated with ‘PASS with comments’ because the test cases TL.1, TL.2 and DL.4 are validated only for first 7 converters due to known limitation of ADC. The ADC does not output RAMP/PRBS test-pattern for the 8th converter and this is documented in the ADC’s datasheet in TEST MODES section on page 54.

For a few modes, in order to avoid lane de-skew error or achieve deterministic latency, RBD offset and LMFC offset registers had to be programmed. The modes and the corresponding values used are tabled below.

Table 10. Mode (LMF)csr_lmfc_offsetcsr_rbd_offset
Mode (LMF)	csr_lmfc_offset	csr_rbd_offset
211-K20	2	0
421-K20	0	2
821-K20	0	1
411-K20	2	0
841-K20	0	2

Document Revision History for AN 779: Intel FPGA JESD204B IP Core and AD9691 Hardware Checkout Report

Date	Version	Changes
December 2017	2017.12.18	Renamed the document as AN 779: Intel FPGA JESD204B IP Core and AD9691 Hardware Checkout Report. Added a note to clarify that the IOPLL input reference clock is sourcing from device clock through global clock network in the Hardware Setup topic. Updated for latest branding standards.
May 2017	2017.05.08	Rebranded as Intel.
October 2016	2016.10.31	Initial release.