The Altera^® JESD204B IP core is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to or from the FPGA devices.

The JESD204B IP core is part of the IP Catalog library, which is distributed with the software and downloadable from the Altera^® website.

This reference design demonstrates the JESD204B IP core operating as part of a system that includes:

• Altera JESD204B transport layer (assembler and deassembler)
• test pattern generator and checker
• core PLL
• Serial Parallel Interface (SPI) – Master module
• reset sequencer
• various dynamic reconfiguration controllers
• ARM^® hard processor subsystem (HPS) as the control unit

The key feature of this reference design is the software-based control flow that utilizes the ARM^® HPS control unit.

The reference design utilizes the Arria V SoC Development Kit to interoperate with the Analog Devices (ADI) AD9680 ADC daughter card that connects to the development board.

This reference design is implemented on the Arria V SoC development board interoperating with the ADI AD9680 ADC converter card.

The reference design consists of these components and sub components:

• Qsys system:
  • ARM^® HPS control unit and various processor peripherals
  • JESD204B subsystem
  • SPI master module
• Top level HDL:
  • Core PLL
  • In-system source and probes (ISSP)
  • Edge detectors
  • Altera transport layer (assembler and deassembler)
  • Test pattern generator and checker

• ARM^® HPS control unit—generates a one-shot SYSREF pulse for the JESD204B IP core and the AD9680 module (for Subclass 1 mode compliance).
• device_clk (153.6 MHz) clock signal sourced from the AD9516 external clock module—acts as the reference clock for the on-chip core PLL and transceiver PHY PLL.
• Core PLL module—generates the link clock (link_clk) and frame clock (frame_clk).
• Oscillator on-board the Arria V SoC development board—supplies a 50 MHz clock (fpga_clk_50) to clock the control plane.
• Altera In-System Source and Probes (ISSP) module instantiated in the top level HDL—generates the following resets for the ARM HPS control unit:
  • Cold reset
  • Warm reset
  • Debug reset

• Edge detect module instantiated in the top level HDL—shapes the reset pulses generated by the ISSP module to meet the ARM HPS reset pulse width requirements.
• AD9516 external clock module
  • Supplies a 614.4 MHz clock to the ADCs on the AD9680 module via an SMA connector.
  • Supplies a 153.6 MHz reference clock to the FPGA via an SMA connector on the AD9680 module. The reference clock is passed through from the AD9680 module to the FPGA via the FMC connector.
  • You can replace this module with any external clock module that supplies a 614.4 MHz and 153.6 MHz reference clock.
• AD9680 module
  • Configuration of the AD9680 converter parameters is through a 4-wire SPI master module via FMC connector.
  • Configured to transmit on 4 high-speed transceiver lanes (L=4) to the FPGA.
  • Each lane is configured to 6.144 Gbps data rate.
  • Passes through the FPGA reference clock (device_clk) from the AD9516 clock module to the FPGA via the FMC connector.

This reference design uses the following hardware and software tools:

• Arria V SoC development kit
• ADI AD9680 ADC converter card
• ADI AD9516 clock module
• Quartus^® Prime software version 15.1
• Altera SoC Embedded Design Suite (EDS) with ARM^® DS-5 Altera Edition tool

1. Install the ADI AD9680 converter card module to the FMC port A (J26) on the Arria V SoC development board.
2. Connect the USB cable to the USB-Blaster^® II connector on the development board.
3. Connect the power adapter shipped with the development board to the power supply jack (J34).
4. Connect the AD9516 power adapter to the power supply jack on the AD9516 clock module card.
5. Connect the USB cable from your workstation to the USB connector on the AD9516 card.
6. Connect the AD9516 clock module OUT0 SMA connector (J0A) to the CLKIN SMA connector (J801) on the AD9680 card.
7. Connect the AD9516 clock module OUT8 SMA connector (J8A) to the Refclk to FPGA SMA connector (J804) on the AD9680 card.
8. Turn on the power for the AD9516 clock module card.
9. Configure the clock settings of the AD9516 to output 614.4 MHz clock for the ADCs at OUT0 SMA connector and 153.6 MHz for the FPGA at OUT8 SMA connector. Refer to the AD9516 documentation for more information on configuring the AD9516 clock module.
10. Turn on the power for the Arria V SoC development board.

The hardware system is now ready for programming.

1. Extract the reference design from the reference design ZIP file (jesd204b_av_soc_ref_design.zip).
2. Launch the Quartus^® Prime software.
3. On the File menu, click Open Project.
4. Navigate to your project directory and select the Quartus project archive file (jesd204b_ed.qar). Click Open.
5. In the Restore Archived Project window, verify that the archive file name is jesd204b_ed.qar and set the destination folder to the destination folder of your choice. Click OK. The Quartus project opens in the Quartus window.
6. To compile the HDL, navigate to the Processing menu and select Start Compilation. The Quartus software compiles the design and indicates the compilation status in the Tasks panel.
7. After compilation is done, you are ready to program the FPGA device with the programming file. Navigate to the Tools menu and click Programmer.
8. In the Programmer window, click Add File.
9. In the Select Programming File window, navigate to <your project directory> /output_files/jesd204b_ed.sof and click Open.
10. Verify that all the hardware setup options are set correctly to your system configurations.
11. Click Start to download the file into the Arria V SoC device on the development board. Alternatively, if you want to use the pre-generated golden programming file, skip the Quartus compilation in step 6. In step 9, select <your project directory> output_files/jesd204b_ed_golden.sof and proceed accordingly.

After programming the Arria V SoC device on the development board, the system needs to be initialized via software before the JESD204B link can be fully active.

1. Create a software workspace in a project directory of your choice. For ease of reference, this document will assume the software workspace name of <your project directory> /software.
2. Launch the SoC EDS ARM^® DS-5 Altera Edition tool.
3. In the Select a workspace dialog box, navigate to the software workspace, <your project directory> /software and click OK.
4. Import the software archive project into your workspace. On the File menu, click Import.
5. In the Import/Select window, select General > Existing Projects into Workspace and click Next >.
6. In the Import/Import Projects window, check the Select archive file radio button.
7. Browse to the software archive project location, select the archive project file, jesd204b_soc_baremetal_gnu.tar.gz and click OK. The software archive project file is in the location where you unzipped the reference design, jesd204b_av_soc_ref_design.zip.
8. Verify that the jesd204b_soc_baremetal_gnu check box is checked in the Projects panel and click Finish. The ARM^® DS-5 tool restores the archived software project into your workspace.
9. In the Project Explorer tab of the main Eclipse window, expand the jesd204b_soc_baremetal_gnu project file list and verify that you see all the files listed in the Reference Design Files section.
10. To compile the source code, right-click on the jesd204b_soc_baremetal_gnu project in the Project Explorer tab and select Build Project. This action executes the software build project Makefile.
11. When recompiling the source code after the first compile, right-click on the jesd204b_soc_baremetal_gnu project and select Clean Project before building the project. This clears the project workspace of object files and other project executables from the previous project build.
12. Whenever you add or remove any *.c source files from the project, in addition to adding or removing the file from the Project Explorer window, you must update the source file list in the software build project Makefile accordingly. To update the source file list in the Makefile, double-click the Makefile file under the jesd204b_soc_baremetal_gnu project in the Project Explorer tab. In the Makefile editor window, locate the 'EXAMPLE_SRC' variable and add or remove your *.c source file from the list. Save the file and proceed to build the project.
13. View the build project log in the Console tab and verify that there are no errors during the build project operation.
14. To download the project executable file to the ARM^® HPS and execute the code in semi-hosting debug mode, right-click on the jesd204b_soc_baremetal_gnu project in the Project Explorer tab and select Debug As > Debug Configurations.
15. In the Debug Configurations window, on the left panel, select DS-5 Debugger > jesd204b_soc_baremetal_gnu. On the right panel, under the Connection tab, in the Select target panel, select Arria V SoC > Bare Metal Debug > Debug Cortex-A9_0. Ensure that all the other connections settings in the Connection tab are set according to your system configurations.
16. Click Debug. The tool downloads the executable code onto the ARM^® HPS and launches the Debugger interface.
17. Execution of the code is halted on the first executable line of the main.c code. To continue execution without interruption until the end of the code, click the Continue button in the Debug Control window. To step through the code line by line, use the stepping buttons in the Debug Control window.

The App Console window is the main user interface portal that you can view printed messages and enter commands to the main execution code.

The main execution code executes the JESD204B link initialization sequence and prints a command prompt for you to enter commands to the ARM^® HPS. View the printed messages from the JESD204B link initialization sequence in the App Console window. Verify that the link is initialized successfully and the TX/RX status registers display the expected values. Tables below describe the expected values of the link status register report.

The code also reports the status of the pattern checker comparison. Any pattern checker errors that occur during the initialization period is flagged to the console window. Verify that the console displays this message to indicate no pattern checker errors were detected:

INFO: No pattern checker error detected on link 0

The reference design consists of the following components:

• Qsys system
  • ARM HPS control unit and supporting processor peripherals
  • JESD204B subsystem
• Core PLL
• Assembler and deassembler (in the transport layer)
• Test pattern generator
• Test pattern checker

The top level Qsys system (jesd204b_ed_soc.qsys) instantiates the following key components:

• ARM^® HPS control unit and supporting processor peripherals
• JESD204B subsystem

The main data path flows through the JESD204B subsystem. In this reference design, the JESD204B IP core is configured in duplex mode with both TX and RX data paths. On the TX data path, user data flows from the transport layer through the JESD204B IP core base module via a 32-bit per transceiver lane Avalon^® Streaming (Avalon-ST) interface and out as serial data to either the external converters or the RX data path in internal serial loopback mode via the JESD204B IP core PHY module. On the RX data path, serial data flows from the external converters (or from the TX data path, in internal serial loopback mode) to the JESD204B IP core PHY module and out from the JESD204B IP core base module to the transport layer via a 32-bit per transceiver lane Avalon-ST interface. Since the system is configured to 4 transceiver lanes (L=4), the total bit width of the Avalon-ST interface for both the TX and RX data paths is 128 bits.

The control path is centered on the ARM^® HPS control unit that connects to various peripherals via the Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) bus protocol. Altera processor peripherals primarily use the Avalon^® Memory-Mapped (Avalon-MM) protocol for bus connectivity. The Qsys tool automatically and seamlessly translates between the two protocols such that you can connect an Avalon-MM peripheral to the ARM^® HPS interface directly. An Avalon-MM bridge module provides a single memory-mapped interface between the ARM^® HPS lightweight HPS-to-FPGA bridge AXI interface and Avalon-MM peripherals implemented in the FPGA core fabric.

A secondary control path from the SPI master module links to the SPI configuration interface of the external converters via a 4-wire SPI interconnect. The configuration of the external converters is done by the ARM^® HPS control unit writing configuration data to the SPI master module. The SPI master module handles the serial transfer of data to the SPI interface on the converter end via the 4-wire SPI interconnect.

To view the top level Qsys system in Qsys:

1. Launch the Quartus^® Prime software.
2. On the File menu, click Open.
3. Browse and select the jesd204b_ed_soc.qsys file located in the project directory.
4. Click Open to view the Qsys system.

This section describes the following components:

• ARM^® HPS control unit
• On-chip memory—provides general purpose data memory to the ARM^® HPS
• System ID (sysid)—a simple read-only device that provides the system with a unique identifier. The ARM^® HPS uses this module to verify that an executable program is compiled targeting the actual hardware image configured in the target FPGA.
• JTAG UART—transmits information between the ARM^® HPS and user console
• External ports parallel I/O (PIO)—provides memory-mapped access to/from the ARM^® HPS from/to external ports. There are three external port PIO modules in the system:
  • fpga_dipsw_pio—4-bit input from on-board DIP switches
  • fpga_button_pio—4-bit input from on-board push buttons
  • fpga_led_pio—4-bit output to on-board LEDs

• FPGA core control and status parallel I/O (PIO)
• SPI master module
• Interrupt latency counter (ILC)—measures in clock cycles the time taken from the moment an interrupt request (IRQ) signal is asserted until the interrupt service routine (ISR) begins
• Avalon-MM bridge—provides single memory-mapped interface between the ARM^® HPS lightweight HPS-to-FPGA bridge AXI interface and Avalon-MM peripherals in the FPGA core
• JTAG-to-Avalon-Master bridge—facilitates System Console interface for debug purposes

The ARM^® HPS is configured with the following input resets enabled:

• Cold reset
• Warm reset
• Debug reset

The reset pulses to the ARM^® HPS are generated by the Altera In-System Sources and Probes (ISSP) module that is instantiated in the top level HDL file. The reset pulses are shaped by the edge detector unit (also instantiated in the top level HDL file) to meet the ARM^® HPS reset pulse specifications. The ARM^® HPS in turn generates an output reset signal to the FPGA core fabric via the HPS-to-FPGA external reset port (h2f_reset) and is used by the JESD204B subsystem reset sequencer.

The ARM^® HPS communicates with the FPGA core fabric via a set of AXI bridges that are part of the HPS:

• HPS-to-FPGA bridge—64-bit master interface that interfaces to the on-chip memory
• FPGA-to-HPS bridge—64-bit general purpose slave interface from the FPGA core fabric to ARM^® HPS
• Lightweight HPS-to-FPGA bridge—32-bit master interface that connects to all Avalon-MM peripherals that are implemented in the FPGA core fabric

The SDRAM interface protocol setting is configured to DDR3 operating at 533 MHz.

The following peripherals have their interrupt request (IRQ) output ports connected to the IRQ input port of the ARM^® HPS (f2h_irq0):

• Push button input PIO module
• DIP switch input PIO module
• SPI master module
• JESD204B IP core TX base layer
• JESD204B IP core RX base layer
• Reset sequencer

The FPGA core control and status PIO modules provide general purpose I/O access to and from the ARM^® HPS for elements inside the FPGA core fabric. The FPGA control PIO is a 32-bit output signal from the ARM^® HPS to the FPGA core fabric. The FPGA status PIO is a 32-bit input signal from the FPGA core fabric to the ARM^® HPS. The signal connectivity is set at the top level HDL file. The tables below describe the signal connectivity for the FPGA control and status registers.

The SPI master module is a 4-wire, 24-bit width interface that uses the SPI protocol to facilitate the configuration of external converters (for example, ADC, DAC, and external clock modules) via a structured register space provided inside the converter device. The SPI master module connects to the ARM^® HPS via the Avalon-MM bridge. The ARM^® HPS sends the configuration instructions and data to external converters during the external converter configuration operation. The software instructions to execute external converter configuration via the SPI interface is described in the Reference Design Software section.

The JESD204B subsystem Qsys project (jesd204b_system.qsys) instantiates these modules:

• JESD204B IP core configured in duplex (with TX and RX data paths), non-bonded mode
• Reset sequencer
• Transceiver PHY reset controller
• Avalon-MM bridge

The grouping of modules into a single Qsys subsystem project facilitates easy implementation of multi-link capabilities. For every link that you implement, a jesd204b_system.qsys project is instantiated in the top level Qsys project and assigned an address as described in the Top Level Address Map section. You can reset and dynamically reconfigure each link independently.

The JESD204B IP core is configured in duplex (with TX and RX data paths), non-bonded mode with the following parameter configuration:

The JESD204B IP base core connects to the ARM HPS via the Avalon-MM bridge. There are two separate Avalon-MM ports for the JESD204B IP core:

• Base core TX data path—for dynamic reconfiguration of the TX CSR parameters.
• Base core RX data path—for dynamic reconfiguration of the RX CSR parameters.

The ARM^® HPS writes to the JESD204B IP core CSR during a dynamic reconfiguration operation. The software instructions to execute dynamic reconfiguration of the JESD204B IP core are described in the User Commands section.

To customize the JESD204B IP core parameters to meet your specifications, follow the instructions in the Modifying JESD204B IP Core Parameters section.

The reset sequencer is a standard Qsys component in the IP Catalog standard library. The reset sequencer generates the following system resets to reset various modules in the system:

• Core PLL reset—resets the core PLL.
• Transceiver reset—resets the JESD204B IP core PHY module.
• TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core CSRs.
• TX/RX link reset—resets the TX/RX JESD204B IP core base module and transport layer.
• TX/RX frame reset—resets the TX/RX transport layer, downstream modules.

The reset sequencer has hard and soft reset options. The hard reset port connects to the ARM^® HPS-generated FPGA reset output signal (h2f_reset). The ARM^® HPS executes a soft reset by issuing the reset command to the Avalon-MM interface of the reset sequencer. When you assert a hard reset or issue the full sequence reset command, the reset sequencer cycles through all the various module resets based on a pre-set sequence. The figure below illustrates the sequence and also shows how the reset sequencer output ports correspond to the modules that are being reset.

The transceiver PHY reset controller is a standard Qsys component in the IP Catalog standard library. This module takes the transceiver PHY reset output from the reset sequencer and generates the proper analog and digital reset sequencing for the transceiver PHY module.

All the Avalon-MM peripherals in the JESD204B subsystem connect via the Avalon-MM interconnect to a single Avalon-MM bridge. This bridge is the single interface for Avalon-MM communications into and out of the subsystem. This Avalon-MM bridge connects to the main Avalon-MM bridge in the top level Qsys system to connect to the ARM^® HPS control unit.

You can access the address map of the peripherals in the JESD204B subsystem by clicking on the Address Map tab in the Qsys window when the jesd204b_system.qsys project is open.

The core PLL generates clocks for the FPGA core fabric. The core PLL uses the device_clk external clock signal as its reference clock to generate two derivative clocks from a single VCO:

• Link clock—from output C0
• Frame clock—from output C1

For the frame clock, when F=1 and F=2, the resulting frame clock value can easily exceed the capability of the core PLL to generate and close timing. The top level HDL file (jesd204b_ed.sv) defines the frame clock division factor parameters, F1_FRAMECLK_DIV (for cases with F = 1) and F2_FRAMECLK_DIV (for cases with F = 2). This factor enables the transport layer and test pattern generator to operate at a divided factor of the required frame clock rate by widening the data width accordingly. For this reference design, the F1_FRAMECLK_DIV is set to 4 and F2_FRAMECLK_DIV is set to 2. Based on the default settings of the reference design, the frame clock for a serial data rate of 6.144 Gbps and F = 1 equals to:

(6144/(10 × 1)) / F1_FRAMECLK_DIV = 614.4 / 4 = 153.6 MHz

The transport layer in the reference design consists of an assembler at the TX path and a deassembler at the RX path. The transport layer for both the TX and RX path is implemented in the top level HDL file, not in the Qsys project.

The transport layer provides the following services to the application layer (AL) and the link layer:

• The assembler at the TX path:
  • maps the conversion samples from the AL (through the Avalon-ST interface) to a specific format of non-scrambled octets, before streaming them to the DLL.
  • reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during TX data streaming.

• The deassembler at the RX path:
  • maps the descrambled octets from the DLL to a specific conversion sample format before streaming them to the AL (through the Avalon-ST interface).
  • reports AL error to the DLL if it encounters a specific error condition on the Avalon-ST interface during RX data streaming.

The transport layer has many customization options and you can modify the transport layer HDL code to customize it to your specifications. Furthermore, for certain parameters like L, F, and N, the transport layer shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core will affect the transport layer in the same way.

The software instructions to execute dynamic reconfiguration of the transport layer are described in the User Commands section.

The test pattern generator generates one of three patterns—parallel PRBS, alternate checkerboard, or ramp wave—and sends the pattern along to the transport layer during test mode. The test pattern generator has many customization options and you can modify the test pattern generator HDL code to customize it to your specifications. Furthermore, for certain parameters like M, S, N, and test mode, the test pattern generator shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core will affect the test pattern generator in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR. The software instructions to execute dynamic reconfiguration of the test pattern generator are described in the User Commands section.

The test pattern checker checks one of three patterns—parallel PRBS, alternate checkerboard, or ramp wave—from the transport layer during test mode. The test pattern checker has many customization options and you can modify the test pattern checker HDL code to customize it to your specifications. Furthermore, for certain parameters like M, S, N, and test mode, the test pattern checker shares the CSR values with the JESD204B IP core. This means that any dynamic reconfiguration operation that affects those values for the JESD204B IP core will affect the test pattern checker in the same way. This includes the pattern type (PRBS, alternate checkerboard, ramp) which is controlled by the test mode CSR. The software instructions to execute dynamic reconfiguration of the test pattern checker are described in the User Commands section.

The key feature of the reference design with ARM^® HPS control unit is the ability to control certain aspects of the JESD204B system using a C-based, software control flow. Some of the capabilities enabled by the software control flow are:

• System reset—ability to reset individual modules (for example, core PLL, transceiver PHY, JESD204B base Avalon-MM interface, link clock domain, and frame clock domain) independently or in sequence.
• Initial and dynamic, real-time configuration of external converter devices via SPI interface.
• Dynamic reconfiguration of key modules in the reference design subsystem (for example, JESD204B IP core base layer, transceiver PHY, core PLL, and so forth).
• Error handling via interrupt service routines (ISR).
• Status register read back.
• Dynamic switching between real-time operation and test mode.

The software C code included as part of the reference design performs basic JESD204B link initialization and brings up the user command prompt, where you can enter commands to perform a wide variety of tasks. Modify the code as necessary to meet your system specifications.

This section contains instructions on how to customize the reference design to various configurations.

To customize the JESD204B IP core parameters to meet your specifications, follow these steps:

1. Launch the Quartus^® Prime software.
2. On the File menu, click Open.
3. Browse and select the jesd204b_ed_soc.qsys file located in the project directory.
4. Click Open to view the Qsys system in the System Contents window.
5. Right-click on the jesd204b_subsystem_0 module and select the Drill into subsystem option. The jesd204b_system.qsys project opens in the System Contents window.
6. In the System Contents window, locate the jesd204b module and double-click it to open the parameter editor. This brings up the Parameters tab that shows the current parameter settings of the JESD204B IP core.
7. Modify the IP core parameters of the jesd204b module as necessary per your system specifications. When you are done, navigate to File and click Save.
8. Click the Move to the top of hierarchy button to move back to the jesd204b_ed_soc.qsys view.
9. Click Generate HDL to generate the HDL files needed for Quartus compilation.
10. After the HDL generation completes, click Finish to save your Qsys settings and exit the Qsys window.
11. You have to manually change the system parameters in the top level HDL file to match the parameters that you set in the Qsys project (if applicable). Open the top level HDL file (jesd204b_ed.sv) in any text editor of your choice.
12. Modify the system parameters at the top of the file to match the new JESD204B IP core settings in the Qsys project, if applicable. Refer to the System Parameters section for more details on the system parameters.
13. Save the file and compile the design in Quartus as per the instructions in the Compiling the HDL and Programming the Board section.

When changing the data rate or reference clock frequency, be aware of the relationships between the serial data rate, link clock, and frame clock as described in the Core PLL section. Change the PLL output clock settings accordingly to meet the clock frequency requirements. Also note the F1_FRAMECLK_DIV and F2_FRAMECLK_DIV frame clock division factor parameters for cases when F=1 or F=2. These parameters further divide down the frame clock frequency requirement so the resulting clock frequency is within bounds of timing closure for the FPGA core fabric. See the Core PLL section for more details on clocking requirements and the System Parameter section for more details on the frame clock division factor parameters. Follow the steps below when changing the serial data rate or reference clock frequency.

1. Go through the steps in the Modifying JESD204B IP Core Parameters section to open the jesd204b_system.qsys project in the QSYS window.
2. Double-click the jesd204b module to bring up the JESD204B IP core parameter editor.
3. Change the Data rate and PLL/CDR Reference Clock Frequency values as necessary to meet your system requirements.
4. If the clock frequency values for device_clk, link_clk, frame_clk, or mgmt_clk needs to be updated, double-click the relevant clock source module in the jesd204b_system.qsys System Contents tab and modify the clock frequency values accordingly.
5. Navigate back to the top level jesd204b_ed_soc.qsys hierarchy.
6. If the clock frequency values for device_clk, link_clk, frame_clk, or mgmt_clk needs to be updated, double-click the relevant clock source module in the jesd204b_ed_soc.qsys System Contents tab and modify the clock frequency value accordingly.
7. Click Generate HDL to generate the HDL files needed for Quartus compilation.
8. After the HDL generation completes, click Finish to save your settings and exit the Qsys window.
9. Change the core PLL reference clock or output clock frequency values, if relevant, to match your system requirements. In the Quartus Project Navigator panel, select IP Components from the pull-down menu and double-click the core_pll entity. This brings up the Altera PLL parameter editor.
10. In the Altera PLL parameter editor, modify the Reference Clock Frequency value under the General tab to meet your system requirements. Ensure that the reference clock frequency value matches the ones set for the jesd204b module in the Qsys project. Also, change the outclk0 group settings (which correspond to the link clock) and outclk1 group settings (which correspond to the frame clock) if necessary. Ensure that the link clock and frame clock values satisfy the frequency requirements as described in the Core PLL section.
11. When you are done with the edits, click Finish to save your settings.
12. If the frame clock settings (outclk1 of the core_pll module) are such that F1_FRAMECLK_DIV or F2_FRAMECLK_DIV values need to be changed, modify the relevant system parameters in the top level HDL file, jesd204b_ed.sv as described in the Modifying JESD204B IP Core Parameters section.
13. Save the file and compile the design in Quartus as per the instructions in the Compiling the HDL and Programming the Board section.

1. Open the top level Qsys project (jesd204b_ed_soc.qsys) as per the instructions in the Qsys system section.
2. Each JESD204B link is represented by a single jesd204b_subsystem instantiation. To implement multi-links in Qsys, duplicate the jesd204b_subsystem instantiations. In the System Contents tab, right-click on the jesd204b_subsystem_0 module and select Duplicate. This duplicates the jesd204b_subsystem_0 module to a new module called jesd204b_subsystem_1.
3. Connect the jesd204b_subsystem_1 ports as shown in the table below. Any ports not described in the table below should be exported. To export a port, double-click on the Double-click to export label in the Export column of the System Contents tab.

   Table 20.  Port Connections of jesd204b_subsystem_1 Module

   Ports of jesd204b_subsystem_1 Module	Connection
   device_clk	device_clk.clk
   do_not_connect_reset_0	mgmt_clk.clk_reset
   do_not_connect_reset_1	mgmt_clk.clk_reset
   do_not_connect_reset_2	mgmt_clk.clk_reset
   frame_clk	frame_clk.clk
   jesd204b_jesd204_rx_int	hps_0.f2h_irq0 ILC.irq
   jesd204b_jesd204_tx_int	hps_0.f2h_irq0 ILC.irq
   link_clk	link_clk.clk
   mgmt_clk	mgmt_clk.clk
   mgmt_reset	mgmt_clk.clk_reset
   mm_bridge_s0	fpga_only_master.master mm_bridge_0.m0
   reset_seq_irq	hps_0.f2h_irq0 ILC.irq
   reset_seq_pll_reset	Do not connect
   reset_seq_reset_in0	mgmt_clk.clk_reset

4. Adjust the IRQ port count of the ILC module to accommodate new interrupt ports of the jesd204b_subsystem_1 module. Double-click the ILC module in the System Contents tab. In the ILC module Parameters tab, adjust the IRQ_PORT_COUNT parameter to 9.
5. Adjust the interrupt priorities of the interrupt ports (for example, jesd204b_jesd204_rx_int , jesd204b_jesd204_tx_int, reset_seq_irq) of the new jesd204b_subsystem_1 module as necessary to meet your system specifications. Click on the priority number of the relevant interrupt ports in the IRQ column of the System Contents tab and edit accordingly. The lower the number, the higher the priority.
6. Assign the address map of the jesd204b_subsystem_1 module. Refer to the Top Level Qsys Address Map section for more details on the top level Qsys project address map. Bits 16-17 of the Avalon-MM bridge (0x0004_0000 base address) indicate the link number. Assign the address map of the jesd204b_subsystem_1 module as shown in the figure below.
   Figure 8. Multi-Link Address Map

   Notice that bits 16-17 of the address map denote the link indicator. For subsequent links, increment the link indicator accordingly. Up to 4 links can be supported in this manner.

   Attention: Do not exceed the maximum number of links (4) that the address map can support.
7. Repeat steps 2 – 6 for subsequent links in your design.
8. Click Generate HDL to generate the HDL files needed for Quartus compilation.
9. After the HDL generation completes, click Finish to save your Qsys settings and exit the Qsys window.

1. Open the top level HDL file (jesd204b_ed.sv) in any text editor of your choice.
2. Modify the LINK system parameter to reflect the number of links in your design.
3. Replace the single-link jesd204b_ed_soc instance with the multi-link one generated from Editing the QSYS Project section above.
4. Reconnect in a similar way all the ports that are similar between the single-link jesd204b_ed_soc instance and the multi-link one.
5. The ports that are new in the multi-link jesd204b_ed_soc instance are the ports associated with the jesd204b_subsystem_1 module. Connect the ports that have jesd204b_subsystem_1_* prefix as shown in the example below:

   .jesd204b_subsystem_1_jesd204b_txlink_rst_n_reset_n
   (tx_link_rst_n[1]),
   

6. Repeat step 5 for subsequent links in your design.
7. Save the file and compile the design in Quartus as per the instructions in the Compiling the HDL and Programming the Board section.

Ensure that any additional pins that are available from the addition of multi-links (for example, tx_serial_data and rx_serial_data pins) have the proper pin assignments in the Quartus settings file (jesd204b_ed.qsf).

1. Open the main.h header file in any text editor of your choice.
2. Change the MAX_LINKS parameter to match the number of links implemented in your design and save the file.
   Attention: Do not exceed the maximum number of links (4) that the address map can support.
3. Compile and execute the source code as per the instructions in the Setting up the Software Command Line Environment section.