Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

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AN-JESD204B-AV | 2015.06.25

Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

The Altera^® JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP).

The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) device.

This report highlights the interoperability of the JESD204B IP core with the AD9250 Analog-to-Digital Converter evaluation module (EVM) from Analog Devices Inc. (ADI). The hardware checkout methodology and test results are described in the following sections.

Hardware Requirements

The hardware checkout test requires the following hardware and software tools:

Arria^® V GT FPGA Development Kit with 19 V power adaptor
Arria V SoC Development Kit
ADI AD9250 EVM (AD9250-FMC-250EBZ)
Mini-USB cable

Hardware Setup

Set up the development kit with the ADI AD9250 daughter card module installed to the board's FMC connector.

Figure 1. Hardware Setup for Arria V GT Development Kit.

The AD9250 module derives power from the FMC connector on the development board.
The AD9250 module supplies the device clock to FPGA 2.
For subclass 1 mode, the FPGA generates SYSREF for the JESD204B MegaCore function as well as the AD9250 module.

Figure 2. Hardware Setup for Arria V SoC Development Kit.

The AD9250 module derives power from the FMC connector on the development board.
The AD9250 module supplies clock to the FPGA and ADC.
For subclass 1 mode, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9250 module.

Figure 3. System Diagram.

The system-level diagram shows how the different modules connect in this design.

In this setup where LMF = 222, the data rate of the both transceiver lanes is 4.915 Gbps. The AD9517 clock generator provides 122.88 MHz clock to the FPGA and 245.76 MHz sampling clock to both AD9250 devices.

Hardware Checkout Methodology

The following section describes the test objectives, procedure, and the passing criteria. The test covers the following areas:

Receiver data link layer
Receiver transport layer
Descrambling
Deterministic latency (Subclass 1)

Receiver Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial frame and lane synchronization.

On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The SignalTap II Logic Analyzer tool is used to monitor the operation of receiver data link layer.

Code Group Synchronization (CGS)

Table 1. CGS Test Cases
Test Case	Objective	Description	Passing Criteria
CGS.1	Check whether sync request is deasserted after correct reception of four successive /K/ characters.	The following signals in <ip_variant_name> _inst_phy.v are tapped: `jesd204_rx_pcs_data[(L32)-1:0]` `jesd204_rx_pcs_data_valid[L-1:0]` `jesd204_rx_pcs_kchar_data[(L4)-1:0]` ¹ The following signals in <ip_variant_name> .v are tapped: `rx_dev_sync_n` `jesd204_rx_int` The `rxframe_clk` is used as the SignalTap II sampling clock. Each lane is represented by 32-bit data bus in `jesd204_rx_pcs_data`. The 32-bit data bus is divided into 4 octets.	/K/ character (0xBC) is observed at each octet of the `jesd204_rx_pcs_data` bus. The `jesd204_rx_pcs_data_valid` signal is asserted to indicate that data from the PCS is valid. The `jesd204_rx_pcs_kchar_data` signal is asserted whenever control characters like /K/, /R/, /Q/, or /A/ are observed. The `rx_dev_sync_n` signal is deasserted after correct reception of at least four successive /K/ characters. The `jesd204_rx_int` signal is deasserted if there is no error.
CGS.2	Check full CGS at the receiver after correct reception of another four 8B/10B characters.	The following signals in <ip_variant_name> _inst_phy.v are tapped: `jesd204_rx_pcs_errdetect[(L4)-1:0]` `jesd204_rx_pcs_disperr[(L4)-1:0]` ¹ The following signal in <ip_variant_name> .v is tapped: `jesd204_rx_int` The `rxframe_clk` is used as the SignalTap II sampling clock.	The `jesd204_rx_pcs_errdetect`, `jesd204_rx_pcs_disperr`, and `jesd204_rx_int` signals should not be asserted during CGS phase.

¹ L is the number of lanes.

Initial Frame and Lane Synchronization

Table 2. Initial Frame and Lane Synchronization Test Cases
Test Case	Objective	Description	Passing Criteria
ILA.1	Check whether the initial frame synchronization state machine enters `FS_DATA` state upon receiving non /K/ characters.	The following signals in <ip_variant_name> _inst_phy.v are tapped: `jesd204_rx_pcs_data[(L32)-1:0]` `jesd204_rx_pcs_data_valid[L-1:0]` `jesd204_rx_pcs_kchar_data[(L4)-1:0]` ² The following signals in <ip_variant_name> .v are tapped: `rx_dev_sync_n` `jesd204_rx_int` The `rxframe_clk` is used as the SignalTap II sampling clock. Each lane is represented by 32-bit data bus in `jesd204_rx_pcs_data`. The 32-bit data bus is divided into 4 octets.	/R/ character or K28.0 (0x1C) is observed after /K/ character at the `jesd204_rx_pcs_data` bus. The `jesd204_rx_pcs_data_valid` signal must be asserted to indicate that data from the PCS is valid. The `rx_dev_sync_n` and `jesd204_rx_int` signal are deasserted. Each multiframe in the ILAS phase ends with /A/ character or K28.3 (0x7C). The `jesd204_rx_pcs_kchar_data` signal is asserted whenever control characters like /K/, /R/, /Q/, or /A/ are observed.
ILA.2	Check the JESD204B configuration parameters from ADC in the second multiframe.	The following signals in <ip_variant_name> _inst_phy.v are tapped: `jesd204_rx_pcs_data[(L32)-1:0]` `jesd204_rx_pcs_data_valid[L-1:0]` ² The following signal in <ip_variant_name>* .v is tapped: `jesd204_rx_int` The `rxframe_clk` is used as the SignalTap II sampling clock. The System Console accesses the following registers: `ilas_octet0` `ilas_octet1` `ilas_octet2` `ilas_octet3`	/R/ character is followed by /Q/ character or K28.4 (0x9C) at the beginning of the second multiframe. The `jesd204_rx_int` signal is deasserted if there is no error. Octets 0-13 read from these registers match with the JESD204B parameters in each test setup.
ILAS.3	Check the lane alignment	The following signals in <ip_variant_name> _inst_phy.v are tapped: `jesd204_rx_pcs_data[(L32)-1:0]` `jesd204_rx_pcs_data_valid[L-1:0]` ² The following signal in <ip_variant_name>* .v is tapped: `rx_somf[3:0]` `dev_lane_aligned` `jesd204_rx_int` The `rxframe_clk` is used as the SignalTap II sampling clock.	The `dev_lane_aligned` signal is asserted after the end of the fourth multiframe in ILAS phase but before the first `rx_somf` signal is asserted. The `rx_somf` signal marks the start of multiframe in user data phase. The `jesd204_rx_int` signal is deasserted if there is no error.

² L is the number of lanes.

Receiver Transport Layer

To check the data integrity of the payload data stream through the RX JESD204B IP core and transport layer, the ADC is configured to output PRBS-9 test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP core. The PRBS checker in the FPGA fabric checks data integrity for one minute.

Figure shows the conceptual test setup for data integrity checking.

Figure 4. Data Integrity Check Using PRBS Checker

The SignalTap II Logic Analyzer tool is used to monitor the operation of the RX transport layer.

Table 3. Transport Layer Test Cases
Test Case	Objective	Description	Passing Criteria
TL.1	Check the transport layer mapping.	The following signals in altera_jesd204_transport_rx_top.v are tapped: `jesd204_rx_data_valid` `jesd204_rx_link_data_valid` `jesd204_rx_link_error` The following signals in jesd204b_ed.v are tapped: `data_error[M-1:0]` `jesd204_rx_int` M is the number of converters. The `rxframe_clk` is used as the SignalTap II sampling clock. The `data_error` signal is the PRBS checker's pass or fail indicator.	The `jesd204_rx_data_valid` and `jesd204_rx_link_data_valid` signals is asserted. The `jesd204_rx_link_error` and `jesd204_rx_int` signals is deasserted.

Descrambling

The PRBS checker at the RX transport layer checks the data integrity of descrambler.

The SignalTap II Logic Analyzer tool is used to monitor the operation of the RX transport layer.

Table 4. Descrambler Test Cases
Test Case	Objective	Description	Passing Criteria
SCR.1	Check the functionality of the descrambler.	Enable scrambler at the ADC and descrambler at the RX JESD204B IP core. The signals that are tapped in this test case are similar to test case TL.1	The `jesd204_rx_data_valid` and `jesd204_rx_link_data_valid` signals is asserted. The `jesd204_rx_link_error` and `jesd204_rx_int` signals is deasserted.

Deterministic Latency (Subclass 1)

Figure shows the block diagram of deterministic latency test setup. A SYSREF generator provides a periodic SYSREF pulse for both the AD9250 and JESD204B IP core. The SYSREF generator is running in link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.

Figure 5. Deterministic Latency Test Setup Block Diagram

The deterministic latency measurement block checks the deterministic latency by measuring the number of link clock counts between the start of deassertion of SYNC~ to the first user data output.

Figure 6. Deterministic Latency Measurement Timing Diagram

With the setup above, four test cases were defined to prove deterministic latency. By default, the JESD204B IP core performs a single SYSREF detection. The SYSREF N-shot mode is enabled on the AD9250 for this deterministic measurement.

Table 5. Deterministic Latency Test Cases
Test Case	Objective	Description	Passing Criteria
DL.1	Check the LMFC alignment.	Check that the FPGA and ADC are aligned to the desired LMF periods. SYSREF detection is always enabled. Observe the `sysref_lmfc_err` signal from the Signal Tap II Logic Analyzer.	The `sysref_lmfc_err` signal should not be triggered.
DL.2	Check the SYSREF capture.	Check that the FPGA and ADC capture SYSREF correctly and restart the LMF counter. Both the FPGA and ADC are also repetitively reset. Observe the `csr_rbd_count` signal from the Signal Tap II Logic Analyzer.	If the SYSREF is captured correctly and the LMF counter restarts, the `csr_rbd_count` value should only drift a little for every reset due to word alignment.
DL.3	Check the latency from start of deassertion of SYNC~ to the first user data output.	Check that the latency is fixed for every FPGA reset. Repetitively reset the FPGA upon assertion of RX valid. Record the number of link clocks count from start of deassertion of SYNC~ to the first user data output. Continuously compare the current test (n) that records the number of link clocks from deassertion of SYNC~ to the first user data output with the previous test (n-1) record.	Consistent latency from the start of deassertion of SYNC~ to the first user data output latency.

JESD204B IP Core and AD9250 Configurations

The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the AD9250 module's quick configuration register at address 0x5E. The transceiver data rate, sampling clock frequency, and other JESD204B parameters complies with the AD9250 operating conditions.

The hardware checkout testing implements the JESD204B IP core with the following parameter configuration.

Table 6. Parameter Configuration
Configuration		Setting
JESD204B Parameters	LMF	112	124	222	211
	HD	0	0	0	1
	S	1	1	1	1
	N	14	14	14	14
	N'	16	16	16	16
	CS	0	0	0	0
	CF	0	0	0	0
FPGA Clock	Device Clock (MHz) ³	122.88
	Management Clock (MHz)	100
	Frame Clock/Sampling Clock (MHz) ⁴	245.76	122.88	245.76	245.76
	Link Clock (MHz) ⁴	122.88			61.44
/K/ Character Replacement		Enabled
Data Pattern		PRBS-9 Ramp ⁵

³ The device clock is used to clock the transceiver.

⁴ The frame clock and link clock is derived from the device clock using an internal PLL.

⁵ The ramp pattern is used in deterministic latency measurement test cases DL.1, DL.2, and DL.3 only.

Test Results

The following table contains the possible results and their definition.

Table 7. Results Definition
Result	Definition
PASS	The Device Under Test (DUT) was observed to exhibit conformant behavior.
PASS with comments	The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations, only a portion of the testing was performed.
FAIL	The DUT was observed to exhibit non-conformant behavior.
Warning	The DUT was observed to exhibit behavior that is not recommended.
Refer to comments	From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included.

The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock and SYSREF frequencies.

Table 8. Test Results
Test	L	M	F	Sub-class	SCR	K	Data rate (Mbps)	Sampling Clock (MHz)	Link Clock (MHz)	SYSREF (MHz)	Result
1	1	1	2	0	0	16	4915	245.76	122.88	—	PASS
2	1	1	2	0	0	32	4915	245.76	122.88	—	PASS
3	1	1	2	0	1	16	4915	245.76	122.88	—	PASS
4	1	1	2	0	1	32	4915	245.76	122.88	—	PASS
5	1	1	2	1	0	16	4915	245.76	122.88	15.36	PASS
6	1	1	2	1	0	32	4915	245.76	122.88	7.68	PASS
7 ⁶	1	1	2	1	1	16	4915	245.76	122.88	15.36	PASS
8 ⁶	1	1	2	1	1	32	4915	245.76	122.88	7.68	PASS
9	1	2	4	0	0	16	4915	122.88	122.88	—	PASS
10	1	2	4	0	0	32	4915	122.88	122.88	—	PASS
11	1	2	4	0	1	16	4915	122.88	122.88	—	PASS
12	1	2	4	0	1	32	4915	122.88	122.88	—	PASS
13	1	2	4	1	0	16	4915	122.88	122.88	7.68	PASS
14	1	2	4	1	0	32	4915	122.88	122.88	3.84	PASS
15 ⁶	1	2	4	1	1	16	4915	122.88	122.88	7.68	PASS
16 ⁶	1	2	4	1	1	32	4915	122.88	122.88	3.84	PASS
17	2	1	1	0	0	20	2457	245.76	61.44	—	PASS
18	2	1	1	0	0	32	2457	245.76	61.44	—	PASS
19	2	1	1	0	1	20	2457	245.76	61.44	—	PASS
20	2	1	1	0	1	32	2457	245.76	61.44	—	PASS
21	2	1	1	1	0	20	2457	245.76	61.44	12.288	PASS
22	2	1	1	1	0	32	2457	245.76	61.44	7.68	PASS
23 ⁶	2	1	1	1	1	20	2457	245.76	61.44	12.288	PASS
24 ⁶	2	1	1	1	1	32	2457	245.76	61.44	7.68	PASS
25	2	2	2	0	0	16	4915	245.76	122.88	—	PASS
26	2	2	2	0	0	32	4915	245.76	122.88	—	PASS
27	2	2	2	0	1	16	4915	245.76	122.88	—	PASS
28	2	2	2	0	1	32	4915	245.76	122.88	—	PASS
29	2	2	2	1	0	16	4915	245.76	122.88	15.36	PASS
30	2	2	2	1	0	32	4915	245.76	122.88	7.68	PASS
31 ⁶	2	2	2	1	1	16	4915	245.76	122.88	15.36	PASS
32 ⁶	2	2	2	1	1	32	4915	245.76	122.88	7.68	PASS

Table 9. Deterministic Latency Measurement for Arria V GT
Test	L	M	F	Sub-class	K	Data rate (Mbps)	Sampling Clock (MHz)	Link Clock (MHz)	SYSREF (MHz)	Result
DL.1	2	2	2	1	32	4915	245.76	122.88	7.68	PASS
DL.2	2	2	2	1	32	4915	245.76	122.88	7.68	PASS
DL.3	2	2	2	1	32	4915	245.76	122.88	7.68	PASS with comments. Link clock observed: 131-132

Table 10. Deterministic Latency Measurement for Arria V SoC
Test	L	M	F	Subclass	SCR	K	Data Rate (Msps)	Link Clock (MHz)	Result
DL.1	1	1	2	1	1	16	4915	122.88	PASS
DL.2									PASS
DL.3									PASS with comments. Link clock observed: 83
DL.1	1	1	2	1	1	32	4915	122.88	PASS
DL.2									PASS
DL.3									PASS with comments. Link clock observed: 131
DL.1	1	2	4	1	1	16	4915	122.88	PASS
DL.2									PASS
DL.3									PASS with comments. Link clock observed: 131
DL.1	1	2	4	1	1	32	4915	122.88	PASS
DL.2									PASS
DL.3									PASS with comments. Link clock observed: 227
DL.1	2	1	1	1	1	20	2457	61.44	PASS
DL.2									PASS
DL.3									PASS with comments. Link clock observed: 63
DL.1	2	1	1	1	1	32	2457	61.44	PASS
DL.2									PASS
DL.3									PASS with comments. Link clock observed: 83
DL.1	2	2	2	1	1	16	4915	122.88	PASS
DL.2									PASS
DL.3									PASS with comments. Link clock observed: 83
DL.1	2	2	2	1	1	32	4915	122.88	PASS
DL.2									PASS
DL.3									PASS with comments. Link clock observed: 131

The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~ in the first output of the ramp test pattern. The clock count measures the first user data output latency.

Figure 7. Deterministic Latency Measurement Ramp Test Pattern

⁶ Results for both Arria V GT and Arria V SoC devices.

Test Result Comments

In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until user data phase. No data integrity issue is observed by the PRSB checker. For test case with LMF = 211, the data rate is reduced to 2457 Mbps to limit the ADC sample clock to less than 250 MHz. The following table describes the scenarios where there is a difference in the data rate.

Table 11. Sample Rate Implication for Test Case with LMF = 211
Item	Scenario 1	Scenario 2	Remark
Data rate	4915 Mbps	2457 Mbps	Data rate is within the operating condition of AD9250.
Link clock = data rate/40	122.88 MHz	61.44 MHz	Link clock frequency is determined by the data rate.
ADC sample clock must be ≤ ADC maximum sampling rate	491.52 MHz	245.76 MHz	Sample clock frequency in scenario 1 is beyond the operating condition of AD9250.

The link clock count variation in the deterministic latency measurement is caused by the word alignment, where control characters fall into the next cycle of data some time after realignment. This makes the duration of the ILAS phase longer by one link clock some time after reset.

Document Revision History

Date	Version	Changes
June 2015	2015.06.25	Added new information on hardware setup, parameter configurations, and test results for Arria V SoC device.
December 2013	2013.12.02	Initial release.