PHY Lite for Parallel Interfaces Intel FPGA IP Core User Guide: Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX Devices
Version Information
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 19.3 |
| IP Version 19.1 |
About the PHY Lite for Parallel Interfaces IP Core
This user guide describes the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP, PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP, and PHY Lite for Parallel Interfaces Intel® Cyclone® 10 GX FPGA IP cores. The PHY Lite for Parallel Interfaces IP core is primarily used for building custom memory interface PHY blocks. You can use this solution to interface with protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (Synchronous Mode), and Mobile DDR.
The IP core has a dedicated PHY clock tree in each I/O bank. The PHY clock tree is shorter which yields lower jitter and duty cycle distortion (DCD), enabling designs to achieve higher performance.
In addition, this IP core supports Dynamic Reconfiguration feature which enables reconfiguration of the data and strobe delays. You can align the data and strobe via calibration to achieve timing closure at high frequencies.
This IP core controls the strobe-based capture I/O elements. Each instance of the IP core can support an interface up to 18 individual data/strobe capture groups. Each group can contain up to 48 data I/Os as well as the strobe capture logic.
Device Family Support
For Arria® V, Cyclone® V, and Stratix® V devices, use the ALTDQ_DQS2 Intel FPGA IP core instead.
Features
The PHY Lite for Parallel Interfaces IP core:
- Supports input, output, and bidirectional data channels
- Supports DQS-group based data capture, with up to 48 I/Os (including strobes) per group and DQS gating/ungating circuitry for strobe-based interfaces
- Supports output delays via interpolator
- Supports dynamic on-chip termination (OCT) control
- Supports quarter-rate to half-rate and half-rate to full-rate of the interface clock conversions.
- Supports input, output, and read/DQS/OCT enable paths
- Supports single data rate (SDR) and double data rate (DDR) at the I/Os
- Supports PHY clock tree
- Supports dynamically reconfigurable delay chains using Avalon-MM interface
- Supports process, voltage,
and temperature (PVT) or non-PVT compensated input and DQS delay chains Note: The non-PVT compensated component of the input delay is set through the .qsf assignment in the Intel® Quartus® Prime software.
Release Information
IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.
The IP versioning scheme (X.Y.Z) number changes from one software version to another. A change in:
- X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
- Y indicates the IP includes new features. Regenerate your IP to include these new features.
- Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
| Item | Description |
|---|---|
| IP Version | 19.1 |
| Intel® Quartus® Prime Version | 19.3 |
| Release Date | September 2019 |
Functional Description
The PHY Lite for Parallel Interfaces IP core utilizes the I/O subsystem in the Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices. The I/O subsystem is located in the I/O columns of each Intel FPGA devices. For Intel® Stratix® 10 devices, each column consists of I/O banks and IOSSM. For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, each column consists of I/O banks and I/O aux. The number of I/O banks varies according to device packages. Each bank is a group of 48 I/O pins, organized into four I/O lanes with 12 pins for each lane. Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combined to form a single data/strobe group or up to four groups in the same interface. Under certain conditions, two groups from different interfaces can also be supported in the same bank.
Top Level Interfaces
The PHY Lite for Parallel Interfaces IP core consists of the following ports:
- Clocks and reset
- Core data and control (broken down into input and output paths)
- I/O (broken down into input and output paths)
- Avalon-MM configuration bus (available only when Dynamic Reconfiguration feature is enabled)
Clocks
The PHY Lite for Parallel Interfaces IP core uses a reference clock that is sourced from a dedicated clock pin to the PLL inside the IP core. This PLL provides four clock domains for the output and input paths.
| Clock Domain | Description |
|---|---|
| Core clock | This clock is generated internally by the IP core and it is used for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phase with the PHY clock for core-to-periphery and periphery-to-core transfers. |
| PHY clock | This clock is used internally by the IP core for PHY circuitry running at the same frequency as the core clock. |
| VCO clock | This clock is generated internally by the PLL. It is used by both the input and output paths to generate PVT compensated delays in the interpolator. |
| Interface clock | This is the clock frequency of the external device connected to the FPGA I/Os . |
| Core Clock Rate | Speed Grade –1 (MHz) | Speed Grade –2 (MHz) | Speed Grade –3 (MHz) | |||
|---|---|---|---|---|---|---|
| Min | Max | Min | Max | Min | Max | |
| Full | 100 | 333 | 100 | 300 | 100 | 233 |
| Half | 100 | 667 | 100 | 600 | 100 | 467 |
| Quarter | 100 | 1200 | 100 | 1200 | 100 | 933 |
| Core Clock Rate | Speed Grade –1 (MHz) | Speed Grade –2 (MHz) | Speed Grade –3 (MHz) | |||
|---|---|---|---|---|---|---|
| Min | Max | Min | Max | Min | Max | |
| Full | 100 | 333 | 100 | 266 | 100 | 233 |
| Half | 100 | 667 | 100 | 533 | 100 | 466 |
| Quarter | 100 | 1200 | 100 | 1067 | 100 | 933 |
| Core Clock Rate | Speed Grade –5 (MHz) | Speed Grade –6 (MHz) | ||
|---|---|---|---|---|
| Min | Max | Min | Max | |
| Full | 100 | 266 | 100 | 233 |
| Half | 100 | 533 | 100 | 466 |
| Quarter | 100 | 1067 | 100 | 933 |
Clock Frequency Relationships
The following equations describe the relationships between the clock domains available in the PHY Lite for Parallel Interfaces IP core.
Core Clock Rate = Interface clock frequency / Core clock frequency
VCO frequency Multiplier Factor = VCO clock frequency 1 / Interface clock frequency
Output Path
The output path consists of a FIFO and an interpolator.
| Block | Description |
|---|---|
| Write FIFO | Serializes the output data from the core with a serialization factor of up to 8 (in DDR quarter-rate). |
| Interpolator | Works with the FIFO block to generate the desired output delay. You can dynamically configure the delay through the Avalon-MM interface. For more information, refer to Dynamic Reconfiguration section. |
- Interface Frequency: 1000 MHz
- VCO Multiplier Factor: 1
- User logic clock rate: Quarter rate
- Interface Frequency: 1000 MHz
- VCO Multiplier Factor: 1
- User logic clock rate: Quarter rate
Output Path Data Alignment
The data_from_core and oe_from_core signals are arranged in time slices, which are broken down into the individual pins in the group. The first time slice is on the LSBs of the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering of the External Memory Interfaces IP core.
Example of time slices with individual pins correlation:
{time(n),time(n-1),time(n-2),... time(0)}
Where time0 = {pin(n),pin(n-1),pin(n-2),...pin0}
Input Path
The input path of the IP core consists of a data path, a strobe path, and a read enable path.
| Path | Description |
|---|---|
| Data Path |
Receives data from external device to the FPGA core logic. The data path consists of a PVT compensated delay
chain, a DDIO and a read FIFO.
Signals used in this path are:
The IP core supports SDR input by sending data on single clock cycle from the external device. |
| Strobe Path |
Input strobe (dqs) to capture input data from external device. The strobe path consists of pstamble_reg (a gating
component) and a PVT compensated delay chain.
Signals used in this path are:
|
| Read and Strobe Enable Path |
Generates control signals for strobe calibration and reading data from Read FIFO. The read and strobe enable path consists of VFIFO,
DQS_EN FIFO, and an interpolator.
Signals used in this path are:
|
| Read Operation Sequence Number | Operation |
|---|---|
| 1 | The core asserts the rdata_en signal to the PHY Lite for Parallel Interfaces IP and issues a read command to the external device. |
| 2 | VFIFO and DQS_EN FIFO generate the dqs_enable signal to pstamble_reg. This strobe is delayed by the programmed read latency (which should match the latency of the external device). |
| 3 | The pstamble_reg generates dqs_cleansignal as valid data enters the read path. |
| 4 | The Delay Chain (PVT) adjusts the strobe with phase offset between the strobe and the input data (for example, 90° phase shift for DDR center-alignment). |
| 5 | The dqs signal is then used as strobe to read data from external device into the DDIO and Read FIFO modules. |
| 6 | The VFIFO asserts the read_enable signal to Read FIFO and the rdata_valid signal to the core simultaneously. The PHY Lite for Parallel Interfaces IP sends the captured data to the core with the associated valid signal. |
The following figures show the waveform diagrams for the input path. The delays shown in the waveforms are just estimation based on simulations and these values will be different with different core clock rate and VCO multiplier.
- Interface Frequency: 1000 MHz
- VCO Multiplier Factor: 1
- User logic clock rate: Quarter rate
Input Path Data Alignment
The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to the ordering of the output path. That is, the LSBs of the bus hold the first time slice of data received.
The rdata_valid delay is always set by the IP core to match the rdata_en alignment. For example, quarter-rate delays are multiples of four external memory clock cycles (one quarter rate clock cycle).
Reading from an unaligned memory address is called unaligned reads. Unaligned reads will result in unaligned rdata_valid and data_to_core with data and valid signals packed to the LSBs. This request causes the IP core to do two or more read operations.
The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data from group_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1, which shows there are 2 bytes of incoming data from group_0_data_io bus.
The valid data are transfer to the IP core through the group_0_data_to_core bus. At first rising edge of the core_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytes of the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On the subsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes of the data from the group_0_data_to_core bus are valid.
Dynamic Reconfiguration
Because of the asynchronous nature of the PHY, you must perform calibration to achieve timing closure at a high frequency. At a high level, calibration involves reconfiguring input and output delays in the PHY to align data and strobes. With the PHY Lite for Parallel Interfaces IP, you can perform the calibration by using dynamic reconfiguration feature. The dynamic reconfiguration feature allows you to modify these delays by writing to a set of control registers using an Avalon-MM interface.
RTL Connectivity
The PHY Lite for Parallel Interfaces IP core exposes the Avalon-MM master and Avalon-MM slave interfaces when you enable the dynamic reconfiguration feature. If the generated IP core is the only PHY Lite for Parallel Interfaces IP core (with dynamic reconfiguration) or External Memory Interface IP core in the I/O column, connect only the Avalon-MM slave interface with a master in the core. Otherwise, connect Avalon-MM master and slave interfaces as described in the following section.
Daisy Chain
The I/O column provides a single physical Avalon-MM interface. All IP cores in the I/O column that require Avalon-MM interface access the same physical Avalon-MM interface. The system-level RTL for the column reflects this resource limitation by using a daisy chain to connect all dynamically reconfigurable IP cores in an I/O column.
The PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core exposes a 31-bit Avalon-MM address, followed by a 4-bit interface ID. For PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP and PHY Lite for Parallel Interfaces Intel® Cyclone® 10 GX FPGA IP cores, the Avalon-MM address is 28 bits where the top 4-bits are the ID of the interface to be addressed in the daisy chain. These bits are only required for the daisy chain arbitration in RTL simulation, so they are not synthesized during compilation. If only one interface is addressed from the IP core, it is sufficient to connect these bits as the interface’s ID.
Notice that all core controllers must go through the arbitration logic that you created in the FPGA core logic to connect to an interface on the daisy chain. The end of the daisy chain should have its master output interface tied to 0.
Address Lookup
If you do not set the pin locations in the .qsf file, the lane addresses and pin placement to an interface changes every time you compile your design in Intel® Quartus® Prime software. However, the PHY Lite for Parallel Interfaces IP core is always generated as if the IP core is the only IP core in a column, with lane addresses starting from 0. You need to determine the lane and pin addresses in order to dynamically reconfigure the calibration settings in the IP core.
To provide a unified way to look up reconfigurable feature addresses for a specific interface both before and after placement, the address information is stored in memory in the I/O column. This memory is addressable over the same Avalon-MM bus used for feature reconfiguration.
You can cache lookups 1 to 4 (8-bytes of information) to have pin and lane translations in one look-up.
| Component | Description |
|---|---|
| Global parameter table | Stores pointers to the individual interface parameter tables. The global parameter table lists all interfaces in the column (both the External Memory Interfaces and PHY Lite for Parallel Interfaces IP cores). |
| Set of individual interface parameter tables | Contain interface specific information. This is where pin-level and lane-level address look-ups are performed. |
Below are the steps to determine the lane and pin addresses from the lookup tables (the sequence corresponds to the sequence in Memory Overview in Intel® Stratix® 10 Devices):
| Legend in Memory Overview in Intel® Stratix® 10 Devices | Description |
|---|---|
| 1 | Search for Interface Parameter Table
in Global Parameter Table (cache once per interface)
|
| 2 | Retrieve number of groups in the
interface (cache once per interface)
|
| 3 | Retrieve group information (cache once
per group)
|
| 4 | Retrieve Lane/Pin Address Offsets for
group (cache once per group)
|
| 5 | Perform lane/pin address translation
(cache once per pin)
|
| 6 | Read/Write Avalon Calibration Bus
|
Below are the steps to determine the lane and pin addresses from the lookup tables (the sequence corresponds to the sequence in Figure 16):
| Legend in Figure 16 | Description |
|---|---|
| 1 | Search for Interface Parameter Table
in Global Parameter Table (cache once per interface)
|
| 2 | Retrieve number of groups in the
interface (cache once per interface)
|
| 3 | Retrieve group information (cache
once per group)
|
| 4 | Retrieve Lane/Pin Address Offsets for
group (cache once per group)
|
| 5 | Perform lane/pin address translation
(cache once per pin)
|
| 6 | Read/Write Avalon Calibration Bus
|
Strobes
The first pins listed in the pin address lookup table are the strobes. They are also identified by bits[7:4] = 0xE. For separate strobes, the input strobe pin placement always take precedence. For differential and complementary strobes, the positive pin is the lower index.
Parameter Table Example
These figures show examples of designs containing two PHY Lite for Parallel Interfaces IP cores, each with one bidirectional group composed of 4 data bits and one strobe. Both interfaces are in the same I/O column and therefore their tables must be merged.
For more information about the contents of the parameter table, refer to Figure 16.
Reconfiguration Features and Register Addressing
Each reconfigurable feature of the interface has a set of control registers with an associated memory address to store the reconfigurable settings; however, this address is placement dependent. If PHY Lite for Parallel Interfaces IP cores and the External Memory Interface IP cores share the same I/O column, you must track the addresses of the interface lanes and the pins.
- Control/Status registers (CSR) - you can only read the values of these registers. The values are set through the IP core parameters. The CSR registers contain the default setting in the IP core.
- Avalon® Memory-Mapped registers - you can read and write to these registers using Avalon® interface. The time for the the PHY Lite for Parallel Interfaces delays to change after writing a new value to the registers via the Avalon bus is dependent on the user's configuration. For example, it will take approximately 50 VCO clock cycles for the output delay to change value. Perform an RTL simulation to show an accurate timing which correlates to the hardware operation.
PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Core Control Registers Addresses
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [30:27] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW |
Depending on the Interface ID parameter in the Parameter Editor. |
RO |
| [26:24] | Specify the Avalon controller calibration bus base address. | 3'h3 | RW | 3'h3 | RO |
| [23:21] | Reserved | 3'h0 | RW | 3'h0 | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RO |
| [12:8] | Specify the address for the physical location of a pin within a lane. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup or based on your pin assignment setting in the .qsf file. | RW | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup or based on your pin assignment setting in the .qsf file. | RO |
| [7:0] | Reserved | 8'hD0 | RW | 8'hE8 | RO |
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [30:27] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW | N/A | RO |
| [26:24] | Specify the Avalon controller calibration bus base address. | 3'h3 | RW | N/A | RO |
| [23:21] | Reserved | 3'h0 | RW | N/A | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | N/A | RO |
| [12:9] | Reserved | 4'hC | RW | N/A | RO |
| [8:7] | Select DQ pin sets to access. |
|
RW | N/A | RO |
| [6:4] | Select the specific DQ pin to access. |
|
RW | N/A | RO |
| [3:0] | Reserved | 4'h0 | RW | N/A | RO |
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [30:27] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW | N/A | RO |
| [26:24] | Specify the Avalon controller calibration bus base address. | 3'h3 | RW | N/A | RO |
| [23:21] | Reserved | 3'h0 | RW | N/A | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | N/A | RO |
| [12:0] | Reserved | 13'h18E0 | RW | N/A | RO |
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [30:27] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW |
Depending on the Interface ID parameter in the Parameter Editor. |
RO |
| [26:24] | Specify the Avalon controller calibration bus base address. | 3'h3 | RW | 3'h3 | RO |
| [23:21] | Reserved | 3'h0 | RW | 3'h0 | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RO |
| [12:0] | Reserved | 13'h18F0 | RW |
13'h1998 |
RO |
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [30:27] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW |
Depending on the Interface ID parameter in the Parameter Editor. |
RO |
| [26:24] | Specify the Avalon controller calibration bus base address. | 3'h3 | RW | 3'h3 | RO |
| [23:21] | Reserved | 3'h0 | RW | 3'h0 | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RO |
| [12:0] | Reserved | 13'h1808 | RW |
13'h19A8 |
RO |
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [30:27] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW |
Depending on the Interface ID parameter in the Parameter Editor. |
RO |
| [26:24] | Specify the Avalon controller calibration bus base address. | 3'h3 | RW | 3'h3 | RO |
| [23:21] | Reserved | 3'h0 | RW | 3'h0 | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RO |
| [12:0] | Reserved | 13'h180C | RW |
13'h19A4 |
RO |
PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IP Cores Address Registers
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [31:28] | Reserved | 4'h0 | RW | 4'h0 | RO |
| [27:24] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW |
Depending on the Interface ID parameter in the Parameter Editor. |
RO |
| [23:21] | Specify the Avalon controller calibration bus base address. | 3'h4 | RW | 3'h4 | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RO |
| [12:8] | Specify the address for the physical location of a pin within a lane. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup or based on your pin assignment setting in the .qsf file. | RW | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup or based on your pin assignment setting in the .qsf file. | RO |
| [7:0] | Reserved | 8'hD0 | RW | 8'hE8 | RO |
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [31:28] | Reserved | 4'h0 | RW | N/A | RO |
| [27:24] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW | N/A | RO |
| [23:21] | Specify the Avalon controller calibration bus base address. | 3'h4 | RW | N/A | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | N/A | RO |
| [12:9] | Reserved | 4'hC | RW | N/A | RO |
| [8:7] | Select DQ pin sets to access. |
|
RW | N/A | RO |
| [6:4] | Select the specific DQ pin to access. |
|
RW | N/A | RO |
| [3:0] | Reserved | 4'h0 | RW | N/A | RO |
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [31:28] | Reserved | 4'h0 | RW | N/A | RO |
| [27:24] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW | N/A | RO |
| [23:21] | Specify the Avalon controller calibration bus base address. | 3'h4 | RW | N/A | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | N/A | RO |
| [12:0] | Reserved | 13'18E0 | RW | N/A | RO |
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [31:28] | Reserved | 4'h0 | RW | 4'h0 | RO |
| [27:24] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW |
Depending on the Interface ID parameter in the Parameter Editor. |
RO |
| [23:21] | Specify the Avalon controller calibration bus base address. | 3'h4 | RW | 3'h4 | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RO |
| [12:0] | Reserved | 13h'18F0 | RW |
13'h1998 |
RO |
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [31:28] | Reserved | 4'h0 | RW | 4'h0 | RO |
| [27:24] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW |
Depending on the Interface ID parameter in the Parameter Editor. |
RO |
| [23:21] | Specify the Avalon controller calibration bus base address. | 3'h4 | RW | 3'h4 | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RO |
| [12:0] | Reserved | 13'h1808 | RW |
13'h19A8 |
RO |
| Bit | Description | Avalon® MM Register | CSR Register | ||
|---|---|---|---|---|---|
| Value | Access Type | Value | Access Type | ||
| [31:28] | Reserved | 4'h0 | RW | 4'h0 | RO |
| [27:24] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
Depending on the Interface ID parameter in the Parameter Editor. |
RW |
Depending on the Interface ID parameter in the Parameter Editor. |
RO |
| [23:21] | Specify the Avalon controller calibration bus base address. | 3'h4 | RW | 3'h4 | RO |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RW | You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup. | RO |
| [12:0] | Reserved | 13'h180C | RW |
13'h19A4 |
RO |
Control Registers Description
| Feature | Bit | Description |
|---|---|---|
| Pin Output Delay | [31:13] |
Reserved 2 |
| [12:0] |
Phase value Strobe minimum setting: Refer to Table 25 Strobe maximum setting: Refer to Table 25 Incremental Delay: 1/128th VCO clock period The CSR value for DQS is set through the Output Strobe Phase parameter during IP core instantiation. Note: The pin output delay switches from the CSR register value to the
Avalon register value after the first Avalon write. It is only reset to the CSR
register value on a reset of the interface.
|
|
| Pin Input Delay | [31:13] |
Reserved 2 |
| [12] |
Enable bit to select access to Avalon register or CSR register. 0 = Delay value is 0. CSR register is not available for this feature. 1 = Select delay value from Avalon register |
|
| [11:9] | Reserved 2 | |
| [8:0] |
Delay value Minimum Setting: 0 Maximum Setting: 511 VCO clock periods Incremental Delay: 1/256th VCO clock period |
|
| Strobe Input Delay | [31:13] |
Reserved 2 |
| [12] |
Enable bit to select access to Avalon register or CSR register. 0 = Delay value is 0. CSR register is not available for this feature. 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group. |
|
| [11:10] | Reserved2 | |
| [9:0] |
Delay value Minimum Setting: 0 Maximum Setting: 1023 VCO clock periods Incremental Delay: 1/256th VCO clock period Modifying these values must be done on all lanes in a group. |
|
| Strobe Enable Phase | [31:16] | Reserved 2 |
| [15] |
Enable bit to select access to Avalon register or CSR register. 0 = Select delay value from CSR register. The CSR value is set through the Capture Strobe Phase Shift parameter during IP core instantiation. 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group. |
|
| [14:13] | Reserved2 | |
| [12:0] |
Bit [12:0]: Phase value Minimum Setting: Refer to Table 25 Maximum Setting: Refer to Table 25 Incremental Delay: 1/128th VCO clock period Modifying these values must be done on all lanes in a group. |
|
| Strobe Enable Delay | [31:16] | Reserved2 |
| [15] |
Enable bit to select access to Avalon register or CSR register. 0 = Select delay value from CSR register 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group. |
|
| [14:6] | Reserved2 | |
| [5:0] |
Delay value Minimum Setting: 0 external clock cycles Maximum Setting: 63 external memory clock cycles Incremental Delay: 1 external memory clock cycle Modifying these values must be done on all lanes in a group. |
|
| Read Valid Delay | [31:16] | Reserved2 |
| [15] |
Enable bit to select access to Avalon register or CSR register. 0 = Select delay value from CSR register 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group. |
|
| [14:7] | Reserved | |
| [6:0] |
Delay value Minimum Setting: 0 external clock cycles Maximum Setting: 127 external memory clock cycles Incremental Delay: 1 external memory clock cycle Modifying these values must be done on all lanes in a group. |
|
| Internal VREF Code | [31:6] | Reserved |
| Bit [5:0]: VREF Code Refer to Table 38 |
Example of Accessing Dynamic Reconfiguration Control Registers using Parameter Table
- Number of groups: 2. The group index is automatically set to 0x00.
- Interface ID: 0x00
- Pin width: 4
- Strobe configuration: Single ended
- Avalon controller calibration bus base address: 0x3000000
| Bit | Description | Avalon® MM Register Value |
|---|---|---|
| [30:27] | Specify the PHY Lite for Parallel Interfaces IP core interface ID. |
0x00 (Interface ID from parameter table) |
| [26:24] | Specify the Avalon controller calibration bus base address. | 0x3 |
| [23:21] | Reserved | 0x00 |
| [20:13] | Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. | 0x4b (Lane address from parameter table) |
| [12:8] | Specify the address for the physical location of a pin within a lane. | 0x04 (Strobe pin address from parameter table) |
| [7:0] | Reserved | 0xe8 |
avl_in_address[30:0] = {interface id[30:27], calibration bus address[26:24], Reserved[23:21], lanes address[20:13], pin address[12:8], reserved[7:0]}
avl_in_address[30:0] = {0x00, 0x3, 0x00, 0x4B, 0x04, 0xE8}
Calibration Guidelines
The PHY Lite for Parallel Interfaces IP core allows you to dynamically reconfigure the features of the interface. However, performing calibration is an application specific process. This section provides some general guidelines for calibrating the Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX I/O architecture.
Strobe Enable Windowing
The read pointer in the read FIFO buffer gets reset when reads are far apart (80 core clock cycles). However, the data inside the FIFO is not cleared. Therefore, an alternating pattern should be used to find the end to the strobe enable window to avoid reading stale data in the FIFO.
The strobe enable signal turns itself off on the last negative edge of the strobe. Therefore, while finding the enable window, use extra dummy pulses (either extended strobe or reads from memory without asserting the rdata_en signal) to clear the strobe enable.
Output and Strobe Enable Minimum and Maximum Phase Settings
When dynamically reconfiguring the interpolator phase settings, the values must be kept within the ranges below to ensure proper operation of the circuitry.
| VCO Multiplication Factor | Core Rate | Minimum Interpolator Phase | Maximum Interpolator Phase | ||
|---|---|---|---|---|---|
| Output | Bidirectional | Bidirectional with OCT Enabled | |||
| 1 | Full | 0x080 | 0x100 | 0x100 | 0xA80 |
| Half | 0x080 | 0x100 | 0x100 | 0xBC0 | |
| Quarter | 0x080 | 0x100 | 0x100 | 0xA00 | |
| 2 | Full | 0x080 | 0x100 | 0x180 | 0x1400 |
| Half | 0x080 | 0x100 | 0x180 | 0x1400 | |
| Quarter | 0x080 | 0x100 | 0x180 | 0x1400 | |
| 4 | Full | 0x080 | 0x100 | 0x280 | 0x1FFF |
| Half | 0x080 | 0x100 | 0x280 | 0x1FFF | |
| Quarter | 0x080 | 0x100 | 0x280 | 0x1FFF | |
| 8 | Full | 0x080 | 0x100 | 0x480 | 0x1FFF |
| Half | 0x080 | 0x100 | 0x480 | 0x1FFF | |
| Quarter | 0x080 | 0x100 | 0x480 | 0x1FFF | |
For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.
Getting Started
You can instantiate the PHY Lite for Parallel Interfaces IP core from IP Catalog in Intel® Quartus® Prime software. Intel provides an integrated parameter editor that allows you to customize this IP core to support a wide variety of applications.
This IP core is located in of the IP catalog.
Parameter Settings
| GUI Name | Values | Default Values | Description |
|---|---|---|---|
| Parameter | |||
| Number of groups | 1 to 18 | 1 | Number of data and strobe groups in the interface. The value is set to 1 by default. |
| General Tab- these parameters are set on a per interface basis | |||
| Clocks | |||
| Interface clock frequency |
100 MHz - 1200 MHz |
533.0 MHz | External memory clock frequency. Note: To achieve timing closure at 534 MHz and above, use
dynamic reconfiguration to calibrate the interface. Compile your
design with
Intel®
Quartus® Prime with
accurate board skew information for final timing analysis.
|
| Use recommended PLL reference clock frequency | On, Off | On |
If you want to calculate the PLL reference clock frequency automatically for best performance, turn on this option. If you want to specify your own PLL reference clock frequency, turn off this option. |
| PLL reference clock frequency | Dependent on desired memory clock frequency | 133.25 MHz | PLL reference clock frequency. You must feed a
clock of this frequency to the PLL reference clock input of the memory
interface. Note: There is no minimum range, but the maximum output
frequency is 1600 MHz, limited by the clock network.
The minimum range for the ref_clk
signal is 10 MHz but the maximum is dependent on the speed
grade.
|
| VCO clock frequency | Calculated internally by PLL | 1066.0 MHz | The frequency of this clock is calculated internally by the PLL based on the interface clock and the core clock rate. |
| Clock rate of user logic | Full, Half, Quarter | Quarter | Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800 MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200 MHz. |
| Specify additional output clocks based on existing PLL | On, Off | Off | Exposes additional output clocks from the existing
PLL. Important:
PHY Lite for Parallel Interfaces in
Intel®
Arria® 10 and
Intel®
Cyclone® 10 GX devices do not support exposing additional
output clocks when VCO frequency is below 600 MHz.
|
|
Output Clocks
Note: These parameters are available only if the
Specify additional output clocks
based on existing PLL parameter is turned
on
|
|||
| Number of additional clocks | 0 to 4 | 0 | Specifies the number of additional clocks to be
exposed. Important:
PHY Lite for Parallel Interfaces in
Intel®
Arria® 10 and
Intel®
Cyclone® 10 GX devices do not support exposing additional
output clocks when VCO frequency is below 600 MHz.
|
| outclk[4:0] (Reserved) | — | — | PLL output clocks with the flag (Reserved) in the QSYS GUI are reserved for PHY Lite for Parallel Interfaces IP core internal functionality. |
| Desired Frequency | — | 133.25 MHz | Specifies the output clock frequency of the corresponding output clock port, outclk[], in MHz. The minimum and maximum values depend on the device used. The PLL only reads the numerals in the first six decimal places. |
| Actual Frequency | — | 133.25 MHz | Allows you to select the actual output clock frequency from a list of achievable frequencies. |
| Phase shift units | ps or degrees | ps | Specifies the phase shift unit for the corresponding output clock port, outclk[], in picoseconds (ps) or degrees. |
| Phase shift | — | 469.0 ps | Specifies the requested value for the phase shift. The default value is 0 ps. |
| Actual phase shift | — | 469.0 ps | Allows you to select the actual phase shift from a list of achievable phase shift values. The default value is the closest achievable phase shift to the desired phase shift. |
| Desired duty cycle | 0.0–100.0 | 50.0 % | Specifies the requested value for the duty cycle. |
| Actual duty cycle | — | 50.0 % | Allows you to select the actual duty cycle from a list of achievable duty cycle values. The default value is the closest achievable duty cycle to the desired duty cycle. |
| Dynamic Reconfiguration | |||
| Use dynamic reconfiguration | On, Off | Off | Exposes an Avalon-MM interface, allowing you to control the configuration of the PHY Lite for Parallel Interfaces IP core settings. |
| First PHYLite Instance in the Avalon Chain | On, Off | On |
Select this parameter if this IP core instance is the first instance in the Avalon chain, connected to the master. This parameter is only available when you select Use dynamic reconfiguration . Important: Do not select this parameter
if there is an External Memory InterfaceIP core selected as the first instance in the chain, available
in the same column.
Only available in PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core. |
| Interface ID | — | 0 | The ID used to identify this interface in the I/O column over the Avalon-MM bus. |
| I/O Settings | |||
| I/O standard |
SSTL-12 SSTL-125 SSTL-135 SSTL-15 SSTL-15 Class I SSTL-15 Class II SSTL-18 Class I SSTL-18 Class II 1.2-V-HSTL Class I 1.2-V-HSTL Class II 1.5-V-HSTL Class I 1.5-V-HSTL Class II 1.8-V-HSTL Class I 1.8-V-HSTL Class II 1.2-V POD 1.2-V 1.5-V 1.8-V None |
SSTL-15 Class I |
Specifies the I/O standard of the interface's strobe and data pins written to the .qip file of the IP instance. When you choose None, the I/O standard is unspecified in the generated IP. |
| Reference clock I/O configuration |
Single-ended, LVDS with on-chip termination, LVDS without on-chip termination |
Single-ended |
Specify the reference clock I/O configuration. |
| General Settings | |||
| Fast simulation model | On, Off | Off |
Turn on this option to reduce PHY Lite for Parallel Interfaces IP simulation time. Note: This option is preliminarily supported in
Intel®
Quartus® Prime v18.1.
|
| Group <x> - these parameters are set on a per group basis | |||
| Group <x> Parameter Settings | |||
| Copy parameters from another group | On, Off | Off | Select this option when you want to copy the
parameter settings from another group. Set Number of groups to more than 1 to enable this option. |
| Group | 1 - 17 | 1 | Choose the group index that you want as the
parameter settings source. The changes made to the source is updated
automatically to all the target groups. You can only choose the group index which the parameter settings are not copied from another group. Set Number of groups to more than 1 to enable this option. |
|
Group
<x> Pin Settings
Note: These parameters are disabled when Copy parameters from another group
is enabled.
|
|||
| Pin type | Input, Output, Bidirectional | Bidirectional | Direction of data pins. This value is set to Bidirectional by default. |
| Pin width | 1 to 48 | 9 | Number of pins in this data/strobe group. A data width up to 48 is achievable if no strobe is used in the group. The number of strobes is controlled by the Use output strobe, Strobe configuration and Use separate capture strobe parameters. |
| DDR/SDR | DDR, SDR | DDR | Double/single data rate. |
|
Group
<x> Input Path Settings
Note: These parameters are disabled when Copy parameters from another group
is enabled.
|
|||
| Read latency | 1 to 63 external interface clock cycles | 7 | Expected read latency of the external device in
memory clock cycles. For example, a design with an external clock frequency of 533 MHz in half-rate has a valid read latency range of 5 to 63 external interface clock cycles. Refer to Table 27 for minimum read latency settings based on FPGA core clock rate . |
| Swap capture strobe polarity | On, Off | Off | Internally swap the negative and positive capture strobe input pins. This feature is only available for complementary strobe configurations. |
| Capture strobe phase shift | 0, 45, 90, 135, 180 | 90 | Internally phase shift the input strobe relative to input data. |
|
Group <x> Output Path Settings
Note: These parameters are disabled when Copy parameters from another group
is enabled.
|
|||
| Write latency | 0 to 3 (maximum value is dependent on the rate) | 0 | Additional delay added to the output data in memory
clock cycles. Refer to Table 28 for write latency settings based on FPGA core clock rate. |
| Use output strobe | On, Off | On | Use an output strobe. |
| Output strobe phase | 0, 45, 90, 135, 180 | 90 | Phase shift of the output strobe relative to the output data. |
|
Group <x> General Data Settings
Note: These parameters are disabled when Copy parameters from another group
is enabled.
|
|||
| Data configuration | Single ended, Differential (available only for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices) | Single ended |
Selects the type of data. Single ended data type uses one pin. Differential data type uses 2 pins. PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core does not support differential data pins. Refer to I/O Standards for a list of supported I/O standards. |
|
Group <x> General Strobe Settings
Note: These parameters are disabled when Copy parameters from another group
is enabled.
|
|||
| Strobe configuration | Single ended, Differential, Complementary | Single ended |
Select the type of strobe. A single ended strobe uses one pin, which reduces the maximum possible number of data pins in the group to 47. Differential/complementary strobe types use 2 pins, which reduces the maximum possible number of data pins in the group to 46. Note: The differential strobe configuration uses a
differential input buffer, which produces a single clock for the
capture DDIO and read FIFO. The complementary strobe configuration
uses two single-ended input buffers and clocks the data into the
capture DDIO and read FIFO using both clocks (as required by
protocols such as QDRII). The output path functionality is the same.
Refer to I/O Standards for a list of supported I/O standards. |
| Use separate strobes | On, Off | Off |
Separate the bidirectional strobe into input and output strobe pins. Use separate strobes is only available for a bidirectional data group with the output strobe enabled. |
|
Group <x> OCT Settings
Note: These parameters are disabled when Copy parameters from another group
is enabled.
|
|||
| OCT enable size |
0 - 15 ( Intel® Stratix® 10 devices) 0 - 4 ( Intel® Arria® 10 and Intel® Cyclone® 10 GX devices) |
1 | Specifies the delay between the OCT enable signal
assertion and the dqs_enable signal assertion. You must set a value that
is large enough to ensure that the OCT is turn on before sampling input
data. Note: For
Intel®
Quartus® Prime
software version prior to 17.0, refer to related information for
known issue.
|
| Expose termination ports | On, Off | Off |
Turn on to expose the series and parallel termination ports to connect separate OCT block. To enable this option, turn off Use Default OCT Values parameter and select a value for Input OCT Value or Output OCT Value parameters. |
| Use Default OCT Values | — |
Use default OCT values based on the I/O standard parameter setting. |
|
| Input OCT Value | No termination, <n> ohm with calibration | No termination |
Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to I/O Standards. This option is available when the Use Default OCT Values option is disabled. |
| Output OCT Value | No termination, <n> ohm with calibration, <n> with no calibration | No termination |
Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to I/O Standards supported termination values. This option is available when the Use Default OCT Values option is disabled. |
|
Group <x> Timing Settings
Note: These parameters are disabled when Copy parameters from another group
is enabled.
|
|||
| Generate Input Delay Constraints for this group | On, Off | On | Instructs SDC to generate set_input_delay constraints for this group. |
| Input Strobe Setup Delay Constraint | Constraint in ns | 0.03 ns | Specifies the group's input setup delay constraint against the input strobe. |
| Input Strobe Hold Delay Constraint | Constraint in ns | 0.03 ns | Specifies the group's input hold delay constraint against the input strobe. |
| Inter Symbol Interference of the Read Channel | Constraint in ns | 0.09 ns | Specifies the Inter Symbol Interference value for
DQS signal of read channel. Specify a positive value to decrease the setup and hold slack by half of the entered value. |
| Generate Output Delay Constraints for this group | On, Off | On | Instructs SDC to generate set_output_delay constraints for this group. |
| Output Strobe Setup Delay Constraint | Constraint in ns | 0.03 ns | Specifies the group's output setup delay constraint against the input strobe. |
| Output Strobe Hold Delay Constraint | Constraint in ns | 0.03 ns | Specifies the group's output hold delay constraint against the input strobe. |
| Inter Symbol Interference of the Write Channel | Constraint in ns | 0.09 ns | Specifies the Inter Symbol Interference value for
DQS signal of write channel. Specify a positive value to decrease the setup and hold slack by half of the entered value. |
|
Group <x> Dynamic Reconfiguration Timing Settings
Note: These parameters are disabled when Copy parameters from another group
is enabled.
|
|||
| Dynamic Reconfiguration Read Deskew Algorithm | DQ Per-Bit Deskew, DQ Group Deskew, Custom Deskew | DQ Per-Bit Deskew | Specifies the Read Deskew algorithm for Timing Analyzer to use when performing
I/O timing analysis:
You must select Use dynamic reconfiguration option to enable this parameter. |
| Setup Slack Recoverable of Custom Read Deskew Algorithm | Constraint in ns | 0.0 ns | Specifies the amount of positive setup slack
available based on your custom read deskew algorithm. This parameter is available with the conditions:
|
| Hold Slack Recoverable of Custom Read Deskew Algorithm | Constraint in ns | 0.0 ns | Specifies the amount of positive hold slack
available based on your custom read deskew algorithm. This parameter is available with the conditions:
|
| Dynamic Reconfiguration Write Deskew Algorithm | DQ Per-Bit Deskew, DQ Group Deskew, Custom Deskew | DQ Per-Bit Deskew | Specifies the Write Deskew algorithm for Timing Analyzer to use when performing
I/O timing analysis:
You must select Use dynamic reconfiguration option to enable this parameter. |
| Setup Slack Recoverable of Custom Write Deskew Algorithm | Constraint in ns | 0.0 ns | Specifies the amount of positive setup slack
available based on your custom write deskew algorithm. This parameter is available with the conditions:
|
| Hold Slack Recoverable of Custom Write Deskew Algorithm | Constraint in ns | 0.0 ns | Specifies the amount of positive hold slack
available based on your custom write deskew algorithm. This parameter is available with the conditions:
|
Read Latency
| Core Clock Rate | VCO Multiplier Factor | Read Latency (External Memory Clock Cycle) |
|---|---|---|
| Full rate | 1 | 4 |
| 2 | 4 | |
| 4 | 3 | |
| 8 | 3 | |
| Half rate | 1 | 5 |
| 2 | 5 | |
| 4 | 4 | |
| 8 | 4 | |
| Quarter rate | 1 | 7 |
| 2 | 7 | |
| 4 | 7 | |
| 8 | 7 |
Write Latency
| Core Clock Rate | VCO Multiplier Factor | Write Latency (External Memory Clock Cycle) |
|---|---|---|
| Full rate | 1 | 0 |
| 2 | 0 | |
| 4 | 0 | |
| 8 | 0 | |
| Half rate | 1 | 1 |
| 2 | 1 | |
| 4 | 1 | |
| 8 | 1 | |
| Quarter rate | 1 | 3 |
| 2 | 3 | |
| 4 | 3 | |
| 8 | 2 |
Signals
Clock and Reset Interface Signals
| Signal Name | Direction | Width | Description |
|---|---|---|---|
| ref_clk | Input | 1 | Reference clock for the PLL. The reference clock must be synchronous with strobe_in to ensure the dqs_enable signal is in-sync with strobe_in. |
| reset_n | Input | 1 | Resets the interface. This signal is asynchronous. |
| interface_locked | Output | 1 | Interface locked signal from PHY Lite for Parallel Interfaces IP core to Intel FPGA core.
This signal indicates that the PLL and PHY circuitry are locked. Data transfer should starts after the assertion of this signal. |
| core_clk_out | Output | 1 | Use this core clock in the
core-to-periphery transfer of soft logic data and control signals. The core_clk_out frequency depends on the interface frequency and clock rate of user logic parameter. |
| pll_extra_clock[0..3] | Output | 4 | These are the additional output clock
signals generated by PHY Lite for Parallel Interfaces IP core when you enable Specify additional output clocks based on existing
PLL parameter. Important:
PHY Lite for Parallel Interfaces in
Intel®
Arria® 10 and
Intel®
Cyclone® 10 GX devices do not support exposing additional
output clocks when VCO frequency is below 600 MHz.
|
| pll_locked | Output | 1 | This is the locked signal for the additional output clocks generated by the IP core. |
Output Path Signals
| Signal Name | Direction | Width | Description |
|---|---|---|---|
| oe_from_core | Input |
Quarter-rate: 4 x PIN_WIDTH Half-rate: 2 x PIN_WIDTH Full-rate: 1 x PIN_WIDTH |
Output enable signal from Intel FPGA core. Synchronous to the core_clk output from the IP core. |
| data_from_core | Input |
Quarter rate-DDR: 8 x PIN_WIDTH Half-rate DDR: 4 x PIN_WIDTH Full-rate DDR: 2 x PIN_WIDTH Quarter-rate SDR: 4 x PIN_WIDTH Half-rate SDR: 2 x PIN_WIDTH Full-rate SDR: 1 x PIN_WIDTH |
Data signal from Intel FPGA core. Synchronous to the core_clk output from the IP core. |
| strobe_out_in | Input |
Quarter-rate: 8 Half-rate: 4 Full-rate: 2 |
Strobe signal from Intel FPGA core. Synchronous to the core_clk output from the IP core. Note: This path is always DDR.
|
| strobe_out_en | Input |
Quarter-rate: 4 Half-rate: 2 Full-rate: 1 |
Strobe output enable from Intel FPGA core. Synchronous to the core_clk output from the IP core. |
| data_out/data_io | Output/Bidirectional |
|
Data output from PHY Lite for Parallel Interfaces IP core. Synchronous to the
strobe_out or strobe_io output from the IP core. If the Pin Type parameter is set to Output, the data_out signals are used. If the Pin Type parameter is set to Bidirectional, the data_io signals are used. Note:
PHY Lite for Parallel Interfaces
Intel®
Stratix® 10 FPGA IP core does not
support differential data pins.
|
| data_out_n/data_io_n | Output/Bidirectional | 1 to 24 | Negative data output from PHY Lite for Parallel Interfaces IP core is enabled when data
configuration is set to Differential. Data is synchronous to the strobe_out or strobe_io output from the IP core. If the Pin Type is set to Output, the data_out_n
ports are used. If the pin type is set to Bidirectional, the data_io_n
ports are used. Note:
PHY Lite for Parallel Interfaces
Intel®
Stratix® 10 FPGA IP core does not
support differential data pins.
|
| strobe_out/strobe_io | Output/Bidirectional | 1 | Positive output strobe fromPHY Lite for Parallel Interfaces IP core. If the Pin Type is set to Output, the strobe_out signal is used. If the Pin Type is set to Bidirectional the strobe_io signal is used. The Use Separate Strobes parameter forces the use of the strobe_out signal with a Bidirectional Pin Type. |
| strobe_out_n/strobe_io_n | Output/Bidirectional | 1 | Negative output strobe fromPHY Lite for Parallel Interfaces IP core. This is used if the Strobe Configuration is set to Differential or Complementary. If the Pin Type is set to Output, the strobe_out_n signal is used. If the Pin Type is set to Bidirectional, the strobe_io_n signal is used. The Use Separate Strobes parameter forces the use of the strobe_out_n signal with a Bidirectional Pin Type. |
Input Path Signals
| Signal Name | Direction | Width | Description |
|---|---|---|---|
| data_to_core | Output |
Quarter-rate DDR: 8 x PIN_WIDTH Half-rate DDR: 4 x PIN_WIDTH Full-rate DDR: 2 x PIN_WIDTH Quarter-rate SDR: 4 x PIN_WIDTH Half-rate SDR: 2 x PIN_WIDTH Full-rate SDR: 1 x PIN_WIDTH |
Output data to the Intel FPGA core. Valid on rdata_valid. Synchronous to the core_clk output from the PHY Lite for Parallel Interfaces IP core. |
| rdata_en | Input |
Quarter-rate: 4 Half-rate: 2 Full-rate: 1 |
This signal represents the number of
expected words to read from the external
device.
This signal is set to high after a read command is issued. Synchronous to the core_clk output from thePHY Lite for Parallel Interfaces IP core. When using the IP as a receiver, assert this signal after interface_locked signal is asserted and strobe_inis stable. |
| rdata_valid | Output |
Quarter-rate: 4 Half-rate: 2 Full-rate: 1 |
This signal
determines which data are valid when reading from Read
FIFO. Delayed by READ_LATENCY with margin and aligned to the core clock
rate. For example, in quarter-rate, the delay is a multiple of 4
external clock cycles. Synchronous to the core_clk output from the PHY Lite for Parallel Interfaces IP core. |
|
data_in/
data_io |
Input/Bidirectional |
1 to 48 if data configuration is Single Ended 1 to 24 if data configuration is Differential ( Intel® Arria® 10 and Intel® Cyclone® 10 GX devices) |
Input and output data from/to external
device. Synchronous to the strobe_in or strobe_io
input. The first data_in must be associated with positive edge of
strobe_in/strobe_io. If the pin type is set to Input, the data_in ports are used. If the pin type is set to bidirectional, the data_io ports are used. Note:
PHY Lite for Parallel Interfaces
Intel®
Stratix® 10 FPGA IP core does not
support differential data pins.
|
|
data_in_n/
data_io_n |
Input/Bidirectional | 1 to 24 | Negative data input/output from external device enabled when
data configuration is set to Differential. Data is synchronous to the strobe_in or strobe_io input. If the pin type is set to Input, the data_in_n ports are used. If the pin type is set to
bidirectional, the data_io_n ports are used. Note:
PHY Lite for Parallel Interfaces
Intel®
Stratix® 10 FPGA IP core does not
support differential data pins.
|
| strobe_in/strobe_io | Input/Bidirectional | 1 |
Input and output strobe from/to external device. If the pin type is set to Input, the strobe_in signal is used. If the pin type is set to Bidirectional, the strobe_io signal is used. |
| strobe_in_n/strobe_io_n | Input/Bidirectional | 1 | Negative strobe from/to external device. This is used if the Strobe Configuration parameter is set to Differential or Complementary. If the pin type is set to Input, the strobe_in_n signal is used. If the pin type is set to Bidirectional, the strobe_io_n signal is used. |
Avalon Configuration Bus Interface Signals
The PHY Lite for Parallel Interfaces IP core exposes the Avalon-MM slave and Avalon-MM master interfaces when you perform dynamic reconfiguration. Connect the Avalon-MM slave to either a master in the core or the master interface of either an PHY Lite for Parallel Interfaces IP core or the External Memory Interface IP core to be placed in the same column. You can only connect the master interface to the slave interface of a PHY Lite for Parallel Interfaces IP core or External Memory Interface IP core to be placed in the same column.
| Signal Name | Direction | Width | Description |
|---|---|---|---|
| avl_clk | Input | 1 |
Avalon interface clock. Maximum Avalon-MM interface clock for PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core is 167 MHz. |
| avl_reset_n | Input | 1 | Reset input synchronous to avl_clk. |
| avl_read | Input | 1 | Read request from io_aux. This signal is synchronous to the avl_clk input. |
| avl_write | Input | 1 | Write request from io_aux. This signal is synchronous to the avl_clk input. |
| avl_byteenable | Input | 4 | Controls which bytes should be written on avl_writedata. |
| avl_writedata | Input | 32 | Write data from io_aux. This signal is synchronous to the avl_clk input. |
| avl_address | Input |
31 ( Intel® Stratix® 10 devices) 28 ( Intel® Arria® 10 and Intel® Cyclone® 10 GX devices) |
Address from io_aux. This signal is synchronous to the avl_clk input. |
| avl_readdata | Output | 32 | Read data to io_aux. This signal is synchronous to the avl_clk input. |
| avl_writedata | Input | 32 | Write data from io_aux. This signal is synchronous to the avl_clk input. |
| avl_readdata_valid | Output | 1 | Indicates that read data has returned. |
| avl_waitrequest | Output | 1 | Stalls upstream logic when it is asserted. |
| Signal Name | Direction | Width | Description |
|---|---|---|---|
| avl_out_clk | Output | 1 | Connect this signal to the input Avalon interface of another PHY Lite for Parallel Interfaces IP core or the Arria 10 External Memory Interfaces IP. |
| avl_out_reset_n | Output | 1 | Connect this signal to the input Avalon interface of another PHY Lite for Parallel Interfacess IP core or the External Memory Interfaces Intel® Arria® 10 FPGA IP. |
| avl_out_read | Output | 1 | Indicates read transaction. |
| avl_out_write | Output | 1 | Indicates write transaction. |
| avl_out_byteenable | Output | 4 | Controls which bytes should be written on avl_out_writedata. |
| avl_out_writedata | Output | 32 | The data packet associated with the write transaction. |
| avl_out_address | Output |
31 ( Intel® Stratix® 10 devices) 28 ( Intel® Arria® 10 and Intel® Cyclone® 10 GX devices) |
Avalon address (in byte granularity). Value is identical to avl_address but with zeroes padded on the LSBs. |
| avl_out_readdata | Input | 32 | The data packet associated with avl_out_readdata_valid. |
| avl_out_readdata_valid | Input | 1 | Indicates that read data has returned. |
| avl_out_waitrequest | Input | 1 | Stalls upstream logic when it is asserted. |
I/O Standards
The PHY Lite for Parallel Interfaces IP core allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.
| I/O Standard | Valid Input Terminations (Ω) | Valid Output Terminations (Ω) | RZQ (Ω) | Differential/Complementary I/O Support Important:
PHY Lite for Parallel Interfaces
Intel®
Stratix® 10 FPGA IP core does not support
differential data pins. |
|---|---|---|---|---|
| SSTL-12 | 60, 120 | 40, 60,240 | 240 | Yes |
| SSTL-125 | 40, 60, 120 | 34, 40 | 240 | Yes |
| SSTL-135 | 40, 60, 120 | 34, 40 | 240 | Yes |
| SSTL-15 | 40, 60, 120 | 34, 40 | 240 | Yes |
| SSTL-15 Class I | 50 | 50 | 100 | Yes |
| SSTL-15 Class II | 50 | 25 | 100 | Yes |
| SSTL-18 Class I | 50 | 50 | 100 | Yes |
| SSTL-18 Class II | 50 | 25 | 100 | Yes |
| 1.2-V HSTL Class I | 50 | 50 | 100 | Yes |
| 1.2-V HSTL Class II | 50 | 25 | 100 | Yes |
| 1.5-V HSTL Class I | 50 | 50 | 100 | Yes |
| 1.5-V HSTL Class II | 50 | 25 | 100 | Yes |
| 1.8-V HSTL Class I | 50 | 50 | 100 | Yes |
| 1.8-V HSTL Class II | 50 | 25 | 100 | Yes |
| 1.2-V POD | 34, 40, 48, 60, 80, 120, 240 | 34, 40, 48, 60 | 240 | Yes |
| 1.2-V | — | — | — | No |
| 1.5-V | — | — | — | No |
| 1.8-V | — | — | — | No |
| I/O Standard | Valid Input Terminations (Ω) 3 | Valid Output Calibrated/Uncalibrated Terminations (Ω)3 | RZQ (Ω) 4 | Differential/Complementary I/O Support |
|---|---|---|---|---|
| SSTL-12 5 | 60, 120 | 40, 60 | 240 | Yes |
| SSTL-125 5 | 60, 120 | 34, 40 | 240 | Yes |
| SSTL-135 5 | 60, 120 | 34, 40 | 240 | Yes |
| SSTL-15 5 | 60, 120 | 34, 40 | 240 | Yes |
| SSTL-15 Class I 6 | 0, 50 | 0, 50 | 100 | Yes |
| SSTL-15 Class II6 | 0, 50 | 0, 25 | 100 | Yes |
| SSTL-18 Class I6 | 0, 50 | 0, 50 | 100 | Yes |
| SSTL-18 Class II6 | 0, 50 | 0, 25 | 100 | Yes |
| 1.2-V HSTL Class I6 | 0, 50 | 0, 50 | 100 | Yes |
| 1.2-V HSTL Class II6 | 0, 50 | 0, 25 | 100 | Yes |
| 1.5-V HSTL Class I6 | 0, 50 | 0, 50 | 100 | Yes |
| 1.5-V HSTL Class II6 | 0, 50 | 0, 25 | 100 | Yes |
| 1.8-V HSTL Class I6 | 0, 50 | 0, 50 | 100 | Yes |
| 1.8-V HSTL Class II6 | 0, 50 | 0, 25 | 100 | Yes |
| 1.2-V POD | 34, 40, 48, 60, 80, 120, 240 | 34, 40, 48, 60 | 240 | Yes |
| 1.2-V | — | — | — | No |
| 1.5-V | — | — | — | No |
| 1.8-V | — | — | — | No |
| I/O Standard | Valid Input Terminations (Ω) 3 | Valid Output Calibrated/Uncalibrated Terminations (Ω)3 | RZQ (Ω) 4 | Differential/Complementary I/O Support |
|---|---|---|---|---|
| SSTL-12 7 | 60, 120 | 40, 60 | 240 | Yes |
| SSTL-125 7 | 60, 120 | 34, 40 | 240 | Yes |
| SSTL-135 7 | 60, 120 | 34, 40 | 240 | Yes |
| SSTL-15 7 | 60, 120 | 34, 40 | 240 | Yes |
| SSTL-15 Class I 8 | 0, 50 | 0, 50 | 100 | Yes |
| SSTL-15 Class II8 | 0, 50 | 0, 25 | 100 | Yes |
| SSTL-18 Class I8 | 0, 50 | 0, 50 | 100 | Yes |
| SSTL-18 Class II8 | 0, 50 | 0, 25 | 100 | Yes |
| 1.2-V HSTL Class I8 | 0, 50 | 0, 50 | 100 | Yes |
| 1.2-V HSTL Class II8 | 0, 50 | 0, 25 | 100 | Yes |
| 1.5-V HSTL Class I8 | 0, 50 | 0, 50 | 100 | Yes |
| 1.5-V HSTL Class II8 | 0, 50 | 0, 25 | 100 | Yes |
| 1.8-V HSTL Class I8 | 0, 50 | 0, 50 | 100 | Yes |
| 1.8-V HSTL Class II8 | 0, 50 | 0, 25 | 100 | Yes |
| 1.2-V POD | 34, 40, 48, 60, 80, 120, 240 | 34, 40, 48, 60 | 240 | Yes |
| 1.2-V | — | — | — | No |
| 1.5-V | — | — | — | No |
| 1.8-V | — | — | — | No |
Input Buffer Reference Voltage (VREF)
The POD I/O standard allows configurable VREF. By default, the externally provided VREF is used and using an internal VREF requires the following .qsf assignments:
set_instance_assignment -name VREF_MODE <mode> -to <pin_name>
| VREF Mode | Description |
|---|---|
| EXTERNAL | Use the external VREF. This is the default. |
| CALIBRATED | Use internal VREF generated using VREF codes from the Avalon-MM reconfiguration bus. |
| VCCIO_45 | Use internal VREF generated using static VREF code. VREF is 45% of VCCIO |
| VCCIO_50 | Use internal VREF generated using static VREF code. VREF is 50% of VCCIO |
| VCCIO_55 | Use internal VREF generated using static VREF code. VREF is 55% of VCCIO |
| VCCIO_65 | Use internal VREF generated using static VREF code. VREF is 65% of VCCIO |
| VCCIO_70 | Use internal VREF generated using static VREF code. VREF is 70% of VCCIO |
| VCCIO_75 | Use internal VREF generated using static VREF code. VREF is 75% of VCCIO |
Calibrated VREF Settings
| avl_writedata[5:0] | % of VCCIO |
|---|---|
| 000000 | 60.00% |
| 000001 | 60.64% |
| 000010 | 61.28% |
| 000011 | 61.92% |
| 000100 | 62.56% |
| 000101 | 63.20% |
| 000110 | 63.84% |
| 000111 | 64.48% |
| 001000 | 65.12% |
| 001001 | 65.76% |
| 001010 | 66.40% |
| 001011 | 67.04% |
| 001100 | 67.68% |
| 001101 | 68.32% |
| 001110 | 68.96% |
| 001111 | 69.60% |
| 010000 | 70.24% |
| 010001 | 70.88% |
| 010010 | 71.52% |
| 010011 | 72.16% |
| 010100 | 72.80% |
| 010101 | 73.44% |
| 010110 | 74.08% |
| 010111 | 74.72% |
| 011000 | 75.36% |
| 011001 | 76.00% |
| 011010 | 76.64% |
| 011011 | 77.28% |
| 011100 | 77.92% |
| 011101 | 78.56% |
| 011110 | 79.20% |
| 011111 | 79.84% |
| 100000 | 80.48% |
| 100001 | 81.12% |
| 100010 | 81.76% |
| 100011 | 82.40% |
| 100100 | 83.04% |
| 100101 | 83.68% |
| 100110 | 84.32% |
| 100111 | 84.96% |
| 101000 | 85.60% |
| 101001 | 86.24% |
| 101010 | 86.88% |
| 101011 | 87.52% |
| 101100 | 88.16% |
| 101101 | 88.80% |
| 101110 | 89.44% |
| 101111 | 90.08% |
| 110000 | 90.72% |
| 110001 | 91.36% |
| 110010 | 92.00% |
| 110011 -> 111111 | Reserved |
On-Chip Termination (OCT)
PHY Lite for Parallel Interfaces IP core provides valid OCT settings for each group (refer to I/O Standards). These settings are written to the .qip of the instance during generation. If you select an I/O standard that supports OCT in the General tab, you can use the OCT blocks provided in the Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
You can instantiate the OCT block in one of two ways:
- Using RZQ_GROUP assignment in the assignment editor, or
- Manual insertion of OCT block
RZQ_GROUP Assignment
The RZQ_GROUP assignment creates the OCT Intel FPGA IP core without modifying the RTL. The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the Fitter creates the pin name along with the OCT Intel FPGA IP core and its corresponding connections. This allows you to create a group of pins to be calibrated by an existing or non-existing OCT and the Fitter ensures the legality of the design. You must associate the terminated pins of the PHY Lite for Parallel Interfaces IP core instance with an RZQ pin at the system level manually.
Use the following steps to set RZQ pin locations for the PHY Lite for Parallel Interfaces IP:
Manual Insertion of OCT Block
You may also instantiate the OCT Intel FPGA IP Core separately in your project and connect the termination ports to the PHY Lite for Parallel Interfaces.
- Expose the PHY Lite for Parallel Interfaces termination ports by disable Use Default OCT Values.
- Select the available OCT values in the Input
OCT Value parameter. This will display the Expose termination ports parameter.Note: For supported input and output OCT values, refer to I/O Standards.
- Select Expose termination ports to expose the termination ports in the IP.
- Connect the termination ports to a OCT Intel FPGA IP core either in power-up or user mode.
Design Guidelines
Guidelines: Group Pin Placement
- All groups in a PHY Lite for Parallel Interfaces IP core must be placed across a contiguous set of lanes. The number of lanes depends on the number of pins used by the group.
- Two groups, from either the same or different PHY Lite for Parallel Interfaces IP core, cannot share an I/O lane.
- For PHY Lite for Parallel Interfaces IP core instance that spans more than one I/O bank, all groups in the interface must be placed across a contiguous set of banks within an I/O column. The number of I/O banks required depends on the memory interface width.
- Pins that are not used in an I/O bank are available as general purpose I/O (GPIO) pins.
- To constrain groups from separate PHY Lite for Parallel Interfaces IP core instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies, and the same voltage settings. The number of I/O banks must be at least as many as the number of PHY Lite for Parallel Interfaces IP core interfaces.
- A reference clock network can only span across maximum of 6 I/O banks.
- You cannot share the OCT termination block across the I/O column. You can associate the terminated pins of the PHY Lite for Parallel Interfaces IP core instance with an RZQ pin through RZQ_GROUP assignment.
| Number of Pins in Group | Valid DQS Group in a Bank | Valid Index in a Bank |
|---|---|---|
| 1-12 | DQS for X8/X9 | {0-11}/{12-23}/{24-35}/{36-47} |
| 13-24 | DQS for X16/X18 | {0-23}/{24-47} |
| 25-48 | DQS for X32/X36 | {0-47} |
Reference Clock
You are recommended to source the reference clock to the PHY Lite for Parallel Interfaces IP core from a dedicated clock pin. Use the clock pin in one of the I/O banks used by the PHY Lite for Parallel Interfaces IP core. You must use contiguous I/O banks to implement multiple interfaces (consisting of a combination of External Memory Interface and PHY Lite for Parallel Interfaces IP cores). If you use the same reference clock for these interfaces, place the reference clock in any of the contiguous I/O banks.
Reset
set_location_asignment <PIN_NUMBER> -to <signal_name>
Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank
You can instantiate multiple PHY Lite for Parallel Interfaces Intel FPGA IPs within an I/O column. To constrain groups from separate PHY Lite for Parallel Interfaces IP core instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies and the same voltage settings.
Dynamic Reconfiguration
If you are using the dynamic reconfiguration feature, all interfaces of the External Memory Interfaces and PHY Lite for Parallel Interfaces IP cores in the same I/O column must share the reset signal. Multiple IP cores requiring Avalon core access require daisy chain connectivity.
Timing
The Intel® Quartus® Prime software generates the required timing constraints to analyze the timing of the PHY Lite for Parallel Interfaces IP core on the all Intel FPGA devices.
Timing Components
| Circuit Category | Timing Paths | Source | Destination | Description |
|---|---|---|---|---|
| Source synchronous and optionally calibrated 9 | Read Path | Memory Device | DQ Capture Register | Source synchronous timing
paths—paths where clock and data signals are passed from the transmitting
devices to the receiving devices.
Optionally calibrated paths—paths with delay elements that are dynamically reconfigurable to achieve timing closure, especially at higher frequency, and to maximize the timing margins. You can calibrate these paths by implementing an algorithm and turning on the optional dynamic reconfiguration feature. An example of the calibrated path is the FPGA to memory device write path, in which you can dynamically reconfigure the delay elements to, for instance, compensate the skew due to process voltage temperature variation. |
| Source synchronous and optionally calibrated 9 | Write Path | FPGA DQ/DQS | Memory Device | |
| Internal FPGA | Core to PHY Lite for Parallel Interfaces IP Path | Core Registers | Write FIFO | The internal FPGA paths are paths in the FPGA fabric. The Timing Analyzer reports the corresponding timing margins. |
| Internal FPGA | PHY Lite for Parallel Interfaces IP to Core | Read FIFO | Core Registers |
Timing Constraints and Files
To successfully constrain the timing for PHY Lite for Parallel Interfaces IP core, the IP core generates a set of timing files. You can locate these timing files in the <variation_name> directory:
- <variation_name> .sdc
- <variation_name> _ip_parameters.tcl
- <variation_name> _pin_map.tcl
- <variation_name> _parameters.tcl
- <variation_name> _report_timing.tcl
- <variation_name> _report_timing_core.tcl
<variation_name>.sdc
You can find the location of the <variation_name> .sdc file in the .qip or .qsys, which is generated during the IP generation. The <variation_name> .sdc allows the Fitter to optimize timing margins with timing driven compilation and allows the Timing Analyzer to analyze the timing of your design.
The IP core uses <variation_name> .sdc for the following operations:
- Creating clocks on PLL inputs
- Creating generated clocks
- Calling derive_clock_uncertainty
- Creating set_output_delay and set_input_delay constraints to analyze the timing of the read and write paths
<variation_name>_parameter.tcl
- Jitter
- Simultaneous switching noise
- Calibration uncertainties
<variation_name>_ip_parameters.tcl
The <variation_name> _ip_parameters.tcl file lists the PHY Lite for Parallel Interfaces IP core parameters and is read by the <variation_name> .sdc.
<variation_name>_pin_map.tcl
The <variation_name>_pin_map.tcl is a TCL library of functions and procedures that <variation_name>.sdc uses.
<variation_name>_report_timing.tcl
- <variation_name>_ip_parameters.tcl
- <variation_name>_parameters.tcl
- <variation_name>_pin_map.tcl
- <variation_name>_report_timing_core.tcl
<variation_name>_report_timing_core.tcl
The <variation_name>_report_timing_core.tcl file is a script that <variation_name>_report_timing.tcl uses to calculate the timing slack for your variation. <variation_name>_report_timing_core.tcl runs automatically during compilation.
Timing Analysis
| Location | Description |
|---|---|
| I/O | The PHY Lite for Parallel Interfaces IP
core generation creates the appropriate generated clock settings for the
read strobe on the read path and the write strobe of the write path,
according to their strobe type (singled-ended, complementary, or
differential) and their interface type (SDR or DDR) in the following
format:
|
| FPGA | The PHY Lite for Parallel Interfaces IP
core generation creates the clock settings for the user core clock and
the periphery clock in the following formats:
The user core clock is for user core logic and the periphery clock is the clock for the PHY Lite for Parallel Interfaces IP core periphery hardware. With these clock settings, the Timing Analyzer analyzes the timing of this IP core interface transfer and within core transfer correctly. |
Timing Closure Guidelines
Timing Closure: Dynamic Reconfiguration
You can dynamically reconfigure the delay elements in the I/O to optimize process, voltage, temperature variations by implementing a calibration algorithm that modifies the input and output delays.
Timing Closure: Input Strobe Setup and Hold Delay Constraints
The Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint parameters ensure that an input to the FPGA from the an external device meets the internal FPGA setup and hold time requirements. The value of these constraints are calculated from various timing parameters such as setup and hold timing of the external device, board trace delay and clock skew.
The following figure shows the considerations required to determine the Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint values. The external device sends data and clock to the FPGA through interconnect on the board. The FPGA uses the clock signal from the external device to latch input data to the FPGA. The maximum and minimum values of the output clock TCO are values available in the external device data sheet.
The following is the derivation for Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint:
Input strobe setup delay constraint = Maximum board skew + maximum TCO Input strobe hold delay constraint = Minimum board skew + minimum TCO
where maximum board skew = maximum data trace - minimum clock trace
minimum board skew = minimum data trace - maximum clock trace
maximum TCO = DQS to DQ skew (tDQSQ)
minimum TCO = Data hold skew (tQHS)
- Input clock frequency = 100 MHz
- Board skew estimation = ± 0.03 ns
- Maximum TCO = 0.6 ns
- Minimum TCO = -0.6 ns
Input Strobe Setup Delay Constraint = 0.03 + 0.6= 0.63 ns
Input Strobe Hold Delay Constraint = -0.03 + (-0.6) = -0.63 ns
Timing Closure: Output Strobe Setup and Hold Delay Constraints
The Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint ensure that the data output from the FPGA to the external device meets the setup and hold requirements of the external device. The value of these constraints are calculated from various timing parameters such as setup and hold timing of the external device, board trace delay and clock skew.
The following figure shows the considerations required to determine the Output trobe Setup Delay Constraint and Output Strobe Hold Delay Constraint values. These constraints are depending on the clock and data traces, and setup and hold requirements of the external device. With system-centric delays, you can obtain the setup and hold requirements, clock delay, and data trace delay values for the external device through the device data sheet.
The following is the derivation for Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint:
Output strobe setup delay constraint = Maximum board skew + maximum tSU Output strobe hold delay constraint = Minimum board skew + minimum tH
where maximum board skew = maximum data trace - minimum clock trace
minimum board skew = minimum data trace - maximum clock trace
maximum tSU = clock setup time
minimum tH = clock hold time
- Input clock frequency = 100 MHz
- Board skew estimation = ± 0.03 ns
- Maximum tSU = 0.75 ns
- Minimum tH = 0.75 ns
Output Strobe Setup Delay Constraint = 0.03 + 0.75= 0.78 ns
Output Strobe Hold Delay Constraint = -0.03 - 0.75 = -0.78 ns
Timing Closure: Non Edge-Aligned Input Data
If the input data is not edge-aligned, use the following equation to calculate the new Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint values:
New Input Strobe Setup Delay Constraint Value = Clock to data skew - Input Strobe Phase Shift (nanosecond)
New Input Strobe Hold Delay Constraint Value = Clock to data skew + Input Strobe Phase Shift (nanosecond)
For example, if the memory speed is 800 MHz and the clock to data skew value is 0.1 with input data phase shift of 90°:
New Input Strobe Setup Delay Constraint value = 0.1-1.25*(90/360) = -0.2125ns.
New Input Strobe Hold Delay Constraint value = 0.1 + 1.25*(90/360) = 0.4125ns
I/O Timing Violation
It can be difficult to achieve timing closure for I/O paths at high frequency. Use the dynamic reconfiguration feature to calibrate the I/O path.
Internal FPGA Path Timing Violation
If timing violations are reported at the internal FPGA paths (such as <instance_name>_usr_clk or <instance_name>_phy_clk_*), consider the following guidelines:
If setup time violation is reported, lower the clock rate of the user logic from full-rate to half-rate, or from half-rate to quarter-rate. This reduces the frequency requirement of the IP core-to-core data transfer.
If {$::quartus(nameofexecutable) != “quartus_sta”}{
set_clock_uncertainty -from [<instance_name>_phy_clk_*] -to [<instance_name>_phy_clk_*] -hold 0.3 -add
set_clock_uncertainty -from [<instance_name>_usr_clk] -to [<instance_name>_usr_clk] -hold 0.3 -add
}
However, increasing the hold uncertainty value may cause setup timing violation at slow corner.
Design Example
The PHY Lite for Parallel Interfaces IP core is able to generate a design example that matches the same configuration chosen for the IP. The design example is a simple design that does not target any specific application; however you can use the design example as a reference on how to instantiate the IP core and what behavior to expect in a simulation.
Generate the Design Example
You can generate a design example by clicking Generating Example Design in the IP Parameter Editor.
The software generates a user defined directory in which the design example files reside.
- Variant without dynamic reconfiguration design example
- Variant with dynamic reconfiguration design example
| Design Example Variant | Design Files | Description | |
|---|---|---|---|
| Dynamic Reconfiguration | OFF | ed_synth.qsys (synthesis only) |
Consists of configurablePHY Lite for Parallel Interfaces IP core instance. |
| ed_sim.qsys (simulation only) |
Consists of sim_ctrl, agent, addr/cmd and PHY Lite for Parallel Interfaces IP core instances. Perform read and write transaction verification. |
||
| ON | ed_synth.qsys (synthesis only) |
Consists of IOAUX andPHY Lite for Parallel Interfaces IP core instances. You need to instantiate NIOS and AVL_Controller manually or create user logic to perform address translation. |
|
| phylite_debug_kit.qsys (synthesis only) |
Consists of NIOS, AVL_Controller, API functions, IOAUX and PHY Lite for Parallel Interfaces IP core instances. A recommended example design to perform dynamic reconfiguration. This design example does not support simulation. |
||
| ed_sim.qsys (simulation only) |
Consists of sim_ctrl, agent, addr/cmd, cfg_ctrl, avl_ctrl and PHY Lite for Parallel Interfaces IP core instances. This design example demonstrates dynamic reconfiguration and uses FSM to perform calibration. |
||
Design Example without Dynamic Reconfiguration
When the Enable dynamic reconfiguration option is not selected, Intel® Quartus® Prime software generates a design example of PHY Lite for Parallel Interfaces IP core without a dynamic reconfiguration module.
This design example consists of simulation and synthesis design files.
Generate the Hardware Design Example
The make_qii_design.tcl generates a synthesizable hardware design example along with a Quartus project, ready for compilation.
quartus_sh -t make_qii_design.tcl
To specify an exact device to use, run the following script:
quartus_sh -t make_qii_design.tcl [device_name]
This script generates a qii directory containing a project called ed_synth.qpf. You can open and compile this project with the Intel® Quartus® Prime software.
Generate the Simulation Design Example
The make_sim_design.tcl generates a simulation design example along with tool-specific scripts to compile and elaborate the necessary files.
To generate the design example for a Verilog or a mixed-language simulator, run the following script at the end of IP generation:
quartus_sh -t make_sim_design.tcl VERILOG
To generate the design example for a VHDL-only simulator, run the following script:
quartus_sh -t make_sim_design.tcl VHDL
This script generates a sim directory containing one subdirectory for each supported simulation tools. Each subdirectory contains the specific scripts to run simulation with the corresponding tool.
The simulation design example provides a generic example of the core and I/O connectivity for your IP configuration. Functionally, the simulation iterates over each group in your configured IP and performs basic reads/writes to an associated agent (one per group) in the testbench. A simple one group PHY Lite for Parallel Interfaces IP core instantiation in the testbench is used for basic address and command outputs to the agent. A side bus between the sim_ctrl and the agents is used to check that the reads and writes are valid.
Dynamic Reconfiguration Design Examples
When you select the Use dynamic reconfiguration option and click Generate Example Design, Intel® Quartus® Prime software generates two design examples:
- Dynamic reconfiguration with debug kit design example.
- Dynamic reconfiguration with configuration control module.
Dynamic Reconfiguration with Debug Kit
This design example provides you a synthesizable system capable to perform dynamic calibration for PHY Lite for Parallel Interfaces IP core in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
- A fully configurable PHY Lite for Parallel Interfaces IP core
- An Avalon controller to perform address translation
- A NIOS II processor to perform dynamic calibration for PHY Lite for Parallel Interfaces IP core
- A set of application program interface (API) to configure delay chains for PHY Lite for Parallel Interfaces Interface IP core
| Example Design Files | Description |
|---|---|
| <example_design_folder>/readme.txt | This file provide simple instructions to generate and use the example design. |
| <example_design_folder>/hello_world.c | This is the main test program. |
| <example_design_folder>/phylite_debug_kit.qsys | This is the system design file. |
| <example_design_folder>/phylite_dynamic_reconfigurations.c | This file contains the set of APIs use in the test program. |
| <example_design_folder>/phylite_dynamic_reconfiguration.h | This is the header file for the APIs. |
| <example_design_folder>/phylite_niosii_bridge.v <example_design_folder>/phylite_niosii_bridge_hw.tcl | This is an interconnect module between PHY Lite for Parallel Interfaces IP core and NIOS II processor. |
| <example_design_folder>/issp.tcl | This is the In-System Source and Probes module. Use this file to reset the system and to probe the status of the interface_locked signal and dynamic calibration done status from NIOS II processor. |
| API Function | Argument | Return Value | Description |
|---|---|---|---|
| hw_get_num_groups | ID | Integer | Read from AVL_CTRL_REG_NUM_GROUPS register for the specified ID. |
| hw_get_group_info | ID, GROUP_NUM | {16'h0000, num_lanes[7:0], num_pins[7:0]} | Read from AVL_CTRL_REG_GROUP_ INFO register for the specified ID
and group number. The return values are the number of lanes and number of pins available for the specified ID and group number. |
| hw_get_num_lanes | ID, GROUP_NUM | Integer | Read from the AVL_CTRL_REG_GROUP_ INFO register for the
specified ID and group number. The return values are the number of lanes available for the specified ID and group number. |
| hw_get_num_pins | ID, GROUP_NUM | Integer | Read from the AVL_CTRL_REG_GROUP_ INFO register for the
specified ID and group number. The return values are the number of pins available for the specified ID and group number. |
| hw_get_input_delay | ID, GROUP_NUM, PIN_NUM, CSR | Integer | Read from the AVL_CTRL_REG_IDELAY register for the specified ID,
group number, and pin ID. Specified CSR to:
|
| hw_get_output_delay | ID, GROUP_NUM, PIN_NUM, CSR | Integer | Read from the AVL_CTRL_REG_ODELAY register for the specified ID,
group number and pin number. Specified CSR to:
|
| hw_get_strobe_input_delay | ID, GROUP_NUM, PIN_NUM, CSR | Integer | Read from the AVL_CTRL_REG_DQS_DELAY delay register for the
specified ID, group number and pin number. Specified CSR to:
|
| hw_get_strobe_enable_delay | ID, GROUP_NUM, PIN_NUM, CSR | Integer | Read from the AVL_CTRL_REG_DQS_EN_DELAY register for the
specified ID, group number and pin number. Specified CSR to:
|
| hw_get_strobe_enable_phase | ID, GROUP_NUM, PIN_NUM, CSR | Integer | Read from the AVL_CTRL_REG_DQS_EN_PHASE_SHIFT register for the
specified ID, group number and pin number. Specified CSR to:
|
| hw_get_read_valid_enable_delay | ID, GROUP_NUM, PIN_NUM, CSR | Integer | Read from the AVL_CTRL_REG_RD_VALID_DELAY register for the
specified ID, group number and pin number. Specified CSR to:
|
| hw_set_input_delay | ID, GROUP_NUM, PIN_NUM, input delay value (integer) | — | Write to AVL_CTRL_REG_IDELAY register for the specified ID,
group number and pin number. Refer to Table 24 for valid value range. |
| hw_set_output_delay | ID, GROUP_NUM, PIN_NUM, output delay value (integer) | — | Write to AVL_CTRL_REG_ODELAY register for the specified ID,
group number and pin number. Refer to Table 24 for valid value range. |
| hw_set_strobe_input_delay | ID, GROUP_NUM, PIN_NUM, strobe input delay value (integer) | — | Write to AVL_CTRL_REG_DQS_DELAY register for the specified ID,
group number and pin number. Refer to Table 24 for valid value range. |
| hw_set_strobe_enable_delay | ID, GROUP_NUM, PIN_NUM, strobe enable delay value (integer) | — | Write to AVL_CTRL_REG_DQS_EN_DELAY register for the specified
ID, group number and pin number. Refer to Table 24 for valid value range. |
| hw_set_strobe_enable_phase | ID, GROUP_NUM, PIN_NUM, strobe enable phase value (integer) | — | Write to AVL_CTRL_REG_DQS_EN_PHASE_SHIFT register for the
specified ID, group number and pin number. Refer to Table 24 for valid value range. |
| hw_set_read_valid_enable_delay | ID, GROUP_NUM, PIN_NUM, read valid enable delay value (integer) | — | Write to AVL_CTRL_REG_RD_VALID_DELAY register for the specified
ID, group number and pin number. Refer to Table 24 for valid value range. |
Avalon Controller
The example design provides an Avalon controller to simplify the access to the dynamic reconfiguration registers of an interface. The Avalon controller is useful when there are multiple groups or instantiation of the PHY Lite for Parallel Interfaces IP core. A single controller can support multiple interfaces in an I/O column.
The input interface is as follows:
avl_in_address[31:0] = {8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0]}
| Register [7:0] | Register Name | Pin [5:0] | Csr[0] | Register Access Type | Data on avl_readdata / writedata | Description |
|---|---|---|---|---|---|---|
| 8'h00 | AVL_CTRL_REG_NUM_GROUPS | 0 | 0: Access to Avalon register. |
Avalon register: RO CSR register: N/A |
{24'h000000,num_grps[7:0]} | Number of groups within an interface. |
| 8'h01 | AVL_CTRL_REG_GROUP_INFO | 0 | 0: Access to Avalon register. |
Avalon register: RO CSR register: N/A |
{16'h0000,num_lanes[7:0],num_pins[7:0]} | Number of pins within a group. |
| 8'h02 | AVL_CTRL_REG_IDELAY | 0-47 | 0: Access to Avalon register. |
Avalon register: RW CSR register: N/A |
{23'h000000,dq_delay[8:0]} | Pin input delay. Use this register to set pin PVT compensated input delay. |
| 8'h03 | AVL_CTRL_REG_ODELAY | 0-47 |
0: Access to Avalon register. 1: Access to CSR register. Only read operation is allowed. |
Avalon register: RW CSR register: RO |
{19'h00000,output_delay[12:0]} | Pin output delay. Use this register to read and set the pin output delay. |
| 8'h04 | AVL_CTRL_REG_DQS_DELAY | 0: DQS A 1: DQS B 10 |
0: Access to Avalon register. |
Avalon register: RW CSR register: N/A |
{22'h000000,dqs_delay[9:0]} | Strobe input delay of a pin. Use this register to set the strobe PVT compensated input delay. |
| 8'h05 | AVL_CTRL_REG_DQS_EN_DELAY | 0 |
0: Access to Avalon register. 1: Access to CSR register. Only read operation is allowed. |
Avalon register: RW CSR register: RO |
{26'h0000000,dqs_en_delay[5:0]} | Strobe enable input delay of a pin. Use this register to set the strobe enable delay. |
| 8'h06 | AVL_CTRL_REG_DQS_EN_PHASE_SHIFT | 0: DQS A 1: DQS B 10 |
0: Access to Avalon register. 1: Access to CSR register. Only read operation is allowed. |
Avalon register: RW CSR register: RO |
{19'h00000,phase[12:0]} | Strobe enable input phase of a pin. Use this register to set the strobe enable phase. |
| 8'h07 | AVL_CTRL_REG_RD_VALID_DELAY | 0 |
0: Access to Avalon register. 1: Access to CSR register. Only read operation is allowed. |
Avalon register: RW CSR register: RO |
{25'h0000000,rd_vld_delay[6:0]} | Read val to set the read valid delay. |
Example of Accessing Dynamic Reconfiguration Control Registers using Avalon Controller
- Number of groups: 1. The group index is automatically set to 0x00.
- Interface ID: 0x04
- Pin width: 5
- Strobe configuration: Differential
avl_in_address[31:0] = {8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0]}
avl_in_address[31:0] = {8'h00,0x04,0x00,0x00,0x00,0x04}
avl_in_address[31:0] = {8'h00,interface_id[3:0],grp[4:0],pin[5:0],csr[0],register[7:0]}
avl_in_address[31:0] = {8'h00,0x04,0x00,0x06,0x00,0x02}
Generate the Dynamic Reconfiguration with Debug Kit Design Example
Run the Dynamic Reconfiguration with Debug Kit Design Example
Dynamic Reconfiguration Using Finite State Machine
This design example provides you a synthesizable system capable to perform dynamic calibration for PHY Lite for Parallel Interfaces IP core in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
Features
- Perform dynamic reconfiguration using Avalon controller
- Read and write transactions monitoring
- Delay values monitoring
Software Requirements
- Intel® Quartus® Prime software
- Active-HDL, ModelSim* - Intel® FPGA Edition, NCsim or VCS Simulator
Functional Description
This design example introduces the cfg_ctrl and avl_ctrl blocks, which work with the sim_ctrl module to demonstrate the basic functionality of the PHY Lite for Parallel Interfaces IPs Avalon-MM based reconfiguration. The agent is also modified to insert delays on the data and clocks, which the new modules will compensate for.
NOTE: The cfg_ctrl module performs a simplistic reconfiguration of the interface that stops at the first working delay values. The design example only support simulation. A robust calibration algorithm should sweep over the entire valid range of delays to choose the correct value for the application.
| Component | Description |
|---|---|
| ref_clk_gen | Generates clock to reset_gen, PHY Lite for Parallel Interfaces ADDR/CMD (ref_clk), and PHY Lite for Parallel Interfaces DUT (ref_clk) blocks. |
| reset_gen | Generates reset to PHY Lite for Parallel Interfaces ADDR/CMD and PHY Lite for Parallel Interfaces DUT blocks. |
| sim_ctrl |
|
| Driver | Generates strobe and data for each group and to PHY Lite for Parallel Interfaces_DUT block. |
| PHY Lite for Parallel Interfaces ADDR/CMD | Passing read/write commands and command clock from sim_ctrl to Agent. |
| Agent | FIFO to store data from PHY Lite for Parallel Interfaces DUT and side read/write data from sim_ctrl block. |
| cfg_ctrl |
This is configuration control block which performs read and write delay calibration before test begin. The calibration results is passed to the PHY Lite for Parallel Interfaces DUT through Avalon Controller. Contains 4 FSMs:
|
| avl_ctrl |
The Avalon controller is used to perform address translation to store delay settings from the calibration done by cfg_ctrl block. |
Generate the Dynamic Reconfiguration with Configuration Control Module Design Example
Run the Dynamic Reconfiguration with Configuration Control Design Example
Follow these steps to compile and simulate the design:
Application Specific Design Example
This design example demonstrates the PHY Lite for Parallel Interfaces IP core implementation for a NAND Flash design in Intel® Arria® 10 devices.
The following figure shows the RTL view of the design example.
Implementation using the PHY Lite for Parallel Interfaces IP Core
You can configure the PHY Lite for Parallel Interfaces IP core to support multiple groups (maximum 48 I/O pins each).
The following lists the possible implementations:
- Instantiates one PHY Lite for Parallel Interfaces IP core with two
groups
- Bidirectional type for DQ and DQS signals
- Output type for Addr/Cmd signals
PHY Lite for Parallel Interfaces IP Core User Guide Document Archives
| IP Core Version | User Guide |
|---|---|
| 19.1 | Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide |
| 18.1 | Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide |
| 18.0 | Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide |
| 17.1 | Intel FPGA PHYLite for Parallel Interfaces IP Core User Guide |
| 17.0 | Altera PHYLite for Parallel Interfaces IP Core User Guide |
| 16.0 | Altera PHYLite for Parallel Interfaces IP Core User Guide |
| 15.1 | Altera PHYLite for Parallel Interfaces IP Core User Guide |
| 14.1 | Altera PHYLite for Parallel Interfaces IP Core User Guide |
Document Revision History for the PHY Lite for Parallel Interfaces IP Core User Guide
| Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
|---|---|---|---|
| 2019.11.07 | 19.3 | 19.1 |
|
| 2019.04.04 | 19.1 | 19.1 |
|
| 2019.04.01 | 19.1 | 19.1 |
|
| 2019.01.09 | 18.1 | 18.1 | Added estimation time for a delay register value to change in Reconfiguration Features and Register Addressing. |
| 2018.09.21 | 18.1 | 18.1 |
|
| 2018.06.06 | 18.0 | 18.0 |
|
| 2018.05.07 | 18.0 | 18.0 |
|
| Date | Version | Changes |
|---|---|---|
| November 2017 | 2017.11.30 |
|
| June 2017 | 2017.06.16 |
|
| February 2017 | 2017.02.24 |
|
| October 2016 | 2016.10.28 |
|
| May 2016 | 2016.05.02 |
|
| December 2015 | 2015.12.11 |
|
| November 2015 | 2015.11.02 |
|
| June 2015 | 2015.06.12 |
|
| January 2015 | 2015.01.28 | Updated related information link to Functional Description for External Memory Interfaces in Arria 10 Devices. |
| December, 2014 | 2014.12.30 |
|
|
August, 2014 |
2014.08.18 |
|
|
November, 2013 |
2013.11.29 |
Initial release. |