PHY Lite for Parallel Interfaces Intel FPGA IP User Guide

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ug_altera_phylite | 2020.11.13

Version Information

Updated for:
Intel® Quartus® Prime Design Suite 20.3

1. About the PHY Lite for Parallel Interfaces IP

This user guide describes the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP, PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP, PHY Lite for Parallel Interfaces Intel^® Arria^® 10 FPGA IP, and PHY Lite for Parallel Interfaces Intel^® Cyclone^® 10 GX FPGA IP cores. The PHY Lite for Parallel Interfaces IP core is primarily used for building custom memory interface PHY blocks. You can use this solution to interface with protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (Synchronous Mode), and Mobile DDR.

The IP has a dedicated PHY clock tree in each I/O bank. The PHY clock tree is shorter which yields lower jitter and duty cycle distortion (DCD), enabling designs to achieve higher performance.

In addition, this IP supports Dynamic Reconfiguration feature which enables reconfiguration of the data and strobe delays. You can align the data and strobe via calibration to achieve timing closure at high frequencies.

This IP controls the strobe-based capture I/O elements. Each instance of the IP can support an interface up to 18 individual data/strobe capture groups. Each group can contain up to 48 data I/Os as well as the strobe capture logic.

1.1. Device Family Support

The PHY Lite for Parallel Interfaces IP supports the following devices:

Intel^® Agilex™
Intel^® Stratix^® 10
Intel^® Arria^® 10
Intel^® Cyclone^® 10 GX

For Arria^® V, Cyclone^® V, and Stratix^® V devices, use the ALTDQ_DQS2 Intel FPGA IP instead.

1.2. Features

The PHY Lite for Parallel Interfaces IP:

Supports input, output, and bidirectional data channels.
Supports DQS-group based data capture, with up to 36 I/Os (including strobes) per group for Intel^® Agilex™ devices and 48 I/Os (including strobes) per group for Intel^® Stratix^® 10, Intel^® Arria^® 10, and Intel^® Cyclone^® 10 GX devices.
Supports DQS gating/ungating circuitry for strobe-based interfaces.
Supports output delays via interpolator.
Supports dynamic on-chip termination (OCT) control.
Supports quarter-rate for Intel^® Agilex™ devices and quarter-rate to half-rate and half-rate to full-rate of the interface clock conversions for Intel^® Stratix^® 10, Intel^® Arria^® 10, and Intel^® Cyclone^® 10 GX devices.
Supports input, output, and read/DQS/OCT enable paths.
Supports single data rate (SDR) and double data rate (DDR) at the I/Os.
Supports PHY clock tree.
Supports dynamically reconfigurable delay chains using Avalon memory-mapped interface for Intel^® Stratix^® 10, Intel^® Arria^® 10, and Intel^® Cyclone^® 10 GX devices.
Supports process, voltage, and temperature (PVT) or non-PVT compensated input and DQS delay chains
Note: The non-PVT compensated component of the input delay is set through the .qsf assignment in the Intel^® Quartus^® Prime software.

2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP

2.1. Release Information

Intel^® FPGA IP versions match the Intel^® Quartus^® Prime Design Suite software versions until v19.1. Starting in Intel^® Quartus^® Prime Design Suite software version 19.2, Intel^® FPGA IP has a new versioning scheme.

The Intel^® FPGA IP version (X.Y.Z) number can change with each Intel^® Quartus^® Prime software version. A change in:

X indicates a major revision of the IP. If you update the Intel^® Quartus^® Prime software, you must regenerate the IP.
Y indicates the IP includes new features. Regenerate your IP to include these new features.
Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Table 1. PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP Release Information
Item	Description
IP Version	20.3.0
Intel^® Quartus^® Prime Version	20.3
Release Date	2020.09.28

2.2. Functional Description

The PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP utilizes the I/O banks in Intel^® Agilex™ devices. Each I/O bank has two I/O sub-banks in each device. The top sub-bank is placed near the edge of the die, and the bottom sub-bank is placed near the FPGA core.

Each each sub-bank contains the following components:

Hard memory controller
I/O PLL and PHY clock trees
DLL
Input DQS/strobe trees
48 pins, organized into four I/O lanes of 12 pins each

Figure 1. Intel^® Agilex™ I/O Bank Structure

2.2.1. Intel Agilex I/O Sub-bank Interconnects

There are interconnects between the sub-banks which chain the sub-banks into a row. The following figures show how I/O lanes in various sub-banks are chained together to form the top and bottom I/O rows in various Intel^® Agilex™ device variants. These figures represent the top view of the silicon die that corresponds to a reverse view of the device package.

Figure 2. Sub-Bank Ordering in Top I/O Row in Intel^® Agilex™ AGF012 and AGF014, package R24A

Figure 3. Sub-Bank Ordering in Bottom I/O Row in Intel^® Agilex™ AGF012 and AGF014, package R24A

Figure 4. Sub-Bank Ordering in Top I/O Row in Intel^® Agilex™ AGF014, package R17A

Figure 5. Sub-Bank Ordering in Bottom I/O Row in Intel^® Agilex™ AGF014, package R17A

Figure 6. Sub-Bank Ordering in Top I/O Row in Intel^® Agilex™ AGF022 and AGF027 devices, package R25A

Figure 7. Sub-Bank Ordering in Bottom I/O Row in Intel^® Agilex™ AGF022 and AGF027 devices, package R25A

2.2.2. Intel Agilex Input DQS/Strobe Tree

The input DQS/strobe tree is a balanced clock network that distributes the read capture strobe (such as DQS/DQS#) from the external device to the read capture registers inside the I/Os.

The DQS/strobe tree is used for input and bidirectional pin types.

Within every bank, only certain physical pins at specific locations can drive the input DQS/strobe trees. The pin locations that can drive the input DQS/strobe trees vary, depending on the size of the group.

Table 2. Pins Usable as Read Capture Clock / Strobe Pair
Lane Index Options	Pin Width	Group Size	Sub-Bank	Index of Pins Usable as Read Capture Clock / Strobe Pair
Lane Index Options	Pin Width	Group Size	Sub-Bank	DQS p	DQS n
0	1 to 9	x8 / x9	Top and bottom	4	5
1	1 to 9	x8 / x9		16	17
2	1 to 9	x8 / x9		28	29
3	1 to 9	x8 / x9		40	41
0, 1	1 to 9 ¹	x18		4	5
0, 1	10 to 18	x18		4	5
2, 3	1 to 9 ²	x18		28	29
2, 3	10 to 18	x18		28	29
1,2	1 to 9 ³	x36		16	17
1,2	10 to 18	x36		16	17
0,1,2	1 to 9 ⁴	x36		16	17
	10 to 18⁴	x36		16	17
	19 to 34	x36		16	17
1,2,3	1 to 9 ⁵	x36		16	17
	10 to 18⁵	x36		16	17
	19 to 34	x36		16	17
0,1,2,3	1 to 9 ⁶	x36		16	17
	10 to 18⁶	x36		16	17
	19 to 34	x36		16	17

¹ When the pins in lanes 0 and 1 are used.

² When the pins in lanes 2 and 3 are used.

³ When the pins in lanes 1 and 2 are used.

⁴ When the pins in lanes 0, 1, and 2 are used.

⁵ When the pins in lanes 1,2, and 3 are used.

⁶ When the pins in lanes 0,1,2, and 3 are used.

2.2.3. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP Top Level Interfaces

The PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP consists of the following ports:

Clocks and reset
Core data and control (broken down into input and output paths)
I/O (broken down into input and output paths)

Figure 8. Top-Level Interface This figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP interface.

2.2.3.1. Clocks

The PHY Lite for Parallel Interfaces IP uses a reference clock that is sourced from a dedicated clock pin to the PLL inside the IP. This PLL provides four clock domains for the output and input paths.

Table 3. PHY Lite for Parallel Interfaces IP Clock Domains
Clock Domain	Description
Core clock	This clock is generated internally by the IP and it is used for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phase with the PHY clock for core-to-periphery and periphery-to-core transfers.
PHY clock	This clock is used internally by the IP for PHY circuitry running at the same frequency as the core clock.
VCO clock	This clock is generated internally by the PLL. It is used by both the input and output paths to generate PVT compensated delays in the interpolator.
Interface clock	This is the clock frequency of the external device connected to the FPGA I/Os.

Table 4. PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP Supported Interface Frequency
Core Clock Rate	Speed Grade –1 (MHz)		Speed Grade –2 (MHz)		Speed Grade –3 (MHz)
Core Clock Rate	Min	Max	Min	Max	Min	Max
Quarter	100	1200	100	1200	100	1200

Note: The PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP supports only quarter core clock rate.

2.2.3.1.1. Clock Frequency Relationships

The following equations describe the relationships between the clock domains available in the PHY Lite for Parallel Interfaces IP.

Core Clock Rate = Interface clock frequency / Core clock frequency

VCO frequency Multiplier Factor = VCO clock frequency ⁷ / Interface clock frequency

⁷ You can obtain this value from the VCO clock frequency parameter under General Tab in the IP parameter editor.

2.2.3.2. Output Path

The output path consists of a FIFO and an interpolator.

Table 5. Blocks in Output PathThis table lists the blocks in the output path.
Block	Description
Write FIFO	Serializes the output data from the core with a serialization factor of up to 8 (in DDR quarter-rate).
Interpolator	Works with the FIFO block to generate the desired output delay.

Figure 9. Output PathThis figure shows the output path for the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP.

2.2.3.2.1. Output Path Data Alignment

The group_data_from_core and group_oe_from_core signals are arranged in time slices, which are separated into the individual pins in the group. The first time slice is on the LSBs of the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering of the External Memory Interfaces IP.

Example of time slices with individual pins correlation:

{time(n),time(n-1),time(n-2),... time(0)}

Where time0 = {pin(n),pin(n-1),pin(n-2),...pin0}

Figure 10. Example Output for Quarter Rate DDR

2.2.3.3. Input Path

The input path of the IP consists of a data path, a strobe path, and a read enable path.

Table 6. Blocks in Data, Strobe, and Read Enable PathsThis table lists the information about these paths.
Path	Description
Data Path	Receives data from external device to the FPGA core logic. The data path consists of a PVT compensated delay chain, a DDIO and a read FIFO. DDIO and read FIFO—Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate). The transfer between the DDIO and the read FIFO is a zero-cycle transfer. Signals used in this path are: `group_data_in`—Input data from external device. `group_data_io`—Input and output data from/to external device. `group_data_to_core` (output)—Output data to the Intel FPGA core. `phy_clk`—This is an internal clock signal that provides clock to the blocks used in this path. The IP supports SDR input by sending data on single clock cycle from the external device.
Strobe Path	Input strobe (`dqs`) to capture input data from external device. The strobe path consists of pstamble_reg (a gating component) and a PVT compensated delay chain. pstamble_reg—This gating circuitry ensures that only clock edges associated with valid input data are used. PVT compensated delay chain—Provides a phase offset between the strobe and the data (for example, center aligning edge-aligned inputs). Signals used in this path are: `group_strobe_in`, `group_strobe_in_n` (input)—Input strobe from external device. . `group_strobe_io`, `group_strobe_io_n`(bidirectional)—Input and output strobe from/to external device. `group_strobe_io_n` is used when strobe configuration is set to Differential. `dqs_clean`(output)—This internal signal is the refined version of `strobe_in` signal. `dqs`(input)—This internal signal is an input strobe to DDIO and Read FIFO in the data path, after phase shift adjustment.
Read and Strobe Enable Path	Generates control signals for strobe calibration and reading data from Read FIFO. The read and strobe enable path consists of VFIFO, DQS_EN FIFO, and an interpolator. VFIFO—Takes the `rdata_en` signal from the core and delays it separately for two outputs, one for the read enable on the Read FIFO, and one for the strobe enable. These delays are calculated at generation time based on the read latency that you provide. DQS_EN FIFO and interpolator—Used for the strobe enable delay, the DQS_EN FIFO and interpolator are identical to the Write FIFO and interpolator circuitry in the output path. The DQS_EN FIFO and interpolator are configured to match the output delay for a group with no additional output delay (Write latency = `0`). Signals used in this path are: `group_rdata_valid` (output)—This signal determines which data are valid when reading from Read FIFO. This signal is delayed by the Read latency value set in the parameter editor. `group_rdata_en` (input)—This signal represents the number of expected words to read from the external device. `dqs_enable_in` (input)—This is an internal signal that provides dqs delay value to the pstamble_reg module to process a refined dqs signal. `dqs_enable_out` (output)— This is an internal strobe with the delayed value specified by the dqs_enable_in signal. `phy_clk`—This is an internal clock for VFIFO and Read FIFO modules. `phy_clk_phs`—This is an internal clock for the interpolator. `interpolator_clk`—This is an internal clock for DQS_EN FIFO module.

Figure 11. Input PathThis figure shows the input path of the IP.

Table 7. Read Operation SequenceA read operation is performed as listed in this table.
Read Operation Sequence Number	Operation
1	The core asserts the `rdata_en` signal to the PHY Lite for Parallel Interfaces IP and issues a read command to the external device.
2	VFIFO and DQS_EN FIFO generate the `dqs_enable` signal to pstamble_reg. This signal is delayed by the programmed read latency (which should match the latency of the external device).
3	The pstamble_reg generates `dqs_clean` signal as valid data enters the read path.
4	The Delay Chain (PVT) adjusts the strobe with phase offset between the strobe and the input data (for example, 90° phase shift for DDR center-alignment).
5	The `dqs` signal is then used as strobe to read data from external device into the DDIO and Read FIFO modules.
6	The VFIFO asserts the `read_enable` signal to Read FIFO and the `rdata_valid` signal to the core simultaneously. The PHY Lite for Parallel Interfaces IP sends the captured data to the core with the associated valid signal.

2.2.3.3.1. Input Path Data Alignment

The bus ordering of group_data_to_core, group_rdata_en, and group_rdata_valid is identical to the ordering of the output path. The LSBs of the bus hold the first time slice of data received.

The group_rdata_valid delay is always set by the IP to match the group_rdata_en alignment. For example, quarter-rate delays are multiples of four external memory clock cycles (one quarter rate clock cycle).

Reading from an unaligned memory address is called unaligned reads. Unaligned reads will result in unaligned group_rdata_valid and group_data_to_core with data and valid signals packed to the LSBs. This request causes the IP to do two or more read operations.

The following waveform shows an example of aligned reads on the input path of the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf, which represents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, which represents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core bus matches the data seen on the group_0_data_io bus.

Figure 12. Example Input (Quarter Rate DDR) - Aligned

The following waveform shows an example of unaligned reads on the input path of the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP.

The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data from group_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1, which shows there are 2 bytes of incoming data from group_0_data_io bus.

The valid data are transfer to the IP through the group_0_data_to_core bus. At first rising edge of the core_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytes of the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On the subsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes of the data from the group_0_data_to_core bus are valid.

Figure 13. Example Input (Quarter Rate DDR) - Unaligned

2.3. Getting Started

You can instantiate the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP from IP Catalog in Intel^® Quartus^® Prime software. Intel provides an integrated parameter editor that allows you to customize this IP to support a wide variety of applications.

This IP is located in Libraries > Basic Functions > I/O of the IP catalog.

2.3.1. Parameter Settings

Table 8. PHY Lite for Parallel Interfaces IP Parameter Settings
GUI Name	Values	Default Values	Description
Parameter
Number of groups	1 to 4	1	Number of data and strobe groups in the interface. The value is set to 1 by default.
General Tab- these parameters are set on a per interface basis
Clocks
Interface clock frequency	100 MHz - 1200 MHz	533.0 MHz	External interface clock frequency.
Use recommended PLL reference clock frequency	On, Off	On	If you want to calculate the PLL reference clock frequency automatically for best performance, turn on this option. If you want to specify your own PLL reference clock frequency, turn off this option.
PLL reference clock frequency	Dependent on interface clock frequency	133.25 MHz	PLL reference clock frequency. You must feed a clock of this frequency to the PLL reference clock input of the memory interface. Select the desired PLL reference clock frequency from the drop-down list. The values in the list changes when you change the interface clock frequency or the user clock rate logic.
VCO clock frequency	Calculated internally by PLL	1066.0 MHz	The frequency of this clock is calculated internally by the PLL based on the interface clock and the core clock rate.
Clock rate of user logic	Quarter	Quarter	Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800 MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200 MHz.
Dynamic Reconfiguration
Use dynamic reconfiguration	—	—	Exposes an Avalon memory-mapped interface, allowing you to control the configuration of the PHY Lite for Parallel Interfaces IP settings. Note: The PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP does not support dynamic reconfiguration feature in the Intel^® Quartus^® Prime v20.3.
I/O Settings
I/O standard	SSTL-12 1.2-V POD	SSTL-12	Specifies the I/O standard of the interface's strobe and data pins written to the .qip file of the IP instance.
Reference clock I/O configuration	Single-ended, True Differential with on-chip termination, True Differential without on-chip termination	Single-ended	Specify the reference clock I/O configuration.
Group <x> - these parameters are set on a per group basis
Group <x> Pin Settings
Pin type	Input, Output, Bidirectional	Bidirectional	Direction of data pins. This value is set to Bidirectional by default.
Pin width	1 to 36	9	Number of pins in this data/strobe group. The pin width includes the number of strobe pins.
DDR/SDR	DDR, SDR	DDR	Double/single data rate.
Group <x> Input Path Settings
Read latency	7 to 63 external interface clock cycles	7	Expected read latency of the external device in memory clock cycles. Refer to the Read Latency table for minimum read latency settings based on FPGA core clock rate.
Capture strobe phase shift	0, 45, 90, 135, 180	90	Internally phase shift the input strobe relative to input data.
Group <x> Output Path Settings
Write latency	0 to 3	0	Additional delay added to the output data in memory clock cycles. Refer to the Write Latency table for write latency settings based on FPGA core clock rate.
Output strobe phase	0, 45, 90, 135, 180	90	Phase shift of the output strobe relative to the output data.
Group <x> General Strobe Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Strobe configuration	Differential	Differential	Select the type of strobe. Note: The differential strobe configuration uses a differential input buffer, which produces a single clock for the capture DDIO and read FIFO. The output path functionality is the same. Refer to the I/O Standards table for a list of supported I/O standards.
Group <x> OCT Settings
OCT enable size	0 - 15	1	Specifies the delay between the OCT enable signal assertion and the dqs_enable signal assertion. You must set a value that is large enough to ensure that the OCT is turn on before sampling input data.
Use Default OCT Values	On, Off	On	Use default OCT values based on the I/O standard parameter setting.
Expose termination ports	On, Off	Off	Enable this parameter to expose the series and parallel termination ports to connect to separate OCT blocks.
Input OCT Value	60 ohm with calibration, 50 ohm with calibration	60 ohm with calibration	Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to theI/O Standards table . Disable the Use Default OCT Values parameter to select the desired input OCT value.
Output OCT Value	34 ohm with calibration, 40 ohm with calibration	40 ohm with calibration	Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to the I/O Standards table supported termination values. Disable the Use Default OCT Values parameter to select the desired output OCT value.
Group <x> Placement Settings
Enable manual location of data pins	On, Off	Off	By default, all the data pins are placed adjacent to each other with no gap between the pins. Enable this option if require a gap between the data pins. Refer to the Guidelines: Group Pin Placement topic for pin placement guidelines for PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP.
Manual location list of data pins	Comma-separated values	—	Enter the location list of the data pins. Provide the data pins location list in values. For example, enter value of 0, 1, 8, 9 to place data [0] on pin 0, data[1 on pin 1], data[2] on pin 8, and data[3] on pin 9 of the I/O bank. In this case, pin 2 to pin 7 are not used. Refer to the Guidelines: Group Pin Placement topic for pin placement guidelines for PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP.

2.3.1.1. Read Latency

Table 9. Minimum Read Latency This table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate	VCO Multiplier Factor	Read Latency (External Memory Clock Cycle)
Quarter rate	1	7
	2	7
	4	7
	8	7

2.3.1.2. Write Latency

Table 10. Maximum Write LatencyThis shows the maximum write latency value supported by PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate	VCO Multiplier Factor	Write Latency (External Memory Clock Cycle)
Quarter rate	1	3
	2	3
	4	3
	8	2

2.3.2. Signals

2.3.2.1. Clock and Reset Interface Signals

Table 11. Clock and Reset Interface Signals
Signal Name	Direction	Width	Description
`ref_clk`	Input	1	Reference clock for the PLL. The reference clock must be synchronous with `group_strobe_in` to ensure the `dqs_enable` signal is in-sync with `group_strobe_in`.
`reset_n`	Input	1	Resets the interface. Deassertion of this signal should be synchronous to the `ref_clk`.
`interface_locked`	Output	1	Interface `locked` signal from PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP to the core logic. This signal indicates that the PLL and PHY circuitry are locked. Data transfer should starts after the assertion of this signal.
`core_clk_out`	Output	1	Use this core clock in the core-to-periphery transfer of soft logic data and control signals. The `core_clk_out` frequency depends on the interface frequency and clock rate of user logic parameter.

2.3.2.2. Output Path Signals

Table 12. Output Path SignalsOutput path signals are signals that are available when you set the **Pin Type** parameter to either **Output** or **Bidirectional**. The <n> in the signal names below represents the group number in the IP.
Signal Name	Direction	Width	Description
`group_oe_from_core`	Input	Quarter-rate: 4	Output enable signal from FPGA core. Synchronous to the `core_clk_out` output from the IP. This signal is shared across all groups.
`group_<n>_data_from_core`	Input	Quarter rate-DDR: 8 x `PIN_WIDTH` Quarter-rate SDR: 4 x `PIN_WIDTH`	Data signal from Intel FPGA core. Synchronous to the `core_clk_out` output from the IP.
`group_strobe_out_en`	Input	Quarter-rate: 4	Strobe output enable from FPGA core. Synchronous to the `core_clk_out` output from the IP. This signal is shared across all groups.
`group_<n>_data_out` /`group_<n>_data_io`	Output/Bidirectional	1 to 34	Data output from the IP. Synchronous to the `group_<n>_strobe_out` or `group_<n>_strobe_io` output from the IP. If the Pin Type parameter is set to Output, the `group_<n>_data_out` signals are used. If the Pin Type parameter is set to Bidirectional, the `group_<n>_data_io` signals are used.
`group_<n>_strobe_out/group_strobe_io`/`group_<n>_strobe_io`	Output/Bidirectional	1	Positive output strobe from the IP. If the Pin Type is set to Output, the `group_<n>_strobe_out` signal is used. If the Pin Type is set to Bidirectional the `group_<n>_strobe_io` signal is used.
`group_<n>_strobe_out_n`/`group_<n>_strobe_io_n`	Output/Bidirectional	1	Negative output strobe fro the IP. This is used if the Strobe Configuration is set to Differential. If the Pin Type is set to Output, the `group_<n>_strobe_out_n` signal is used. If the Pin Type is set to Bidirectional, the `group_<n>_strobe_io_n` signal is used.

2.3.2.3. Input Path Signals

Table 13. Input Path SignalsInput path signals are signals that are available when you set the **Pin Type** parameter to **Input** or Bidirectional. The <n> in the signal names below represents the group number in the IP.
Signal Name	Direction	Width	Description
`group_<n>_data_to_core`	Output	Quarter-rate DDR: 8 x `PIN_WIDTH` Quarter-rate SDR: 4 x `PIN_WIDTH`	Output data to the core logic. Valid on `group_<n>_rdata_valid`. Synchronous to the `core_clk_out` output from the IP.
`group_rdata_en`	Input	Quarter-rate: 4	This signal represents the number of expected words to read from the external device. This signal is set to high after a read command is issued. Synchronous to the `core_clk_out` output from the IP. When using the IP as a receiver, assert this signal after `interface_locked` signal is asserted and `group_strobe_in` is stable. This signal is shared across all groups.
`group_<n>_rdata_valid`	Output	Quarter-rate: 4	This signal determines which data are valid when reading from Read FIFO. Delayed by `READ_LATENCY` with margin and aligned to the core clock rate. For example, in quarter-rate, the delay is a multiple of 4 external clock cycles. Synchronous to the `core_clk_out` output from the IP.
`group_<n>_data_in/` `group_<n>_data_io`	Input/Bidirectional	1 to 34	Input and output data from/to external device. Synchronous to the `group_<n>_strobe_in` or `group_<n>_strobe_io` input. The first data_in must be associated with positive edge of `group_<n>_strobe_in`/`group_<n>_strobe_io`. If the pin type is set to Input, the `group_<n>_data_in` ports are used. If the pin type is set to bidirectional, the `group_<n>_data_io` ports are used.
`group_<n>_strobe_in/` `group_<n>_strobe_io`	Input/Bidirectional	1	Input and output strobe from/to external device. If the pin type is set to Input, the `group_<n>_strobe_in` signal is used. If the pin type is set to Bidirectional, the `group_<n>_strobe_io` signal is used.
`group_<n>_strobe_in_n`/`group_<n>_strobe_io_n`	Input/Bidirectional	1	Negative strobe from/to external device. This is used if the Strobe Configuration parameter is set to Differential. If the pin type is set to Input, the `group_<n>_strobe_in_n` signal is used. If the pin type is set to Bidirectional, the `group_<n>_strobe_io_n` signal is used.

2.3.2.4. Termination Signals

Table 14. Termination SignalsThe termination signals are signals that are available when you enable the **Expose termination ports** parameter. The <n> in the signal names below represents the group number in the IP.
Signal Name	Direction	Width	Description
`group_<n>_seriesterminationcontrol`	Input	16	Connect this signal to the series termination control signal of the OCT Intel^® FPGA IP to receive series termination code to calibrate R_s.
`group_<n>_parallelterminationcontrol`	Input	16	Connect this signal to the parallel termination control signal of the OCT Intel^® FPGA IP to receive parallel termination code to calibrate R_t.

2.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.

Table 15. I/O Standards and Termination Values for Intel^® Agilex™ Devices
I/O Standard	Valid Input Terminations (Ω)	Valid Output Terminations (Ω)	RZQ (Ω)
SSTL-12	50, 60	34, 40	240
1.2-V POD	50, 60	34, 40	240

2.4.1. Input Buffer Reference Voltage (VREF)

The POD I/O standard allows configurable VREF. By default, the externally provided VREF is used and using an internal VREF requires the following .qsf assignments:

set_instance_assignment -name VREF_MODE <mode> -to <pin_name>

The VREF settings are at the lane level, so all pins using a lane must have the same VREF settings including general-purpose I/Os (GPIO).

Note: Calibrated VREF mode is not supported in Intel^® Quartus^® Prime v20.3.

Table 16. VREF_MODE Description
VREF Mode	Description
EXTERNAL	Use the external VREF. This is the default.
VCCIO_45	Use internal VREF generated using static VREF code. VREF is 45% of VCCIO
VCCIO_50	Use internal VREF generated using static VREF code. VREF is 50% of VCCIO
VCCIO_55	Use internal VREF generated using static VREF code. VREF is 55% of VCCIO
VCCIO_65	Use internal VREF generated using static VREF code. VREF is 65% of VCCIO
VCCIO_70	Use internal VREF generated using static VREF code. VREF is 70% of VCCIO
VCCIO_75	Use internal VREF generated using static VREF code. VREF is 75% of VCCIO

Figure 14. VREF

2.4.2. On-Chip Termination (OCT)

PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP provides valid OCT settings for each group (refer to I/O Standards). These settings are written to the .qip of the instance during generation. If you select an I/O standard that supports OCT in the General tab, you can use the OCT blocks provided in the Intel^® Agilex™ devices.

You can instantiate the OCT block in one of two ways:

Using RZQ_GROUP assignment in the assignment editor, or
Manual insertion of OCT block

2.4.2.1. RZQ_GROUP Assignment

The RZQ_GROUP assignment creates the OCT Intel FPGA IP without modifying the RTL. The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the Fitter creates the pin name along with the OCT Intel FPGA IP and its corresponding connections. This allows you to create a group of pins to be calibrated by an existing or non-existing OCT and the Fitter ensures the legality of the design. You must associate the terminated pins of the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP instance with an RZQ pin at the system level manually.

Use the following steps to set RZQ pin locations for the IP:

In the Group <x> OCT Settings tab, disable Use Default OCT Values and Expose termination ports.

Figure 15. Group <x> OCT Settings Parameter Settings
Generate the IP or instantiate the IP into your project.
You can view the available RZQ pins location in the Pin Planner. Go to Pin Planner > Tasks > OCT Pins and double click the RZQ. The available RZQ pins are display in the pin grid diagram.
You can modify the qsf in your project to change the default RZQ location using the following command:
```
set_location_assignment <rzq_capable_pin_location> –to <user_defined_rzq_pin_name>
```

Use the following command to associate the terminated pins of the IP with the RZQ pin:

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <phylite_strobe_pin>

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <phylite_data_pin[*]>

where * represents all the data pins within the same group.

This is an example of a qsf file with modified RZQ pin location assignments:

set_location_assignment PIN_AH3 -to octrzq
set_instance_assignment -name IO_STANDARD "1.5 V" -to octrzq
set_instance_assignment -name RZQ_GROUP OCTRZQ -to group_0_io_interface_conduit_end_io_strobe_io
set_instance_assignment -name RZQ_GROUP OCTRZQ -to group_0_io_interface_conduit_end_io_data_io[*]

Compile the project.
To verify that the Intel^® Quartus^® Prime has successfully created and assigned the RZQ pin to the correct location, go to Pin Planner > Node Name and look for <user_defined_rzq_pin_name> with the assigned pin location in the list.

2.4.2.2. Manual Insertion of OCT Block

You may also instantiate the OCT Intel FPGA IP separately in your project and connect the termination ports to the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP.

Expose the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP termination ports by disable Use Default OCT Values.
Select the available OCT values in the Input OCT Value or Output OCT Value parameter depending on Pin Type selection. This displays the Expose termination ports parameter.
Note: For supported input and output OCT values, refer to the I/O Standards topic.
Select Expose termination ports to expose the termination ports in the IP.
Connect the termination ports to a OCT Intel FPGA IP either in power-up or user mode.

Figure 16. RTL View of PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP Interfacing with OCT Intel FPGA IP in User Mode

2.5. Design Guidelines

2.5.1. Guidelines: Group Pin Placement

Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP group pins.

All groups in a PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP must be placed across a contiguous set of lanes. The number of lanes depends on the number of pins used by the group. Refer to the Intel^® Agilex™ Input DQS Clock Tree for more information about the number lanes used per pin width.
Two groups within a PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP cannot share an I/O lane.
Pins that are not used in an I/O sub-bank cannot be used as GPIO pins.
A PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP must fit within one I/O sub-bank and must not span across multiple I/O sub-banks. One I/O sub-bank can support only one IP instance.
When there are multiple groups within an IP instance, the pins must be set to either bidirectional pin or unidirectional (can be a mix of input and output groups). Do not mix bidirectional and unidirectional pin types in the same IP instance.
If an input group uses x36 DQS/strobe tree another group must be set as an output group to utilize the remainder I/O lane in the same I/O sub-bank.
If a group is set to bidirectional pin type and uses the x36 DQS/strobe tree, no other groups are allowed to be in the same IP.
Control signals are shared across all groups within an IP instance.
You must calibrate the I/Os within the same I/O lane using the same OCT calibration block. You can associate the terminated pins of the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP instance with an RZQ pin through the RZQ_GROUP assignment.
You can place the data pin locations manually by enabling the Enable manual location of data pins and provide a list of comma-separated values in the Manual location list of data pins parameter. Manual pin placement lets you set the pin locations when generating the IP. It also eliminates the effort to decode pin addresses in the parameter tables.
The PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP does not support manual pins assignment using .qsf file. All the pin locations within an I/O sub-bank is fixed during IP instantiation.

Table 17. Pin Index Mapping
I/O Bank Pin Index	I/O Sub-bank Pin Index	Lane	Sub-bank Location
0-11	0-11 (pins 4 and 5 are reserved for strobes while pin 7 is not available for the PHY Lite for Parallel Interfaces IP)	0	Bottom
12-23	12-23 (pins 16 and 17 are reserved for strobes while pin 19 is not available for the PHY Lite for Parallel Interfaces IP)	1
24-35	24-35 (pins 28 and 29 are reserved for strobes while pin 31 is not available for the PHY Lite for Parallel Interfaces IP)	2
36-47	36-47 (pins 40 and 41 are reserved for strobes while pin 43 is not available for the PHY Lite for Parallel Interfaces IP)	3
48-59	0-11 (pins 4 and 5 are reserved for strobes while pin 7 is not available for the PHY Lite for Parallel Interfaces IP)	0	Top
60-71	12-23 (pins 16 and 17 are reserved for strobes while pin 19 is not available for the PHY Lite for Parallel Interfaces IP)	1
72-83	24-35 (pins 28 and 29 are reserved for strobes while pin 31 is not available for the PHY Lite for Parallel Interfaces IP)	2
84-95	36-47 (pins 40 and 41 are reserved for strobes while pin 43 is not available for the PHY Lite for Parallel Interfaces IP)	3

Figure 17. Example of Occupied Data Pins for a Single Group Using Automatic Pin Placement In this example, the pin placement are set by the Intel^® Quartus^® Prime software automatically. The corresponding data pins to data signals are:

data pins 0-3 = data signal 0-3
data pin 6 = data signal 4
data pins 8-11 = data signal 5-8
data pins 12-15 = data signal 9-12
data pin 18 = data signal 13
data pins 20-23 = data signals 14-17
data pins 25-26 = data signals 18-19

Figure 18. Example of Occupied Data Pins for a Single Group Using Manual Pin Placement In this example, the manual pin placement list is 0,1,2,3,8,9,10,11,44,45,46,47,36,37,38,39,12,13,14,15. The corresponding data pins to data signals are:

pins 0-3 = data signals 0-3
pins 8-11 = data signals 4-7
pins 12-15 = data signals 16-19
pins 36-39 = data signals 12-15
pins 44-47 = data signals 8-11

For more information about strobe and clock pin indexes, refer to the device pin-out files.

2.5.2. Reference Clock

You are recommended to source the reference clock to the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP from a dedicated clock pin. Use the clock pin in the I/O sub-bank.

2.5.3. Reset

You can source the reset to the PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP from an external pin or from the core. If you source the reset from an external pin, you must configure the I/O standard of the reset signal in the .qsf file with the following command:

set_location_asignment <PIN_NUMBER> -to <signal_name>

2.6. Design Example

The PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP is able to generate a design example that matches the same configuration chosen for the IP. The design example is a simple design that does not target any specific application; however you can use the design example as a reference on how to instantiate the IP and what behavior to expect in a simulation.

You can generate a design example by clicking Generating Example Design in the IP Parameter Editor.

Note: The PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP supports only simulation design example for variant without dynamic reconfiguration.

Note: The .qsys files are for internal use during design example generation only. You should not edit the files.

2.6.1. Generate the Simulation Design Example

The make_sim_design.tcl generates a simulation design example along with tool-specific scripts to compile and elaborate the necessary files.

To generate the design example for a Verilog or a mixed-language simulator, run the following script at the end of IP generation:

quartus_sh -t make_sim_design.tcl VERILOG

To generate the design example for a VHDL-only simulator, run the following script:

quartus_sh -t make_sim_design.tcl VHDL

This script generates a sim directory containing one subdirectory for each supported simulation tools. Each subdirectory contains the specific scripts to run simulation with the corresponding tool.

The simulation design example provides a generic example of the core and I/O connectivity for your IP configuration. Functionally, the simulation triggers reads and writes over each group in your configured IP. The following diagram shows a simple one group PHY Lite for Parallel Interfaces Intel^® Agilex™ FPGA IP instantiation in the testbench.

Figure 19. High-Level View of the Simulation Design Example with One Group

3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP

3.1. Release Information

The Intel^® FPGA IP version (X.Y.Z) number can change with each Intel^® Quartus^® Prime software version. A change in:

X indicates a major revision of the IP. If you update the Intel^® Quartus^® Prime software, you must regenerate the IP.
Y indicates the IP includes new features. Regenerate your IP to include these new features.
Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Table 18. PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP Release Information
Item	Description
IP Version	19.3.0
Intel^® Quartus^® Prime Version	20.3
Release Date	2020.09.28

3.2. Functional Description

The PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP utilizes the I/O subsystem in the Intel^® Stratix^® 10 devices. The I/O subsystem is located in the I/O columns of each Intel FPGA devices. For Intel^® Stratix^® 10 devices, each column consists of I/O banks and IOSSM. The number of I/O banks varies according to device packages. Each bank is a group of 48 I/O pins, organized into four I/O lanes with 12 pins for each lane. Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combined to form a single data/strobe group or up to four groups in the same interface. Under certain conditions, two groups from different interfaces can also be supported in the same bank. Refer to the Guidelines: Group Pin Placement for more information about the guidelines to implement multiple interfaces in the same bank.

Important: All Intel^® Stratix^® 10 devices have separate LVDS I/O and 3 V I/O banks. The Intel^® Stratix^® 10 GX 10M variant has denser LVDS I/O banks with a slightly different I/O bank structure compared to other Intel^® Stratix^® 10 variants. The PHY Lite for Parallel Interfaces IP utilizes only the LVDS I/O banks.

Figure 20. Intel^® Stratix^® 10 I/O Bank StructureThis figure shows an example of I/O banks in one Intel^® Stratix^® 10 device. The I/O banks availability and locations vary among Intel^® Stratix^® 10 devices.

3.2.1. Top Level Interfaces

The PHY Lite for Parallel Interfaces IP consists of the following ports:

Clocks and reset
Core data and control (broken down into input and output paths)
I/O (broken down into input and output paths)
Avalon memory-mapped configuration bus (available only when Dynamic Reconfiguration feature is enabled)

Figure 21. Top-Level Interface This figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP interface.

3.2.2. Clocks

The PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP uses a reference clock that is sourced from a dedicated clock pin to the PLL inside the IP. This PLL provides four clock domains for the output and input paths.

Table 19. PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP Clock Domains
Clock Domain	Description
Core clock	This clock is generated internally by the IP and it is used for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phase with the PHY clock for core-to-periphery and periphery-to-core transfers.
PHY clock	This clock is used internally by the IP for PHY circuitry running at the same frequency as the core clock.
VCO clock	This clock is generated internally by the PLL. It is used by both the input and output paths to generate PVT compensated delays in the interpolator.
Interface clock	This is the clock frequency of the external device connected to the FPGA I/Os.

Table 20. PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP Supported Interface FrequencyUse the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with the supported frequencies indicated in the table. Full, half, and quarter core clock rate refers to the ratio of the core clock and interface clock. For example, an interface clock frequency of 800 MHz has full core clock rate of 800 MHz, half core clock rate of 400 MHz, and quarter core clock rate of 200 MHz.
Core Clock Rate	Speed Grade –1 (MHz)		Speed Grade –2 (MHz)		Speed Grade –3 (MHz)
Core Clock Rate	Min	Max	Min	Max	Min	Max
Full	100	333	100	300	100	233
Half	100	667	100	600	100	467
Quarter	100	1200	100	1200	100	933

3.2.2.1. Clock Frequency Relationships

The following equations describe the relationships between the clock domains available in the PHY Lite for Parallel Interfaces IP core.

Core Clock Rate = Interface clock frequency / Core clock frequency

VCO frequency Multiplier Factor = VCO clock frequency ⁸ / Interface clock frequency

⁸ You can obtain this value from the VCO clock frequency parameter under General Tab in the IP parameter editor.

3.2.3. Output Path

The output path consists of a FIFO and an interpolator.

Table 21. Blocks in Output PathThis table lists the blocks in the output path.
Block	Description
Write FIFO	Serializes the output data from the core with a serialization factor of up to 8 (in DDR quarter-rate).
Interpolator	Works with the FIFO block to generate the desired output delay. You can dynamically configure the delay through the Avalon memory-mapped interface. For more information, refer to Dynamic Reconfiguration section.

Figure 22. Output PathThis figure shows the output path for the PHY Lite for Parallel Interfaces IP.

The following figures show the waveform diagrams for the output path. The delays shown in the waveforms are just estimation based on simulations and these values are different with different core clock rate and VCO multiplier.

Figure 23. Output Path ─ Write Latency 0This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:

Interface Frequency: 1000 MHz
VCO Multiplier Factor: 1
User logic clock rate: Quarter rate

Figure 24. Output Path ─ Write Latency 2This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:

Interface Frequency: 1000 MHz
VCO Multiplier Factor: 1
User logic clock rate: Quarter rate

3.2.3.1. Output Path Data Alignment

The data_from_core and oe_from_core signals are arranged in time slices, which are broken down into the individual pins in the group. The first time slice is on the LSBs of the buses, which matches the Intel FPGA PHY interface (AFI) bus ordering of the External Memory Interfaces IP.

Example of time slices with individual pins correlation:

{time(n),time(n-1),time(n-2),... time(0)}

Where time0 = {pin(n),pin(n-1),pin(n-2),...pin0}

Figure 25. Example Output for Quarter Rate DDR

3.2.4. Input Path

The input path of the IP consists of a data path, a strobe path, and a read enable path.

Table 22. Blocks in Data, Strobe, and Read Enable PathsThis table lists the information about these paths.
Path	Description
Data Path	Receives data from external device to the FPGA core logic. The data path consists of a PVT compensated delay chain, a DDIO and a read FIFO. PVT compensated delay chain—Allows per-bit deskew. You can only control the PVT compensated delay chain over Avalon memory-mapped interface. For more information, refer to the Dynamic Reconfiguration topic. DDIO and read FIFO—Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate). The transfer between the DDIO and the read FIFO is a zero-cycle transfer. Signals used in this path are: `data_in`, `data_in_n` (input)—Input data from external device. `data_in_n` is used when data configuration is set to Differential. `data_io`, `data_io_n` (bidirectional)—Input and output data from/to external device. `data_io_n` is used when data configuration is set to Differential. `data_to_core` (output)—Output data to the Intel FPGA core. `phy_clk`—This is an internal clock signal that provides clock to the blocks used in this path. The IP supports SDR input by sending data on single clock cycle from the external device.
Strobe Path	Input strobe (`dqs`) to capture input data from external device. The strobe path consists of pstamble_reg (a gating component) and a PVT compensated delay chain. pstamble_reg—This gating circuitry ensures that only clock edges associated with valid input data are used. PVT compensated delay chain—Provides a phase offset between the strobe and the data (for example, center aligning edge-aligned inputs). Signals used in this path are: `strobe_in`, `strobe_in_n`(input)—Input strobe from external device. `strobe_in_n` is used when strobe configuration is set to Differential or Complimentary. `strobe_io`, `strobe_io_n`(bidirectional)—Input and output strobe from/to external device. `strobe_io_n` is used when strobe configuration is set to Differential or Complimentary. `dqs_clean`(output)—This internal signal is the refined version of `strobe_in` signal. `dqs`(input)—This internal signal is an input strobe to DDIO and Read FIFO in the data path, after phase shift adjustment.
Read and Strobe Enable Path	Generates control signals for strobe calibration and reading data from Read FIFO. The read and strobe enable path consists of VFIFO, DQS_EN FIFO, and an interpolator. VFIFO—Takes the `rdata_en` signal from the core and delays it separately for two outputs, one for the read enable on the Read FIFO, and one for the strobe enable. These delays are calculated at generation time based on the read latency that you provide. Individual control is not necessary, but if you are modifying these delays you can do so individually using dynamic reconfiguration. DQS_EN FIFO and interpolator—Used for the strobe enable delay, the DQS_EN FIFO and interpolator are identical to the Write FIFO and interpolator circuitry in the output path. The DQS_EN FIFO and interpolator are configured to match the output delay for a group with no additional output delay (Write latency = `0`). During dynamic reconfiguration, the DQS_EN FIFO and interpolator can be used for fine grained control of the strobe enable signal. Both of these delays are controlled by the Read latency parameter for the group. Signals used in this path are: `rdata_valid`(output)—This signal determines which data are valid when reading from Read FIFO. This signal is delayed by the Read latency value set in the parameter editor. `rdata_en`(input)—This signal represents the number of expected words to read from the external device. `dqs_enable_in`(input)—This is an internal signal that provides dqs delay value to the pstamble_reg module to process a refined dqs signal. `dqs_enable_out`(output)— This is an internal strobe with the delayed value specified by the dqs_enable_in signal. `phy_clk`—This is an internal clock for VFIFO and Read FIFO modules. `phy_clk_phs`—This is an internal clock for the interpolator. `interpolator_clk`—This is an internal clock for DQS_EN FIFO module.

Figure 26. Input PathThis figure shows the input path of the IP.

Table 23. Read Operation SequenceA read operation is performed as listed in this table.
Read Operation Sequence Number	Operation
1	The core asserts the `rdata_en` signal to the PHY Lite for Parallel Interfaces IP and issues a read command to the external device.
2	VFIFO and DQS_EN FIFO generate the `dqs_enable` signal to pstamble_reg. This signal is delayed by the programmed read latency (which should match the latency of the external device).
3	The pstamble_reg generates `dqs_clean` signal as valid data enters the read path.
4	The Delay Chain (PVT) adjusts the strobe with phase offset between the strobe and the input data (for example, 90° phase shift for DDR center-alignment).
5	The `dqs` signal is then used as strobe to read data from external device into the DDIO and Read FIFO modules.
6	The VFIFO asserts the `read_enable` signal to Read FIFO and the `rdata_valid` signal to the core simultaneously. The PHY Lite for Parallel Interfaces IP sends the captured data to the core with the associated valid signal.

The following figures show the waveform diagrams for the input path. The delays shown in the waveforms are just estimation based on simulations and these values are different with different core clock rate and VCO multiplier.

Figure 27. Input Path ─ Read Latency 7This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:

Interface Frequency: 1000 MHz
VCO Multiplier Factor: 1
User logic clock rate: Quarter rate

3.2.4.1. Input Path Data Alignment

The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to the ordering of the output path. That is, the LSBs of the bus hold the first time slice of data received.

The rdata_valid delay is always set by the IP to match the rdata_en alignment. For example, quarter-rate delays are multiples of four external memory clock cycles (one quarter rate clock cycle).

Figure 28. Example Input (Quarter Rate DDR) - AlignedThe waveform shows an example of aligned reads on the input path of the PHY Lite for Parallel Interfaces IP. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf, which represents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, which represents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core bus matches the data seen on the group_0_data_io bus.

Reading from an unaligned memory address is called unaligned reads. Unaligned reads will result in unaligned rdata_valid and data_to_core with data and valid signals packed to the LSBs. This request causes the IP to do two or more read operations.

Figure 29. Example Input (Quarter Rate DDR) - UnalignedThe waveform shows an example of unaligned reads on the input path of the PHY Lite for Parallel Interfaces IP.

3.2.5. Dynamic Reconfiguration

Because of the asynchronous nature of the PHY, you must perform calibration to achieve timing closure at a high frequency. At a high level, calibration involves reconfiguring input and output delays in the PHY to align data and strobes. With the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP, you can perform the calibration by using dynamic reconfiguration feature. The dynamic reconfiguration feature allows you to modify these delays by writing to a set of control registers using an Avalon memory-mapped interface.

Important: When the dynamic reconfiguration feature is enabled in Intel^® Stratix^® 10 devices, the maximum Avalon memory-mapped interface speed is 167 MHz.

3.2.5.1. RTL Connectivity

The PHY Lite for Parallel Interfaces IP exposes the Avalon memory-mapped master and Avalon memory-mapped slave interfaces when you enable the dynamic reconfiguration feature. If the generated IP is the only PHY Lite for Parallel Interfaces IP (with dynamic reconfiguration) or External Memory Interface IP in the I/O column, connect only the Avalon memory-mapped slave interface with a master in the core. Otherwise, connect Avalon memory-mapped master and slave interfaces as described in the following section.

3.2.5.1.1. Daisy Chain

The I/O column provides a single physical Avalon memory-mapped interface. All IPs in the I/O column that require Avalon memory-mapped interface access the same physical Avalon memory-mapped interface. The system-level RTL for the column reflects this resource limitation by using a daisy chain to connect all dynamically reconfigurable IPs in an I/O column.

The PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP exposes a 31-bit Avalon memory-mapped address, followed by a 4-bit interface ID. These bits are only required for the daisy chain arbitration in RTL simulation, so they are not synthesized during compilation. If only one interface is addressed from the IP, it is sufficient to connect these bits as the interface’s ID.

Important: When using multiple PHY Lite for Parallel Interfaces IPs, you are required to specify the IP that is directly connected to the Avalon memory-mapped bus master, using the First PHYLite Instance in the Avalon Chain parameter. Do not select the parameter if there is an External Memory Interface IP selected as the first instance in the chain, available in the same column.

Figure 30. Logical RTL View to Physical Column PlacementThis figure shows an example of a daisy chain consisting of the External Memory Interface and PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP before and after placement.

Notice that all core controllers must go through the arbitration logic that you created in the core logic to connect to an interface on the daisy chain. The end of the daisy chain should have its master output interface tied to 0.

Note: The Fitter rearranges the Avalon address pins during compilation, therefore use the postfit netlist for proper simulation of the merged I/O column instead of prefit netlist.

3.2.5.2. Address Lookup

If you do not set the pin locations in the .qsf file, the lane addresses and pin placement to an interface changes every time you compile your design in Intel^® Quartus^® Prime software. However, the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP is always generated as if the IP core is the only IP in a column, with lane addresses starting from 0. You need to determine the lane and pin addresses in order to dynamically reconfigure the calibration settings in the IP.

Figure 31. Lane and Pin Placement Dependent AddressesThis figure shows two examples of a placed group with two lanes, 16 data pins and a differential strobe.

To provide a unified way to look up reconfigurable feature addresses for a specific interface both before and after placement, the address information is stored in memory in the I/O column. This memory is addressable over the same Avalon memory-mapped interface used for feature reconfiguration.

You can cache lookups 1 to 4 (8-bytes of information) to have pin and lane translations in one look-up.

Table 24. Memory Lookup ComponentsThis table lists the two main components of the memory lookup.
Component	Description
Global parameter table	Stores pointers to the individual interface parameter tables. The global parameter table lists all interfaces in the column (both the External Memory Interfaces and PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IPs).
Set of individual interface parameter tables	Contain interface specific information. This is where pin-level and lane-level address look-ups are performed.

Figure 32. Memory Overview in Intel^® Stratix^® 10 Devices

Below are the steps to determine the lane and pin addresses from the lookup tables (the sequence corresponds to the sequence in the Memory Overview in Intel^® Stratix^® 10 Devices topic):

Table 25. Parameter Table Lookup Operation SequenceThe base address for PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP is 27'h5000000.
Legend in Memory Overview in Intel^® Stratix^® 10 Devices	Description
1	Search for Interface Parameter Table in Global Parameter Table (cache once per interface) `{1'b0,id{3:0],27'h5000000} + 28'h24 to {1'b0,id{3:0],27'h5000000} + 28'h3C` 1 to 11 look-ups
2	Retrieve number of groups in the interface (cache once per interface) `{1'b0,id[3:0],27'h5000000} + {12'h0,pt_ptr[15:0]} + 28'h4` You can skip this sequence if the number of groups is saved in the core during compilation (for example, hard coded in RTL logic)
3	Retrieve group information (cache once per group) `{1'b0,id[3:0],27'h5000000} + {12'h0,pt_ptr[15:0]} + 28'h8 + grp_num` Not always necessary
4	Retrieve Lane/Pin Address Offsets for group (cache once per group) `{1'b0,id[3:0],27'h5000000} + {12'h0,pt_ptr[15:0]} + {18'h0,group_offset[5:2],2'b00} + {21'd0, grp_num, 2'b00} + 28'hC`
5	Perform lane/pin address translation (cache once per pin) `{1'b0,id[3:0],27'h5000000} + {12'h000,lane_ptr[15:0]} + lane_num` `{1'b0,id[3:0],27'h5000000} + {12'h000,pin_ptr[15:0]} + {17'h0,pin_num[5:0], 1'b0}`
6	Read/Write Avalon Calibration Bus `{1'b0,id[3:0],27'h5000000} + read_from_step_4 + intra_lane_addr`

3.2.5.2.1. Strobes

The first pins listed in the pin address lookup table are the strobes. They are also identified by bits[7:4] = 0xE. For separate strobes, the input strobe pin placement always take precedence. For differential and complementary strobes, the positive pin is the lower index.

Note: You can modify the output phase of differential strobes by writing to either the positive or negative pin. Only one write is necessary. This is also the case for output-only complementary strobes.

3.2.5.2.2. Parameter Table Example

These figures show examples of designs containing two PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IPs, each with one bidirectional group composed of 4 data bits and one strobe. Both interfaces are in the same I/O column and therefore their tables must be merged.

Figure 33. Parameter Table Example for Intel^® Stratix^® 10 Devices

Important: There is no guarantee of the ordering of the interface parameter tables in the merged table. You must perform a search to locate a specific interface parameter.

For more information about the contents of the parameter table, refer to the Address Lookup topic.

3.2.5.3. Reconfiguration Features and Register Addressing

Each reconfigurable feature of the interface has a set of control registers with an associated memory address to store the reconfigurable settings; however, this address is placement dependent. If PHY Lite for Parallel Interfaces IPs and the External Memory Interface IPs share the same I/O column, you must track the addresses of the interface lanes and the pins.

There are two sets of control registers that store the reconfiguration feature settings:

Control/Status registers (CSR) - you can only read the values of these registers. The values are set through the IP parameters. The CSR registers contain the default setting in the IP.
Avalon^® Memory-Mapped registers - you can read and write to these registers using Avalon^® interface. The time for the the PHY Lite for Parallel Interfaces delays to change after writing a new value to the registers via the Avalon bus is dependent on the user's configuration. For example, it takes approximately 50 VCO clock cycles for the output delay to change value. Perform an RTL simulation to show an accurate timing which correlates to the hardware operation.

3.2.5.3.1. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Control Registers Addresses

The following tables show the register bits to construct the control register addresses for each feature.

Table 26. Control Register Address for Pin Output Delay Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[30:27]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	Depending on the Interface ID parameter in the Parameter Editor.	RO
[26:24]	Specify the Avalon controller calibration bus base address.	3'h3	RW	3'h3	RO
[23:21]	Reserved	3'h0	RW	3'h0	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RO
[12:8]	Specify the address for the physical location of a pin within a lane.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic or based on your pin assignment setting in the `.qsf` file.	RW	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic or based on your pin assignment setting in the `.qsf` file.	RO
[7:0]	Reserved	8'hD0	RW	8'hE8	RO

Table 27. Address Register for Pin Input Delay Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[30:27]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	N/A	RO
[26:24]	Specify the Avalon controller calibration bus base address.	3'h3	RW	N/A	RO
[23:21]	Reserved	3'h0	RW	N/A	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	N/A	RO
[12:9]	Reserved	4'hC	RW	N/A	RO
[8:7]	Select DQ pin sets to access.	2'h1: DQ 0 to DQ 5 2'h2: DQ 6 to DQ11	RW	N/A	RO
[6:4]	Select the specific DQ pin to access.	3'h0: DQ 0 and DQ 6 3'h1: DQ 1 and DQ 7 3'h2: DQ 2 and DQ 8 3'h3: DQ 3 and DQ 9 3'h4: DQ 4 and DQ 10 3'h5: DQ 5 and DQ 11	RW	N/A	RO
[3:0]	Reserved	4'h0	RW	N/A	RO

Table 28. Address Register for Strobe Input Delay Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[30:27]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	N/A	RO
[26:24]	Specify the Avalon controller calibration bus base address.	3'h3	RW	N/A	RO
[23:21]	Reserved	3'h0	RW	N/A	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	N/A	RO
[12:0]	Reserved	13'h18E0	RW	N/A	RO

Table 29. Address Register for Strobe Enable Phase Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[30:27]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	Depending on the Interface ID parameter in the Parameter Editor.	RO
[26:24]	Specify the Avalon controller calibration bus base address.	3'h3	RW	3'h3	RO
[23:21]	Reserved	3'h0	RW	3'h0	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RO
[12:0]	Reserved	13'h18F0	RW	13'h1998	RO

Table 30. Address Register for Strobe Enable Delay Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[30:27]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	Depending on the Interface ID parameter in the Parameter Editor.	RO
[26:24]	Specify the Avalon controller calibration bus base address.	3'h3	RW	3'h3	RO
[23:21]	Reserved	3'h0	RW	3'h0	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RO
[12:0]	Reserved	13'h1808	RW	13'h19A8	RO

Table 31. Address Register for Read Valid Delay Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[30:27]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	Depending on the Interface ID parameter in the Parameter Editor.	RO
[26:24]	Specify the Avalon controller calibration bus base address.	3'h3	RW	3'h3	RO
[23:21]	Reserved	3'h0	RW	3'h0	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RO
[12:0]	Reserved	13'h180C	RW	13'h19A4	RO

3.2.5.3.2. Control Registers Description

When you generate a read operation to the control registers addresses, the Avalon interface returns a set of values from the control registers. The following tables show the definition of the bits for each control register.

Table 32. Control Register Description
Feature	Bit	Description
Pin Output Delay	[31:13]	Reserved ⁹
Pin Output Delay	[12:0]	Phase value Strobe minimum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic. Strobe maximum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic. Incremental Delay: 1/128th VCO clock period The CSR value for DQS is set through the Output Strobe Phase parameter during IP instantiation. Note: The pin output delay switches from the CSR register value to the Avalon register value after the first Avalon write. It is only reset to the CSR register value on a reset of the interface.
Pin Input Delay	[31:13]	Reserved ⁹
	[12]	Enable bit to select access to Avalon register or CSR register. 0 = Delay value is 0. CSR register is not available for this feature. 1 = Select delay value from Avalon register
	[11:9]	Reserved ⁹
	[8:0]	Delay value Minimum Setting: 0 Maximum Setting: 511 VCO clock periods Incremental Delay: 1/256th VCO clock period
Strobe Input Delay	[31:13]	Reserved ⁹
	[12]	Enable bit to select access to Avalon register or CSR register. 0 = Delay value is 0. CSR register is not available for this feature. 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group.
	[11:10]	Reserved⁹
	[9:0]	Delay value Minimum Setting: 0 Maximum Setting: 1023 VCO clock periods Incremental Delay: 1/256th VCO clock period Modifying these values must be done on all lanes in a group.
Strobe Enable Phase	[31:16]	Reserved ⁹
	[15]	Enable bit to select access to Avalon register or CSR register. 0 = Select delay value from CSR register. The CSR value is set through the Capture Strobe Phase Shift parameter during IP instantiation. 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group.
	[14:13]	Reserved⁹
	[12:0]	Bit [12:0]: Phase value Minimum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic. Maximum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic. Incremental Delay: 1/128th VCO clock period Modifying these values must be done on all lanes in a group.
Strobe Enable Delay	[31:16]	Reserved⁹
	[15]	Enable bit to select access to Avalon register or CSR register. 0 = Select delay value from CSR register 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group.
	[14:6]	Reserved⁹
	[5:0]	Delay value Minimum Setting: 0 external clock cycles Maximum Setting: 63 external memory clock cycles Incremental Delay: 1 external memory clock cycle Modifying these values must be done on all lanes in a group.
Read Valid Delay	[31:16]	Reserved⁹
	[15]	Enable bit to select access to Avalon register or CSR register. 0 = Select delay value from CSR register 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group.
	[14:7]	Reserved
	[6:0]	Delay value Minimum Setting: 0 external clock cycles Maximum Setting: 127 external memory clock cycles Incremental Delay: 1 external memory clock cycle Modifying these values must be done on all lanes in a group.

Important: For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.

Example of Accessing Dynamic Reconfiguration Control Registers using Parameter Table

The example shows the steps to access Pin Output Delay CSR control register for a strobe pin with the following PHY Lite for Parallel Interfaces IP settings in Intel^® Stratix^® 10 devices:

Number of groups: 2. The group index is automatically set to 0x00.
Interface ID: 0x00
Pin width: 4
Strobe configuration: Single ended
Avalon controller calibration bus base address: 0x3000000

After the project compilation, the interface ID, lane address and pin addresses are stored in the parameter table.

The Pin Output Delay CSR control register has the following bit definition:

Bit	Description	Avalon^® MM Register Value
[30:27]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	0x00 (Interface ID from parameter table)
[26:24]	Specify the Avalon controller calibration bus base address.	0x3
[23:21]	Reserved	0x00
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	0x4b (Lane address from parameter table)
[12:8]	Specify the address for the physical location of a pin within a lane.	0x04 (Strobe pin address from parameter table)
[7:0]	Reserved	0xe8

To read the Pin Output Delay CSR control register for a strobe pin, use the command

avl_in_address[30:0] = {interface id[30:27], calibration bus address[26:24], Reserved[23:21], lanes address[20:13], pin address[12:8], reserved[7:0]}
avl_in_address[30:0] = {0x00, 0x3, 0x00, 0x4B, 0x04, 0xE8}

⁹ Reserved bit ranges must be zero

3.2.5.4. Calibration Guidelines

The PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP allows you to dynamically reconfigure the features of the interface. However, performing calibration is an application specific process. This section provides some general guidelines for calibrating Intel^® Stratix^® 10 I/O architecture.

3.2.5.4.1. Strobe Enable Windowing

The read pointer in the read FIFO buffer gets reset when reads are far apart (80 core clock cycles). However, the data inside the FIFO is not cleared. Therefore, an alternating pattern should be used to find the end to the strobe enable window to avoid reading stale data in the FIFO.

The strobe enable signal turns itself off on the last negative edge of the strobe. Therefore, while finding the enable window, use extra dummy pulses (either extended strobe or reads from memory without asserting the rdata_en signal) to clear the strobe enable.

3.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings

When dynamically reconfiguring the interpolator phase settings, the values must be kept within the ranges below to ensure proper operation of the circuitry.

Table 33. Output and Strobe Enable Minimum and Maximum Phase Settings
VCO Multiplication Factor	Core Rate	Minimum Interpolator Phase			Maximum Interpolator Phase
		Output	Bidirectional	Bidirectional with OCT Enabled
1	Full	0x080	0x100	0x100	0xA80
	Half	0x080	0x100	0x100	0xBC0
	Quarter	0x080	0x100	0x100	0xA00
2	Full	0x080	0x100	0x180	0x1400
	Half	0x080	0x100	0x180	0x1400
	Quarter	0x080	0x100	0x180	0x1400
4	Full	0x080	0x100	0x280	0x1FFF
	Half	0x080	0x100	0x280	0x1FFF
	Quarter	0x080	0x100	0x280	0x1FFF
8	Full	0x080	0x100	0x480	0x1FFF
	Half	0x080	0x100	0x480	0x1FFF
	Quarter	0x080	0x100	0x480	0x1FFF

For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.

3.3. Getting Started

You can instantiate the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP from IP Catalog in Intel^® Quartus^® Prime software. Intel provides an integrated parameter editor that allows you to customize this IP to support a wide variety of applications.

This IP is located in Libraries > Basic Functions > I/O of the IP catalog.

3.3.1. Parameter Settings

Table 34. PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP Parameter Settings
GUI Name	Values	Default Values	Description
Parameter
Number of groups	1 to 18	1	Number of data and strobe groups in the interface. The value is set to 1 by default.
General Tab- these parameters are set on a per interface basis
Clocks
Interface clock frequency	100 MHz - 1200 MHz	533.0 MHz	External memory clock frequency. Note: To achieve timing closure at 534 MHz and above, use dynamic reconfiguration to calibrate the interface. Compile your design with Intel^® Quartus^® Prime with accurate board skew information for final timing analysis.
Use recommended PLL reference clock frequency	On, Off	On	If you want to calculate the PLL reference clock frequency automatically for best performance, turn on this option. If you want to specify your own PLL reference clock frequency, turn off this option.
PLL reference clock frequency	Dependent on desired memory clock frequency	133.25 MHz	PLL reference clock frequency. You must feed a clock of this frequency to the PLL reference clock input of the memory interface. Note: There is no minimum range, but the maximum output frequency is 1600 MHz, limited by the clock network. The minimum range for the `ref_clk` signal is 10 MHz but the maximum is dependent on the speed grade.
VCO clock frequency	Calculated internally by PLL	1066.0 MHz	The frequency of this clock is calculated internally by the PLL based on the interface clock and the core clock rate.
Clock rate of user logic	Full, Half, Quarter	Quarter	Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800 MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200 MHz.
Specify additional output clocks based on existing PLL	On, Off	Off	Exposes additional output clocks from the existing PLL.
Output Clocks Note: These parameters are available only if the Specify additional output clocks based on existing PLL parameter is turned on
Number of additional clocks	0 to 4	0	Specifies the number of additional clocks to be exposed.
outclk[4:0] (Reserved)	—	—	PLL output clocks with the flag (Reserved) in the QSYS GUI are reserved for PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP internal functionality.
Desired Frequency	—	133.25 MHz	Specifies the output clock frequency of the corresponding output clock port, `outclk[]`, in MHz. The minimum and maximum values depend on the device used. The PLL only reads the numerals in the first six decimal places.
Actual Frequency	—	133.25 MHz	Allows you to select the actual output clock frequency from a list of achievable frequencies.
Phase shift units	ps or degrees	ps	Specifies the phase shift unit for the corresponding output clock port, `outclk[]`, in picoseconds (ps) or degrees.
Phase shift	—	469.0 ps	Specifies the requested value for the phase shift. The default value is 0 ps.
Actual phase shift	—	469.0 ps	Allows you to select the actual phase shift from a list of achievable phase shift values. The default value is the closest achievable phase shift to the desired phase shift.
Desired duty cycle	0.0–100.0	50.0 %	Specifies the requested value for the duty cycle.
Actual duty cycle	—	50.0 %	Allows you to select the actual duty cycle from a list of achievable duty cycle values. The default value is the closest achievable duty cycle to the desired duty cycle.
Dynamic Reconfiguration
Use dynamic reconfiguration	On, Off	Off	Exposes an Avalon memory-mapped interface, allowing you to control the configuration of the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP settings.
First PHYLite Instance in the Avalon Chain	On, Off	On	Select this parameter if this IP instance is the first instance in the Avalon chain, connected to the master. This parameter is only available when you select Use dynamic reconfiguration . Important: Do not select this parameter if there is an External Memory Interface IP selected as the first instance in the chain, available in the same column.
Interface ID	—	0	The ID used to identify this interface in the I/O column over the Avalon memory-mapped bus.
I/O Settings
I/O standard	SSTL-12 SSTL-125 SSTL-135 SSTL-15 SSTL-15 Class I SSTL-15 Class II SSTL-18 Class I SSTL-18 Class II 1.2-V-HSTL Class I 1.2-V-HSTL Class II 1.5-V-HSTL Class I 1.5-V-HSTL Class II 1.8-V-HSTL Class I 1.8-V-HSTL Class II 1.2-V POD 1.2-V 1.5-V 1.8-V None	SSTL-15 Class I	Specifies the I/O standard of the interface's strobe and data pins written to the .qip file of the IP instance. When you choose None, the I/O standard is unspecified in the generated IP.
Reference clock I/O configuration	Single-ended, LVDS with on-chip termination, LVDS without on-chip termination	Single-ended	Specify the reference clock I/O configuration.
General Settings
Fast simulation model	On, Off	Off	Turn on this option to reduce PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP simulation time. Note: This option is preliminarily supported in Intel^® Quartus^® Prime v18.1.
Group <x> - these parameters are set on a per group basis
Group <x> Parameter Settings
Copy parameters from another group	On, Off	Off	Select this option when you want to copy the parameter settings from another group. Set Number of groups to more than 1 to enable this option.
Group	1 - 17	1	Choose the group index that you want as the parameter settings source. The changes made to the source is updated automatically to all the target groups. You can only choose the group index which the parameter settings are not copied from another group. Set Number of groups to more than 1 to enable this option.
Group <x> Pin Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Pin type	Input, Output, Bidirectional	Bidirectional	Direction of data pins. This value is set to Bidirectional by default.
Pin width	1 to 48	9	Number of pins in this data/strobe group. A data width up to 48 is achievable if no strobe is used in the group. The number of strobes is controlled by the Use output strobe, Strobe configuration and Use separate capture strobe parameters.
DDR/SDR	DDR, SDR	DDR	Double/single data rate.
Group <x> Input Path Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Read latency	1 to 63 external interface clock cycles	7	Expected read latency of the external device in memory clock cycles. For example, a design with an external clock frequency of 533 MHz in half-rate has a valid read latency range of 5 to 63 external interface clock cycles. Refer to the Read Latency topic for minimum read latency settings based on FPGA core clock rate.
Swap capture strobe polarity	On, Off	Off	Internally swap the negative and positive capture strobe input pins. This feature is only available for complementary strobe configurations.
Capture strobe phase shift	0, 45, 90, 135, 180	90	Internally phase shift the input strobe relative to input data.
Group <x> Output Path Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Write latency	0 to 3 (maximum value is dependent on the rate)	0	Additional delay added to the output data in memory clock cycles. Refer to the Write Latency topic for write latency settings based on FPGA core clock rate.
Use output strobe	On, Off	On	Use an output strobe.
Output strobe phase	0, 45, 90, 135, 180	90	Phase shift of the output strobe relative to the output data.
Group <x> General Data Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Data configuration	Single ended	Single ended	Selects the type of data. Single ended data type uses one pin. Differential data type uses 2 pins. PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP does not support differential data pins. Refer to the I/O Standards topic for a list of supported I/O standards.
Group <x> General Strobe Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Strobe configuration	Single ended, Differential, Complementary	Single ended	Select the type of strobe. A single ended strobe uses one pin, which reduces the maximum possible number of data pins in the group to 47. Differential/complementary strobe types use 2 pins, which reduces the maximum possible number of data pins in the group to 46. Note: The differential strobe configuration uses a differential input buffer, which produces a single clock for the capture DDIO and read FIFO. The complementary strobe configuration uses two single-ended input buffers and clocks the data into the capture DDIO and read FIFO using both clocks (as required by protocols such as QDRII). The output path functionality is the same. Refer to the I/O Standards topic for a list of supported I/O standards.
Use separate strobes	On, Off	Off	Separate the bidirectional strobe into input and output strobe pins. Use separate strobes is only available for a bidirectional data group with the output strobe enabled.
Group <x> OCT Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
OCT enable size	0 - 15 ( Intel^® Stratix^® 10 devices)	1	Specifies the delay between the OCT enable signal assertion and the dqs_enable signal assertion. You must set a value that is large enough to ensure that the OCT is turn on before sampling input data.
Expose termination ports	On, Off	Off	Turn on to expose the series and parallel termination ports to connect separate OCT block. To enable this option, turn off Use Default OCT Values parameter and select a value for Input OCT Value or Output OCT Value parameters.
Use Default OCT Values	—		Use default OCT values based on the I/O standard parameter setting.
Input OCT Value	No termination, <n> ohm with calibration	No termination	Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to the I/O Standards topic. This option is available when the Use Default OCT Values option is disabled.
Output OCT Value	No termination, <n> ohm with calibration, <n> with no calibration	No termination	Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to the I/O Standards topic supported termination values. This option is available when the Use Default OCT Values option is disabled.
Group <x> Timing Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Generate Input Delay Constraints for this group	On, Off	On	Instructs SDC to generate set_input_delay constraints for this group.
Input Strobe Setup Delay Constraint	Constraint in ns	0.03 ns	Specifies the group's input setup delay constraint against the input strobe.
Input Strobe Hold Delay Constraint	Constraint in ns	0.03 ns	Specifies the group's input hold delay constraint against the input strobe.
Inter Symbol Interference of the Read Channel	Constraint in ns	0.09 ns	Specifies the Inter Symbol Interference value for `DQS` signal of read channel. Specify a positive value to decrease the setup and hold slack by half of the entered value.
Generate Output Delay Constraints for this group	On, Off	On	Instructs SDC to generate set_output_delay constraints for this group.
Output Strobe Setup Delay Constraint	Constraint in ns	0.03 ns	Specifies the group's output setup delay constraint against the input strobe.
Output Strobe Hold Delay Constraint	Constraint in ns	0.03 ns	Specifies the group's output hold delay constraint against the input strobe.
Inter Symbol Interference of the Write Channel	Constraint in ns	0.09 ns	Specifies the Inter Symbol Interference value for `DQS` signal of write channel. Specify a positive value to decrease the setup and hold slack by half of the entered value.
Group <x> Dynamic Reconfiguration Timing Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Dynamic Reconfiguration Read Deskew Algorithm	DQ Per-Bit Deskew, DQ Group Deskew, Custom Deskew	DQ Per-Bit Deskew	Specifies the Read Deskew algorithm for Timing Analyzer to use when performing I/O timing analysis: DQ Per-Bit Deskew: Each `DQ` pin is adjusted independently to minimize the skew within the DQ bits. `DQS` signal is adjusted to center-align to the de-skewed DQ bus. Each `DQ` bit may have different delay chain settings. DQ Group Deskew: `DQS` signal is adjusted center-align to the `DQ` bus without de-skewing individual DQ bits. All `DQ` bits within the same group has same delay chain settings. Custom Deskew: `DQS` is aligned based on the recoverable setup and hold slack you defined. You must select Use dynamic reconfiguration option to enable this parameter.
Setup Slack Recoverable of Custom Read Deskew Algorithm	Constraint in ns	0.0 ns	Specifies the amount of positive setup slack available based on your custom read deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Input or Bidirectional and Dynamic Reconfiguration Read Deskew Algorithm is set to Custom Deskew
Hold Slack Recoverable of Custom Read Deskew Algorithm	Constraint in ns	0.0 ns	Specifies the amount of positive hold slack available based on your custom read deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Input or Bidirectional and Dynamic Reconfiguration Read Deskew Algorithm is set to Custom Deskew
Dynamic Reconfiguration Write Deskew Algorithm	DQ Per-Bit Deskew, DQ Group Deskew, Custom Deskew	DQ Per-Bit Deskew	Specifies the Write Deskew algorithm for Timing Analyzer to use when performing I/O timing analysis: DQ Per-Bit Deskew: `DQS` signal is centered to each individual `DQ` bits. Each `DQ` bit may have different delay chain settings. DQ Group Deskew: `DQS` signal is centered to the `DQ` bus group. All `DQ` bits within the same group has same delay chain settings. Custom Deskew: `DQS` is aligned based on the recoverable setup and hold slack you defined. You must select Use dynamic reconfiguration option to enable this parameter.
Setup Slack Recoverable of Custom Write Deskew Algorithm	Constraint in ns	0.0 ns	Specifies the amount of positive setup slack available based on your custom write deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Output or Bidirectional and Dynamic Reconfiguration Write Deskew Algorithm is set to Custom Deskew
Hold Slack Recoverable of Custom Write Deskew Algorithm	Constraint in ns	0.0 ns	Specifies the amount of positive hold slack available based on your custom write deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Output or Bidirectional and Dynamic Reconfiguration Write Deskew Algorithm is set to Custom Deskew

3.3.1.1. Read Latency

Table 35. Minimum Read Latency This table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate	VCO Multiplier Factor	Read Latency (External Memory Clock Cycle)
Full rate	1	4
	2	4
	4	3
	8	3
Half rate	1	5
	2	5
	4	4
	8	4
Quarter rate	1	7
	2	7
	4	7
	8	7

3.3.1.2. Write Latency

Table 36. Maximum Write LatencyThis shows the maximum write latency value supported by PHY Lite for Parallel Interfaces IP based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate	VCO Multiplier Factor	Write Latency (External Memory Clock Cycle)
Full rate	1	0
	2	0
	4	0
	8	0
Half rate	1	1
	2	1
	4	1
	8	1
Quarter rate	1	3
	2	3
	4	3
	8	2

3.3.2. Signals

3.3.2.1. Clock and Reset Interface Signals

Table 37. Clock and Reset Interface Signals
Signal Name	Direction	Width	Description
`ref_clk`	Input	1	Reference clock for the PLL. The reference clock must be synchronous with `strobe_in` to ensure the `dqs_enable` signal is in-sync with `strobe_in`.
`reset_n`	Input	1	Resets the interface. This signal is asynchronous.
`interface_locked`	Output	1	Interface `locked` signal from PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP to core logic. This signal indicates that the PLL and PHY circuitry are locked. Data transfer should starts after the assertion of this signal.
`core_clk_out`	Output	1	Use this core clock in the core-to-periphery transfer of soft logic data and control signals. The `core_clk_out` frequency depends on the interface frequency and clock rate of user logic parameter.
`pll_extra_clock[0..3]`	Output	4	These are the additional output clock signals generated by PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP when you enable Specify additional output clocks based on existing PLL parameter.
`pll_locked`	Output	1	This is the locked signal for the additional output clocks generated by the IP.

3.3.2.2. Output Path Signals

Table 38. Output Path SignalsOutput path signals are signals that are available when you set the **Pin Type** parameter to either **Output** or **Bidirectional**. The <n> in the signal names below represents the group number in the IP.
Signal Name	Direction	Width	Description
`group_<n>_oe_from_core`	Input	Quarter-rate: 4 x `PIN_WIDTH` Half-rate: 2 x `PIN_WIDTH` Full-rate: 1 x `PIN_WIDTH`	Output enable signal from core logic. Synchronous to the `core_clk_out` output from the IP.
`group_<n>_data_from_core`	Input	Quarter rate-DDR: 8 x `PIN_WIDTH` Half-rate DDR: 4 x `PIN_WIDTH` Full-rate DDR: 2 x `PIN_WIDTH` Quarter-rate SDR: 4 x `PIN_WIDTH` Half-rate SDR: 2 x `PIN_WIDTH` Full-rate SDR: 1 x `PIN_WIDTH`	Data signal from core logic. Synchronous to the `core_clk_out` output from the IP.
`group_<n>_strobe_out_in`	Input	Quarter-rate: 8 Half-rate: 4 Full-rate: 2	Strobe signal from core logic. Synchronous to the `core_clk_out` output from the IP. Note: This path is always DDR.
`group_<n>_strobe_out_en`	Input	Quarter-rate: 4 Half-rate: 2 Full-rate: 1	Strobe output enable from core logic. Synchronous to the `core_clk_out` output from the IP.
`group_<n>_data_out`/`group_<n>_data_io`	Output/Bidirectional	1 to 48 if data configuration is Single Ended	Data output from PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP. Synchronous to the `group_<n>_strobe_out` or `group_<n>_strobe_io` output from the IP. If the Pin Type parameter is set to Output, the `group_<n>_data_out` signals are used. If the Pin Type parameter is set to Bidirectional, the `group_<n>_data_io` signals are used. Note: PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP does not support differential data pins.
`group_<n>_strobe_out` /`group_<n>_strobe_io`	Output/Bidirectional	1	Positive output strobe fromPHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP. If the Pin Type is set to Output, the `group_<n>_strobe_out` signal is used. If the Pin Type is set to Bidirectional the `group_<n>_strobe_io` signal is used. The Use Separate Strobes parameter forces the use of the `group_<n>_strobe_out` signal with a Bidirectional Pin Type.
`group_<n>_strobe_out_n`/`group_<n>_strobe_io_n`	Output/Bidirectional	1	Negative output strobe from PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP. This is used if the Strobe Configuration is set to Differential or Complementary. If the Pin Type is set to Output, the `group_<n>_strobe_out_n` signal is used. If the Pin Type is set to Bidirectional, the `group_<n>_strobe_io_n` signal is used. The Use Separate Strobes parameter forces the use of the `group_<n>_strobe_out_n` signal with a Bidirectional Pin Type.

3.3.2.3. Input Path Signals

Table 39. Input Path SignalsInput path signals are signals that are available when you set the **Pin Type** parameter to **Input** or Bidirectional. The <n> in the signal names below represents the group number in the IP.
Signal Name	Direction	Width	Description
`group_<n>_data_to_core`	Output	Quarter-rate DDR: 8 x `PIN_WIDTH` Half-rate DDR: 4 x `PIN_WIDTH` Full-rate DDR: 2 x `PIN_WIDTH` Quarter-rate SDR: 4 x `PIN_WIDTH` Half-rate SDR: 2 x `PIN_WIDTH` Full-rate SDR: 1 x `PIN_WIDTH`	Output data to the core logic. Valid on `rdata_valid`. Synchronous to the `core_clk` output from the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP.
`group_<n>_rdata_en`	Input	Quarter-rate: 4 Half-rate: 2 Full-rate: 1	This signal represents the number of expected words to read from the external device. This signal is set to high after a read command is issued. Synchronous to the `core_clk` output from the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP. When using the IP as a receiver, assert this signal after `interface_locked` signal is asserted and `strobe_in` is stable.
`group_<n>_rdata_valid`	Output	Quarter-rate: 4 Half-rate: 2 Full-rate: 1	This signal determines which data are valid when reading from Read FIFO. Delayed by `READ_LATENCY` with margin and aligned to the core clock rate. For example, in quarter-rate, the delay is a multiple of 4 external clock cycles. Synchronous to the `core_clk` output from the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP.
`group_<n>_data_in/` `group_<n>_data_io`	Input/Bidirectional	1 to 48 if data configuration is Single Ended	Input and output data from/to external device. Synchronous to the `group_<n>_strobe_in` or `group_<n>_strobe_io` input. The first data_in must be associated with positive edge of `strobe_in`/`strobe_io`. If the pin type is set to Input, the `data_in` ports are used. If the pin type is set to bidirectional, the `data_io` ports are used. Note: PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP does not support differential data pins.
`group_<n>_strobe_in`/`group_<n>_strobe_io`	Input/Bidirectional	1	Input and output strobe from/to external device. If the pin type is set to Input, the `group_<n>_strobe_in` signal is used. If the pin type is set to Bidirectional, the `group_<n>_strobe_io` signal is used.
`group_<n>_strobe_in_n` `group_<n>_strobe_io_n`	Input/Bidirectional	1	Negative strobe from/to external device. This is used if the Strobe Configuration parameter is set to Differential or Complementary. If the pin type is set to Input, the `strobe_in_n` signal is used. If the pin type is set to Bidirectional, the `strobe_io_n` signal is used.

3.3.2.4. Avalon Configuration Bus Interface Signals

The PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP exposes the Avalon memory-mapped-MM slave and Avalon memory-mapped master interfaces when you perform dynamic reconfiguration. Connect the Avalon memory-mapped slave to either a master in the core or the master interface of either an PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP or the External Memory Interface IP to be placed in the same column. You can only connect the master interface to the slave interface of a PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP or External Memory Interface IP to be placed in the same column.

Table 40. Avalon Memory-Mapped Master Interface Signals
Signal Name	Direction	Width	Description
`avl_clk`	Input	1	Avalon interface clock. Maximum Avalon memory-mapped interface clock for PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP is 167 MHz.
`avl_reset_n`	Input	1	Reset input synchronous to `avl_clk`.
`avl_read`	Input	1	Read request from `io_aux`. This signal is synchronous to the `avl_clk` input.
`avl_write`	Input	1	Write request from `io_aux`. This signal is synchronous to the `avl_clk` input.
`avl_byteenable`	Input	4	Controls which bytes should be written on `avl_writedata`.
`avl_address`	Input	31	Address from `io_aux`. This signal is synchronous to the `avl_clk` input.
`avl_readdata`	Output	32	Read data to `io_aux`. This signal is synchronous to the `avl_clk` input.
`avl_writedata`	Input	32	Write data from `io_aux`. This signal is synchronous to the `avl_clk` input.
`avl_readdata_valid`	Output	1	Indicates that read data has returned.
`avl_waitrequest`	Output	1	Stalls upstream logic when it is asserted.

Table 41. Avalon Memory-Mapped Slave Interface Signals
Signal Name	Direction	Width	Description
`avl_out_clk`	Output	1	Connect this signal to the input Avalon interface of another PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP or the External Memory Interfaces IP.
`avl_out_reset_n`	Output	1	Connect this signal to the input Avalon interface of another PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP or the External Memory Interfaces IP.
`avl_out_read`	Output	1	Indicates read transaction.
`avl_out_write`	Output	1	Indicates write transaction.
`avl_out_byteenable`	Output	4	Controls which bytes should be written on `avl_out_writedata`.
`avl_out_writedata`	Output	32	The data packet associated with the write transaction.
`avl_out_address`	Output	31	Avalon address (in byte granularity). Value is identical to `avl_address` but with zeroes padded on the LSBs.
`avl_out_readdata`	Input	32	The data packet associated with `avl_out_readdata_valid`.
`avl_out_readdata_valid`	Input	1	Indicates that read data has returned.
`avl_out_waitrequest`	Input	1	Stalls upstream logic when it is asserted.

3.3.2.5. Termination Signals

Table 42. Termination SignalsThe termination signals are signals that are available when you enable the **Expose termination ports** parameter. The <n> in the signal names below represents the group number in the IP.
Signal Name	Direction	Width	Description
`group_<n>_seriesterminationcontrol`	Input	16	Connect this signal to the series termination control signal of the OCT Intel^® FPGA IP to receive series termination code to calibrate R_s.
`group_<n>_parallelterminationcontrol`	Input	16	Connect this signal to the parallel termination control signal of the OCT Intel^® FPGA IP to receive parallel termination code to calibrate R_t.

3.4. I/O Standards

The PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.

Table 43. I/O Standards and Termination Values
I/O Standard	Valid Input Terminations (Ω)	Valid Output Terminations (Ω)	RZQ (Ω)	Differential/Complementary I/O Support Important: PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP does not support differential data pins.
SSTL-12	60, 120	40, 60,240	240	Yes
SSTL-125	40, 60, 120	34, 40	240	Yes
SSTL-135	40, 60, 120	34, 40	240	Yes
SSTL-15	40, 60, 120	34, 40	240	Yes
SSTL-15 Class I	50	50	100	Yes
SSTL-15 Class II	50	25	100	Yes
SSTL-18 Class I	50	50	100	Yes
SSTL-18 Class II	50	25	100	Yes
1.2-V HSTL Class I	50	50	100	Yes
1.2-V HSTL Class II	50	25	100	Yes
1.5-V HSTL Class I	50	50	100	Yes
1.5-V HSTL Class II	50	25	100	Yes
1.8-V HSTL Class I	50	50	100	Yes
1.8-V HSTL Class II	50	25	100	Yes
1.2-V POD	34, 40, 48, 60, 80, 120, 240	34, 40, 48, 60	240	Yes
1.2-V	—	—	—	No
1.5-V	—	—	—	No
1.8-V	—	—	—	No

3.4.1. Input Buffer Reference Voltage (VREF)

The POD I/O standard allows configurable VREF. By default, the externally provided VREF is used and using an internal VREF requires the following .qsf assignments:

set_instance_assignment -name VREF_MODE <mode> -to <pin_name>

Note: The VREF settings are at the lane level, so all pins using a lane must have the same VREF settings (including GPIOs).

Table 44. VREF_MODE Description
VREF Mode	Description
EXTERNAL	Use the external VREF. This is the default.
CALIBRATED	Use internal VREF generated using VREF codes from the Avalon memory-mapped reconfiguration bus.
VCCIO_45	Use internal VREF generated using static VREF code. VREF is 45% of VCCIO
VCCIO_50	Use internal VREF generated using static VREF code. VREF is 50% of VCCIO
VCCIO_55	Use internal VREF generated using static VREF code. VREF is 55% of VCCIO
VCCIO_65	Use internal VREF generated using static VREF code. VREF is 65% of VCCIO
VCCIO_70	Use internal VREF generated using static VREF code. VREF is 70% of VCCIO
VCCIO_75	Use internal VREF generated using static VREF code. VREF is 75% of VCCIO

Figure 34. VREF

3.4.1.1. Calibrated VREF Settings

Table 45. Calibrated VREF SettingsThis table lists the calibrated VREF settings that you can set over the Avalon memory-mapped calibration bus. This table is applicable to all Intel FPGA devices.
avl_writedata[5:0]	% of VCCIO
000000	60.00%
000001	60.64%
000010	61.28%
000011	61.92%
000100	62.56%
000101	63.20%
000110	63.84%
000111	64.48%
001000	65.12%
001001	65.76%
001010	66.40%
001011	67.04%
001100	67.68%
001101	68.32%
001110	68.96%
001111	69.60%
010000	70.24%
010001	70.88%
010010	71.52%
010011	72.16%
010100	72.80%
010101	73.44%
010110	74.08%
010111	74.72%
011000	75.36%
011001	76.00%
011010	76.64%
011011	77.28%
011100	77.92%
011101	78.56%
011110	79.20%
011111	79.84%
100000	80.48%
100001	81.12%
100010	81.76%
100011	82.40%
100100	83.04%
100101	83.68%
100110	84.32%
100111	84.96%
101000	85.60%
101001	86.24%
101010	86.88%
101011	87.52%
101100	88.16%
101101	88.80%
101110	89.44%
101111	90.08%
110000	90.72%
110001	91.36%
110010	92.00%
110011 -> 111111	Reserved

3.4.2. On-Chip Termination (OCT)

PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP provides valid OCT settings for each group (refer to the I/O Standards topic). These settings are written to the .qip of the instance during generation. If you select an I/O standard that supports OCT in the General tab, you can use the OCT blocks provided in Intel^® Stratix^® 10 devices.

You can instantiate the OCT block in one of two ways:

Using RZQ_GROUP assignment in the assignment editor, or
Manual insertion of OCT block

3.4.2.1. RZQ_GROUP Assignment

The RZQ_GROUP assignment creates the OCT Intel FPGA IP without modifying the RTL. The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the Fitter creates the pin name along with the OCT Intel FPGA IP and its corresponding connections. This allows you to create a group of pins to be calibrated by an existing or non-existing OCT and the Fitter ensures the legality of the design. You must associate the terminated pins of the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP instance with an RZQ pin at the system level manually.

Use the following steps to set RZQ pin locations for the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP:

In the Group <x> OCT Settings tab, disable Use Default OCT Values and Expose termination ports.

Figure 35. Group <x> OCT Settings Parameter Settings
Generate the IP or instantiate the IP into your project.
You can view the available RZQ pins location in the Pin Planner. Go to Pin Planner > Tasks > OCT Pins and double click the RZQ. The available RZQ pins are display in the pin grid diagram.
You can modify the qsf in your project to change the default RZQ location using the following command:
```
set_location_assignment <rzq_capable_pin_location> –to <user_defined_rzq_pin_name>
```

Use the following command to associate the terminated pins of the IP with the RZQ pin:

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <altera_phylite_strobe_pin>

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <altera_phylite_data_pin[*]>

where * represents all the data pins within the same group.

This is an example of a qsf file with modified RZQ pin location assignments:

set_location_assignment PIN_AH3 -to octrzq
set_instance_assignment -name IO_STANDARD "1.5 V" -to octrzq
set_instance_assignment -name RZQ_GROUP OCTRZQ -to group_0_io_interface_conduit_end_io_strobe_io
set_instance_assignment -name RZQ_GROUP OCTRZQ -to group_0_io_interface_conduit_end_io_data_io[*]

Compile the project.
To verify that the Intel^® Quartus^® Prime has successfully created and assigned the RZQ pin to the correct location, go to Pin Planner > Node Name and look for <user_defined_rzq_pin_name> with the assigned pin location in the list.

3.4.2.2. Manual Insertion of OCT Block

You may also instantiate the OCT Intel FPGA IP separately in your project and connect the termination ports to the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP.

Expose the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP termination ports by disable Use Default OCT Values.
Select the available OCT values in the Input OCT Value parameter. This displays the Expose termination ports parameter.
Note: For supported input and output OCT values, refer to the I/O Standards topic.
Select Expose termination ports to expose the termination ports in the IP.
Connect the termination ports to a OCT Intel FPGA IP either in power-up or user mode.

Figure 36. RTL View of PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP Interfacing with OCT Intel FPGA IP in User Mode

3.5. Design Guidelines

3.5.1. Guidelines: Group Pin Placement

Follow these guidelines to place the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP group pins.

All groups in a PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP must be placed across a contiguous set of lanes. The number of lanes depends on the number of pins used by the group.
Two groups, from either the same or different PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP, cannot share an I/O lane.
For PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP instance that spans more than one I/O bank, all groups in the interface must be placed across a contiguous set of banks within an I/O column. The number of I/O banks required depends on the memory interface width.
Pins that are not used in an I/O bank are available as general purpose I/O (GPIO) pins.
To constrain groups from separate PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies, and the same voltage settings. The number of I/O banks must be at least as many as the number of PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP interfaces.
A reference clock network can only span across maximum of 6 I/O banks.
You cannot share the OCT termination block across the I/O column. You can associate the terminated pins of the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP instance with an RZQ pin through RZQ_GROUP assignment.

Table 46. Group Pin Placement PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP does not support `DQS` for X4.
Number of Pins in Group	Valid DQS Group in a Bank	Valid Index in a Bank
1-12	DQS for X8/X9	{0-11}/{12-23}/{24-35}/{36-47}
13-24	DQS for X16/X18	{0-23}/{24-47}
25-48	DQS for X32/X36	{0-47}

3.5.2. Reference Clock

You are recommended to source the reference clock to the PHY Lite for Parallel Interfaces IP from a dedicated clock pin. Use the clock pin in one of the I/O banks used by the PHY Lite for Parallel Interfaces IP. You must use contiguous I/O banks to implement multiple interfaces (consisting of a combination of External Memory Interface and PHY Lite for Parallel Interfaces IPs). If you use the same reference clock for these interfaces, place the reference clock in any of the contiguous I/O banks.

Note: For Intel^® Quartus^® Prime software version 18.1 or later, you may see error warning message for design with encrypted IOPLL IP. The auto-generated .sdc files of the IOPLL IP are not supported if you use encryption. You must manually create the .sdc file using create_clock and create_generated_clock to replace the auto-generated .sdc file in the design for refclk and output clocks.

3.5.3. Reset

You can source the reset to the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP from an external pin or from the core. If you source the reset from an external pin, you must configure the I/O standard of the reset signal in the .qsf file with the following command:

set_location_asignment <PIN_NUMBER> -to <signal_name>

3.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank

You can instantiate multiple PHY Lite for Parallel Interfaces Intel FPGA IPs within an I/O column. To constrain groups from separate PHY Lite for Parallel Interfaces IP instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies and the same voltage settings.

3.5.5. Dynamic Reconfiguration

If you are using the dynamic reconfiguration feature, all interfaces of the External Memory Interfaces and PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IPs in the same I/O column must share the reset signal. Multiple IPs requiring Avalon core access require daisy chain connectivity.

3.5.6. Timing

The Intel^® Quartus^® Prime software generates the required timing constraints to analyze the timing of the PHY Lite for Parallel Interfaces IP on the all Intel FPGA devices.

3.5.6.1. Timing Components

Table 47. Timing Components
Circuit Category	Timing Paths	Source	Destination	Description
Source synchronous and optionally calibrated ¹⁰	Read Path	Memory Device	DQ Capture Register	Source synchronous timing paths—paths where clock and data signals are passed from the transmitting devices to the receiving devices. Optionally calibrated paths—paths with delay elements that are dynamically reconfigurable to achieve timing closure, especially at higher frequency, and to maximize the timing margins. You can calibrate these paths by implementing an algorithm and turning on the optional dynamic reconfiguration feature. An example of the calibrated path is the FPGA to memory device write path, in which you can dynamically reconfigure the delay elements to, for instance, compensate the skew due to process voltage temperature variation.
Source synchronous and optionally calibrated ¹⁰	Write Path	FPGA DQ/DQS	Memory Device
Internal FPGA	Core to PHY Lite for Parallel Interfaces IP Path	Core Registers	Write FIFO	The internal FPGA paths are paths in the FPGA fabric. The Timing Analyzer reports the corresponding timing margins.
Internal FPGA	PHY Lite for Parallel Interfaces IP to Core	Read FIFO	Core Registers

¹⁰ Can be optionally calibrated by using dynamic reconfiguration.

3.5.6.2. Timing Constraints and Files

To successfully constrain the timing for PHY Lite for Parallel Interfaces IP, the IP generates a set of timing files. You can locate these timing files in the <variation_name> directory:

<variation_name> .sdc
<variation_name> _ip_parameters.tcl
<variation_name> _pin_map.tcl
<variation_name> _parameters.tcl
<variation_name> _report_timing.tcl
<variation_name> _report_timing_core.tcl

3.5.6.2.1. <variation_name>.sdc

You can find the location of the <variation_name> .sdc file in the .qip or .qsys, which is generated during the IP generation. The <variation_name> .sdc allows the Fitter to optimize timing margins with timing driven compilation and allows the Timing Analyzer to analyze the timing of your design.

The IP uses <variation_name> .sdc for the following operations:

Creating clocks on PLL inputs
Creating generated clocks
Calling derive_clock_uncertainty
Creating set_output_delay and set_input_delay constraints to analyze the timing of the read and write paths

3.5.6.2.2. <variation_name>_parameter.tcl

The <variation_name>_parameters.tcl file is a script that lists the following PHY Lite for Parallel Interfaces IP parameters used in the .sdc file and report timing scripts:

Jitter
Simultaneous switching noise
Calibration uncertainties

3.5.6.2.3. <variation_name>_ip_parameters.tcl

The <variation_name> _ip_parameters.tcl file lists the PHY Lite for Parallel Interfaces IP parameters and is read by the <variation_name> .sdc.

3.5.6.2.4. <variation_name>_pin_map.tcl

The <variation_name>_pin_map.tcl is a TCL library of functions and procedures that <variation_name>.sdc uses.

3.5.6.2.5. <variation_name>_report_timing.tcl

The <variation_name>_report_timing.tcl file is a script that contains timing analysis flow and reports the timing slack for your variation. This script runs automatically during calibration (during static timing analysis) by sourcing the following files:

<variation_name>_ip_parameters.tcl
<variation_name>_parameters.tcl
<variation_name>_pin_map.tcl
<variation_name>_report_timing_core.tcl

You can also run <variation_name>_report_timing.tcl with the Report DDR function in the Timing Analyzer. This script runs for every instance of the same variation.

Note: You can only use the Report DDR function if you enable the dynamic reconfiguration feature.

3.5.6.2.6. <variation_name>_report_timing_core.tcl

The <variation_name>_report_timing_core.tcl file is a script that <variation_name>_report_timing.tcl uses to calculate the timing slack for your variation. <variation_name>_report_timing_core.tcl runs automatically during compilation.

3.5.6.3. Timing Analysis

Table 48. Timing AnalysisThis table lists the timing analysis performed in the I/O and FPGA for the PHY Lite for Parallel Interfaces IP.
Location	Description
I/O	The PHY Lite for Parallel Interfaces IP generation creates the appropriate generated clock settings for the read strobe on the read path and the write strobe of the write path, according to their strobe type (singled-ended, complementary, or differential) and their interface type (SDR or DDR) in the following format: Clock name for read strobe—`<pin_name>_IN`. Clock name for the write path—`<pin_name>` for positive strobe. Clock name for the write path—`<pin_name>_neg` for negative strobe. The `set_false_path`, `set_input_delay` and `set_output_delay` constraints are also generated to ensure proper timing analysis of the PHY Lite for Parallel Interfaces IP.
FPGA	The PHY Lite for Parallel Interfaces IP generation creates the clock settings for the user core clock and the periphery clock in the following formats: user core clock—`<variation_name>_usr_clk` periphery clock— `<variation_name>_phy_clk*` The user core clock is for user core logic and the periphery clock is the clock for the PHY Lite for Parallel Interfaces IP periphery hardware. With these clock settings, the Timing Analyzer analyzes the timing of this IP interface transfer and within core transfer correctly.

3.5.6.4. Timing Closure Guidelines

3.5.6.4.1. Timing Closure: Dynamic Reconfiguration

You can dynamically reconfigure the delay elements in the I/O to optimize process, voltage, temperature variations by implementing a calibration algorithm that modifies the input and output delays.

3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints

The Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint parameters ensure that an input to the FPGA from the an external device meets the internal FPGA setup and hold time requirements. The value of these constraints are calculated from various timing parameters such as setup and hold timing of the external device, board trace delay and clock skew.

The following figure shows the considerations required to determine the Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint values. The external device sends data and clock to the FPGA through interconnect on the board. The FPGA uses the clock signal from the external device to latch input data to the FPGA. The maximum and minimum values of the output clock T_CO are values available in the external device data sheet.

Figure 37. Input Strobe Setup and Hold Delay Constraints Considerations

The following is the derivation for Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint:

Input strobe setup delay constraint = Maximum board skew + maximum T_CO

Input strobe hold delay constraint = Minimum board skew + minimum T_CO

where maximum board skew = maximum data trace - minimum clock trace

minimum board skew = minimum data trace - maximum clock trace

maximum T_CO = DQS to DQ skew (t_DQSQ)

minimum T_CO = Data hold skew (t_QHS)

Figure 38. Input Data Cycle Timing Diagram

The following is an example of Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint calculations with:

Input clock frequency = 100 MHz
Board skew estimation = ± 0.03 ns
Maximum T_CO = 0.6 ns
Minimum T_CO = -0.6 ns

Input Strobe Setup Delay Constraint = 0.03 + 0.6= 0.63 ns

Input Strobe Hold Delay Constraint = -0.03 + (-0.6) = -0.63 ns

Insert these values into the Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint parameters and run timing analysis with the Timing Analyzer tool. The following is an example of delay result from the Timing Analyzer tool.

Figure 39. Example of Input Strobe Delay Value from Timing Analyzer

3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints

The Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint ensure that the data output from the FPGA to the external device meets the setup and hold requirements of the external device. The value of these constraints are calculated from various timing parameters such as setup and hold timing of the external device, board trace delay and clock skew.

The following figure shows the considerations required to determine the Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint values. These constraints are depending on the clock and data traces, and setup and hold requirements of the external device. With system-centric delays, you can obtain the setup and hold requirements, clock delay, and data trace delay values for the external device through the device data sheet.

Figure 40. Output Strobe Setup and Hold Delay Constraints Considerations

The following is the derivation for Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint:

Output strobe setup delay constraint = Maximum board skew + maximum t_SU

Output strobe hold delay constraint = Minimum board skew + minimum t_H

where maximum board skew = maximum data trace - minimum clock trace

minimum board skew = minimum data trace - maximum clock trace

maximum t_SU = clock setup time

minimum t_H = clock hold time

Figure 41. DDR Output Cycle Timing Diagram

The following is an example of Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint calculations with:

Input clock frequency = 100 MHz
Board skew estimation = ± 0.03 ns
Maximum t_SU = 0.75 ns
Minimum t_H = 0.75 ns

Output Strobe Setup Delay Constraint = 0.03 + 0.75= 0.78 ns

Output Strobe Hold Delay Constraint = -0.03 - 0.75 = -0.78 ns

Insert these values into the Output Strobe Setup Delay Constraint and Output Strobe Hold Delay Constraint parameters and run timing analysis with the Timing Analyzer tool. The following is an example of delay result from the Timing Analyzer tool.

Figure 42. Example of Output Strobe Delay Value from Timing Analyzer

3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data

If the input data is not edge-aligned, use the following equation to calculate the new Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint values:

New Input Strobe Setup Delay Constraint Value = Clock to data skew - Input Strobe Phase Shift (nanosecond)

New Input Strobe Hold Delay Constraint Value = Clock to data skew + Input Strobe Phase Shift (nanosecond)

For example, if the memory speed is 800 MHz and the clock to data skew value is 0.1 with input data phase shift of 90°:

New Input Strobe Setup Delay Constraint value = 0.1-1.25*(90/360) = -0.2125ns.

New Input Strobe Hold Delay Constraint value = 0.1 + 1.25*(90/360) = 0.4125ns

Important: Ensure that you make the changes in the Input Strobe Setup Delay Constraint and Input Strobe Hold Delay Constraint parameters.

3.5.6.4.5. I/O Timing Violation

It can be difficult to achieve timing closure for I/O paths at high frequency. Use the dynamic reconfiguration feature to calibrate the I/O path.

3.5.6.4.6. Internal FPGA Path Timing Violation

If timing violations are reported at the internal FPGA paths (such as <instance_name>_usr_clk or <instance_name>_phy_clk_*), consider the following guidelines:

If setup time violation is reported, lower the clock rate of the user logic from full-rate to half-rate, or from half-rate to quarter-rate. This reduces the frequency requirement of the IP core-to-core data transfer.

If hold time violation is observed, you may increase hold uncertainty value to equal or higher than the violation amount in the .sdc file. This will provide a more stringent constraint during design fitting. Following is an example to increase the hold uncertainty.

If {$::quartus(nameofexecutable) != “quartus_sta”}{

	set_clock_uncertainty -from [<instance_name>_phy_clk_*] -to [<instance_name>_phy_clk_*] -hold 0.3 -add

	set_clock_uncertainty -from [<instance_name>_usr_clk] -to [<instance_name>_usr_clk] -hold 0.3 -add

}

However, increasing the hold uncertainty value may cause setup timing violation at slow corner.

3.6. Design Example

The PHY Lite for Parallel Interfaces IP is able to generate a design example that matches the same configuration chosen for the IP. The design example is a simple design that does not target any specific application; however you can use the design example as a reference on how to instantiate the IP and what behavior to expect in a simulation.

Note: The .qsys files are for internal use during design example generation only. You should not edit the files.

3.6.1. Generate the Design Example

You can generate a design example by clicking Generating Example Design in the IP Parameter Editor.

The software generates a user defined directory in which the design example files reside.

There are two variants of design example available for PHY Lite for Parallel Interfaces IP:

Variant without dynamic reconfiguration design example
Variant with dynamic reconfiguration design example

Table 49. PHY Lite for Parallel Interfaces IP Design Example Variants
Design Example Variant		Design Files	Description
Dynamic Reconfiguration	OFF	ed_synth.qsys (synthesis only)	Consists of configurablePHY Lite for Parallel Interfaces IP instance.
	OFF	ed_sim.qsys (simulation only)	Consists of sim_ctrl, agent, addr/cmd and PHY Lite for Parallel Interfaces IP instances. Perform read and write transaction verification.
	ON	ed_sim.qsys (simulation only)	Consists of sim_ctrl, agent, addr/cmd, cfg_ctrl, avl_ctrl and PHY Lite for Parallel Interfaces IP instances. This design example demonstrates dynamic reconfiguration and uses FSM to perform calibration.

3.6.1.1. Design Example without Dynamic Reconfiguration

When the Enable dynamic reconfiguration option is not selected, Intel^® Quartus^® Prime software generates a design example of PHY Lite for Parallel Interfaces IP without a dynamic reconfiguration module.

This design example consists of simulation and synthesis design files.

3.6.1.1.1. Generate the Hardware Design Example

The make_qii_design.tcl generates a synthesizable hardware design example along with a Quartus project, ready for compilation.

To generate synthesizable design example, run the following script at the end of IP generation:

quartus_sh -t make_qii_design.tcl

To specify an exact device to use, run the following script:

quartus_sh -t make_qii_design.tcl [device_name]

This script generates a qii directory containing a project called ed_synth.qpf. You can open and compile this project with the Intel^® Quartus^® Prime software.

3.6.1.1.2. Generate the Simulation Design Example

The make_sim_design.tcl generates a simulation design example along with tool-specific scripts to compile and elaborate the necessary files.

To generate the design example for a Verilog or a mixed-language simulator, run the following script at the end of IP generation:

quartus_sh -t make_sim_design.tcl VERILOG

To generate the design example for a VHDL-only simulator, run the following script:

quartus_sh -t make_sim_design.tcl VHDL

The simulation design example provides a generic example of the core and I/O connectivity for your IP configuration. Functionally, the simulation iterates over each group in your configured IP and performs basic reads/writes to an associated agent (one per group) in the testbench. A simple one group PHY Lite for Parallel Interfaces IP instantiation in the testbench is used for basic address and command outputs to the agent. A side bus between the sim_ctrl and the agents is used to check that the reads and writes are valid.

Figure 43. High-Level View of the Simulation Design Example with One Group

3.6.1.2. Dynamic Reconfiguration Design Examples

When you select the Use dynamic reconfiguration option and click Generate Example Design, Intel^® Quartus^® Prime software generates the dynamic reconfiguration with configuration control module design examples:

3.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine

This design example is a simulation design example that is capable to perform dynamic calibration for PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP.

Features

Perform dynamic reconfiguration using Avalon controller
Read and write transactions monitoring
Delay values monitoring

Software Requirements

Intel^® Quartus^® Prime software
Active-HDL, ModelSim* - Intel^® FPGA Edition, NCsim or VCS Simulator

Functional Description

This design example introduces the cfg_ctrl and avl_ctrl blocks, which work with the sim_ctrl module to demonstrate the basic functionality of the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP Avalon memory-mapped based reconfiguration. The agent is also modified to insert delays on the data and clocks, which the new modules will compensate for.

NOTE: The cfg_ctrl module performs a simplistic reconfiguration of the interface that stops at the first working delay values. The design example only support simulation. A robust calibration algorithm should sweep over the entire valid range of delays to choose the correct value for the application.

Figure 44. Dynamic Reconfiguration Using Finite State Machine Design ExampleThis figure shows a high-level view of the simulation design example with one group.

Table 50. Design Components Description
Component	Description
ref_clk_gen	Generates clock to reset_gen, PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP ADDR/CMD (ref_clk), and PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP (ref_clk) blocks.
reset_gen	Generates reset to PHY Lite for Parallel Interfaces ADDR/CMD and PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP blocks.
sim_ctrl	Generates read/write commands to PHY Lite for Parallel Interfaces ADDR/CMD block. Generates side read/write commands and data to Agent block. Generates strobe and data to Driver block.
Driver	Generates strobe and data for each group and to PHY Lite for Parallel Interfaces_ Intel^® Stratix^® 10 FPGA IP block.
PHY Lite for Parallel Interfaces ADDR/CMD	Passing read/write commands and command clock from sim_ctrl to Agent.
Agent	FIFO to store data from PHY Lite for Parallel Interfaces DUT and side read/write data from sim_ctrl block.
cfg_ctrl	This is configuration control block which performs read and write delay calibration before test begin. The calibration results is passed to the PHY Lite for Parallel Interfaces Intel^® Stratix^® 10 FPGA IP through Avalon Controller. Contains 4 FSMs: Main FSM – cfg_ctrl state Write Strobe FSM – Calibration state for Output Strobe Read Strobe FSM – Calibration state for Input Strobe Read Enable FSM – Calibration state for Strobe Enable and Input Data
avl_ctrl	The Avalon controller is used to perform address translation to store delay settings from the calibration done by cfg_ctrl block.

Figure 45. Design Example Functional Flow

Generate the Dynamic Reconfiguration with Configuration Control Module Design Example

In Intel^® Quartus^® Prime software, instantiate PHY Lite for Parallel Interfaces IP core.
Customize parameter settings per your requirement and turn on the Use dynamic reconfiguration option.
Click Generate Example Design. Specify a directory name to generate the design example.
To generate Verilog or mixed-language simulation files, go to the design example directory and run the following script in Nios II Command Shell.
```
quartus_sh -t make_sim_design.tcl VERILOG
```
To generate VHDL simulation files, go to the design example directory and run the following script in Nios II Command Shell.
```
quartus_sh -t make_sim_design.tcl VHDL
```

Run the Dynamic Reconfiguration with Configuration Control Design Example

Follow these steps to compile and simulate the design:

Change the working directory to <Example Design>\sim\ed_sim\sim\<Simulator> .

Run the simulation script for the simulator of your choice. Refer to the table below.

Simulator	Working Directory	Steps
Modelsim	`<Example Design>`\sim\ed_sim\sim\mentor	do msim_setup.tcl ld_debug Add desired signals into the waveform window. run -all
VCS	`<Example Design>`\sim\ed_sim\sim\synopsys\vcs	sh vcs_setup.sh
VCSMX	`<Example Design>`\sim\ed_sim\sim\synopsys\vcsmx	sh vcsmx_setup.sh
NCSim	`<Example Design>`\sim\ed_sim\sim\cadence	sh ncsim_setup.sh
Aldec	`Example Design`\sim\ed_sim\sim\aldec	do rivierapro_setup.tcl ld_debug Add desired signals into the waveform window. run -all

Figure 46. Sample of Simulation Output

4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs

4.1. Release Information

The Intel^® FPGA IP version (X.Y.Z) number can change with each Intel^® Quartus^® Prime software version. A change in:

X indicates a major revision of the IP. If you update the Intel^® Quartus^® Prime software, you must regenerate the IP.
Y indicates the IP includes new features. Regenerate your IP to include these new features.
Z indicates the IP includes minor changes. Regenerate your IP to include these changes.

Table 51. PHY Lite for Parallel Interfaces Intel^® Arria^® 10 FPGA IP Release Information
Item	Description
IP Version	19.3.0
Intel^® Quartus^® Prime Version	20.3
Release Date	2020.09.28

Table 52. PHY Lite for Parallel Interfaces Intel^® Cyclone^® 10 GX FPGA IP Release Information
Item	Description
IP Version	19.1
Intel^® Quartus^® Prime Version	20.3
Release Date	2020.09.28

4.2. Functional Description

The PHY Lite for Parallel Interfaces IP utilizes the I/O subsystem in the Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX devices. The I/O subsystem is located in the I/O columns of each Intel FPGA devices. For Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX devices, each column consists of I/O banks and I/O aux. The number of I/O banks varies according to device packages. Each bank is a group of 48 I/O pins, organized into four I/O lanes with 12 pins for each lane. Each I/O lane contains the DDR-PHY input and output path logic for 12 I/Os as well as a DQS logic block. All four lanes in a bank can be combined to form a single data/strobe group or up to four groups in the same interface. Under certain conditions, two groups from different interfaces can also be supported in the same bank.

Figure 47. Intel^® Arria^® 10 I/O Bank Structure

Figure 48. Intel^® Cyclone^® 10 GX I/O Bank Structure

4.2.1. Top Level Interfaces

The PHY Lite for Parallel Interfaces IP consists of the following ports:

Clocks and reset
Core data and control (broken down into input and output paths)
I/O (broken down into input and output paths)
Avalon memory-mapped configuration bus (available only when Dynamic Reconfiguration feature is enabled)

Figure 49. Top-Level Interface This figure shows the top-level diagram of the PHY Lite for Parallel Interfaces IP interface.

4.2.2. Clocks

Table 53. PHY Lite for Parallel Interfaces IP Clock Domains
Clock Domain	Description
Core clock	This clock is generated internally by the IP and it is used for all transfers between the FPGA core fabric and I/O banks. The clock phase alignment circuitry ensures that this clock is kept in phase with the PHY clock for core-to-periphery and periphery-to-core transfers.
PHY clock	This clock is used internally by the IP for PHY circuitry running at the same frequency as the core clock.
VCO clock	This clock is generated internally by the PLL. It is used by both the input and output paths to generate PVT compensated delays in the interpolator.
Interface clock	This is the clock frequency of the external device connected to the FPGA I/Os.

Table 54. PHY Lite for Parallel Interfaces Intel^® Arria^® 10 FPGA IP Supported Interface Frequency Use the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with the supported frequencies indicated in the table. Full, half, and quarter core clock rate refers to the ratio of the core clock and interface clock. For example, an interface clock frequency of 800 MHz has full core clock rate of 800 MHz, half core clock rate of 400 MHz, and quarter core clock rate of 200 MHz.
Core Clock Rate	Speed Grade –1 (MHz)		Speed Grade –2 (MHz)		Speed Grade –3 (MHz)
Core Clock Rate	Min	Max	Min	Max	Min	Max
Full	100	333	100	266	100	233
Half	100	667	100	533	100	466
Quarter	100	1200	100	1067	100	933

Table 55. PHY Lite for Parallel Interfaces Intel^® Cyclone^® 10 GX FPGA IP Supported Interface Frequency Use the Timing Analyzer to perform timing closure to ensure your design fulfilled all timing constraints with the supported frequencies indicated in the table. Full, half, and quarter core clock rate refers to the ratio of the core clock and interface clock. For example, an interface clock frequency of 800 MHz has full core clock rate of 800 MHz, half core clock rate of 400 MHz, and quarter core clock rate of 200 MHz.
Core Clock Rate	Speed Grade –5 (MHz)		Speed Grade –6 (MHz)
Core Clock Rate	Min	Max	Min	Max
Full	100	266	100	233
Half	100	533	100	466
Quarter	100	1067	100	933

4.2.2.1. Clock Frequency Relationships

The following equations describe the relationships between the clock domains available in the PHY Lite for Parallel Interfaces IP core.

Core Clock Rate = Interface clock frequency / Core clock frequency

VCO frequency Multiplier Factor = VCO clock frequency ¹¹ / Interface clock frequency

¹¹ You can obtain this value from the VCO clock frequency parameter under General Tab in the IP parameter editor.

4.2.3. Output Path

The output path consists of a FIFO and an interpolator.

Table 56. Blocks in Output PathThis table lists the blocks in the output path.
Block	Description
Write FIFO	Serializes the output data from the core with a serialization factor of up to 8 (in DDR quarter-rate).
Interpolator	Works with the FIFO block to generate the desired output delay. You can dynamically configure the delay through the Avalon memory-mapped interface. For more information, refer to Dynamic Reconfiguration section.

Figure 50. Output PathThis figure shows the output path for the PHY Lite for Parallel Interfaces IP.

Figure 51. Output Path ─ Write Latency 0This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:

Interface Frequency: 1000 MHz
VCO Multiplier Factor: 1
User logic clock rate: Quarter rate

Figure 52. Output Path ─ Write Latency 2This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:

Interface Frequency: 1000 MHz
VCO Multiplier Factor: 1
User logic clock rate: Quarter rate

4.2.3.1. Output Path Data Alignment

Example of time slices with individual pins correlation:

{time(n),time(n-1),time(n-2),... time(0)}

Where time0 = {pin(n),pin(n-1),pin(n-2),...pin0}

Figure 53. Example Output for Quarter Rate DDR

4.2.4. Input Path

The input path of the IP consists of a data path, a strobe path, and a read enable path.

Table 57. Blocks in Data, Strobe, and Read Enable PathsThis table lists the information about these paths.
Path	Description
Data Path	Receives data from external device to the FPGA core logic. The data path consists of a PVT compensated delay chain, a DDIO and a read FIFO. PVT compensated delay chain—Allows per-bit deskew. You can only control the PVT compensated delay chain over Avalon memory-mapped interface. For more information, refer to Dynamic Reconfiguration. DDIO and read FIFO—Responsible for deserialization with a factor of up to 8 (in DDR quarter-rate). The transfer between the DDIO and the read FIFO is a zero-cycle transfer. Signals used in this path are: `group_data_in` (input)—Input data from external device. `group_data_io` (bidirectional)—Input and output data from/to external device. `group_data_to_core` (output)—Output data to the core logic. `phy_clk`—This is an internal clock signal that provides clock to the blocks used in this path. The IP supports SDR input by sending data on single clock cycle from the external device.
Strobe Path	Input strobe (`dqs`) to capture input data from external device. The strobe path consists of pstamble_reg (a gating component) and a PVT compensated delay chain. pstamble_reg—This gating circuitry ensures that only clock edges associated with valid input data are used. PVT compensated delay chain—Provides a phase offset between the strobe and the data (for example, center aligning edge-aligned inputs). Signals used in this path are: `group_strobe_in`, group_`strobe_in_n` (input)—Input strobe from external device. `group_strobe_in_n` is used when strobe configuration is set to Differential. `group_strobe_io`, `group_strobe_io_n` (bidirectional)—Input and output strobe from/to external device. `strobe_io_n` is used when strobe configuration is set to Differential. `dqs_clean`(output)—This internal signal is the refined version of `group_strobe_in` signal. `dqs` (input)—This internal signal is an input strobe to DDIO and Read FIFO in the data path, after phase shift adjustment.
Read and Strobe Enable Path	Generates control signals for strobe calibration and reading data from Read FIFO. The read and strobe enable path consists of VFIFO, DQS_EN FIFO, and an interpolator. VFIFO—Takes the `rdata_en` signal from the core and delays it separately for two outputs, one for the read enable on the Read FIFO, and one for the strobe enable. These delays are calculated at generation time based on the read latency that you provide. Individual control is not necessary, but if you are modifying these delays you can do so individually using dynamic reconfiguration. DQS_EN FIFO and interpolator—Used for the strobe enable delay, the DQS_EN FIFO and interpolator are identical to the Write FIFO and interpolator circuitry in the output path. The DQS_EN FIFO and interpolator are configured to match the output delay for a group with no additional output delay (Write latency = `0`). During dynamic reconfiguration, the DQS_EN FIFO and interpolator can be used for fine grained control of the strobe enable signal. Both of these delays are controlled by the Read latency parameter for the group. Signals used in this path are: `rdata_valid`(output)—This signal determines which data are valid when reading from Read FIFO. This signal is delayed by the Read latency value set in the parameter editor. `group_rdata_en` (input)—This signal represents the number of expected words to read from the external device. `dqs_enable_in` (input)—This is an internal signal that provides dqs delay value to the pstamble_reg module to process a refined dqs signal. `dqs_enable_out` (output)— This is an internal strobe with the delayed value specified by the dqs_enable_in signal. `phy_clk`—This is an internal clock for VFIFO and Read FIFO modules. `phy_clk_phs`—This is an internal clock for the interpolator. `interpolator_clk`—This is an internal clock for DQS_EN FIFO module.

Figure 54. Input PathThis figure shows the input path of the IP.

Table 58. Read Operation SequenceA read operation is performed as listed in this table.
Read Operation Sequence Number	Operation
1	The core asserts the `rdata_en` signal to the PHY Lite for Parallel Interfaces IP and issues a read command to the external device.
2	VFIFO and DQS_EN FIFO generate the `dqs_enable` signal to pstamble_reg. This signal is delayed by the programmed read latency (which should match the latency of the external device).
3	The pstamble_reg generates `dqs_clean` signal as valid data enters the read path.
4	The Delay Chain (PVT) adjusts the strobe with phase offset between the strobe and the input data (for example, 90° phase shift for DDR center-alignment).
5	The `dqs` signal is then used as strobe to read data from external device into the DDIO and Read FIFO modules.
6	The VFIFO asserts the `read_enable` signal to Read FIFO and the `rdata_valid` signal to the core simultaneously. The PHY Lite for Parallel Interfaces IP sends the captured data to the core with the associated valid signal.

Figure 55. Input Path ─ Read Latency 7This simulation is based on the following PHY Lite for Parallel Interfaces IP configurations:

Interface Frequency: 1000 MHz
VCO Multiplier Factor: 1
User logic clock rate: Quarter rate

4.2.4.1. Input Path Data Alignment

The bus ordering of data_to_core, rdata_en, and rdata_valid is identical to the ordering of the output path. That is, the LSBs of the bus hold the first time slice of data received.

The rdata_valid delay is always set by the IP to match the rdata_en alignment. For example, quarter-rate delays are multiples of four external memory clock cycles (one quarter rate clock cycle).

Figure 56. Example Input (Quarter Rate DDR) - AlignedThe waveform shows an example of aligned reads on the input path of the PHY Lite for Parallel Interfaces IP. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf, which represents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, which represents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core bus matches the data seen on the group_0_data_io bus.

Figure 57. Example Input (Quarter Rate DDR) - UnalignedThe waveform shows an example of unaligned reads on the input path of the PHY Lite for Parallel Interfaces IP.

4.2.5. Dynamic Reconfiguration

Because of the asynchronous nature of the PHY, you must perform calibration to achieve timing closure at a high frequency. At a high level, calibration involves reconfiguring input and output delays in the PHY to align data and strobes. With the PHY Lite for Parallel Interfaces IP, you can perform the calibration by using dynamic reconfiguration feature. The dynamic reconfiguration feature allows you to modify these delays by writing to a set of control registers using an Avalon memory-mapped interface.

4.2.5.1. RTL Connectivity

4.2.5.1.1. Daisy Chain

The I/O column provides a single physical Avalon memory-mapped interface. All IP in the I/O column that require Avalon memory-mapped interface access the same physical Avalon memory-mapped interface. The system-level RTL for the column reflects this resource limitation by using a daisy chain to connect all dynamically reconfigurable IPs in an I/O column.

For PHY Lite for Parallel Interfaces Intel^® Arria^® 10 FPGA IP and PHY Lite for Parallel Interfaces Intel^® Cyclone^® 10 GX FPGA IPs, the Avalon memory-mapped address is 28 bits where the top 4-bits are the ID of the interface to be addressed in the daisy chain. These bits are only required for the daisy chain arbitration in RTL simulation, so they are not synthesized during compilation. If only one interface is addressed from the IP, it is sufficient to connect these bits as the interface’s ID.

Figure 58. Logical RTL View to Physical Column PlacementThis figure shows an example of a daisy chain consisting of the External Memory Interface and PHY Lite for Parallel Interfaces IP before and after placement.

Notice that all core controllers must go through the arbitration logic that you created in the FPGA core logic to connect to an interface on the daisy chain. The end of the daisy chain should have its master output interface tied to 0.

Note: The Fitter rearranges the Avalon address pins during compilation, therefore use the postfit netlist for proper simulation of the merged I/O column instead of prefit netlist.

4.2.5.2. Address Lookup

If you do not set the pin locations in the .qsf file, the lane addresses and pin placement to an interface changes every time you compile your design in Intel^® Quartus^® Prime software. However, the PHY Lite for Parallel Interfaces IP is always generated as if the IP is the only IP in a column, with lane addresses starting from 0. You need to determine the lane and pin addresses in order to dynamically reconfigure the calibration settings in the IP core.

Figure 59. Lane and Pin Placement Dependent AddressesThis figure shows two examples of a placed group with two lanes, 16 data pins and a differential strobe.

You can cache lookups 1 to 4 (8-bytes of information) to have pin and lane translations in one look-up.

Table 59. Memory Lookup ComponentsThis table lists the two main components of the memory lookup.
Component	Description
Global parameter table	Stores pointers to the individual interface parameter tables. The global parameter table lists all interfaces in the column (both the External Memory Interfaces and PHY Lite for Parallel Interfaces IP).
Set of individual interface parameter tables	Contain interface specific information. This is where pin-level and lane-level address look-ups are performed.

Figure 60. Memory Overview in Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX Devices

Below are the steps to determine the lane and pin addresses from the lookup tables (the sequence corresponds to the sequence in the preceding figure. ):

Table 60. Parameter Table Lookup Operation SequenceThe base address for PHY Lite for Parallel Interfaces Intel^® Arria^® 10 and PHY Lite for Parallel Interfaces Intel^® Cyclone^® 10 GX FPGA IP are 24'h00E000.
Legend in Memory Overview in Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX Devices	Description
1	Search for Interface Parameter Table in Global Parameter Table (cache once per interface) `{id{3:0],24'h00E000} + 28'h18 to {id{3:0],24'h00E0000} + 28'h2C` 1 to 11 look-ups
2	Retrieve number of groups in the interface (cache once per interface) `{id[3:0],24'h00E000} + {4'h0,pt_ptr[23:0]} + 4'h4` You can skip this sequence if the number of groups is saved in the core during compilation (for example, hard coded in RTL logic)
3	Retrieve group information (cache once per group) `{id[3:0],24'h00E000} + {4'h0,pt_ptr[23:0]} + 24'h4 + grp_num` Not always necessary
4	Retrieve Lane/Pin Address Offsets for group (cache once per group) `{id[3:0],24'h00E000} + pt_ptr + {22'd0,num_grps[7:2],2'b00} + 28'd8`
5	Perform lane/pin address translation (cache once per pin) `{id[3:0],24'h00E000} + {12'h000,lane_ptr[15:0]} + lane_num` `{id[3:0],24'h00E000} + {12'h000,pin_ptr[15:0]} + {17'h0,pin_num[5:0], 1'b0}`
6	Read/Write Avalon Calibration Bus `{id[3:0],24'h800000} + read_from_step_4 + intra_lane_addr`

4.2.5.2.1. Strobes

4.2.5.2.2. Parameter Table Example

These figures show examples of designs containing two PHY Lite for Parallel Interfaces IP, each with one bidirectional group composed of 4 data bits and one strobe. Both interfaces are in the same I/O column and therefore their tables must be merged.

Figure 61. Parameter Table Example for Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX Devices

Important: There is no guarantee of the ordering of the interface parameter tables in the merged table. You must perform a search to locate a specific interface parameter.

For more information about the contents of the parameter table, refer to the Address Lookup topic.

4.2.5.3. Reconfiguration Features and Register Addressing

There are two sets of control registers that store the reconfiguration feature settings:

Control/Status registers (CSR) - you can only read the values of these registers. The values are set through the IP parameters. The CSR registers contain the default setting in the IP.
Avalon^® Memory-Mapped registers - you can read and write to these registers using Avalon^® interface. The time for the the PHY Lite for Parallel Interfaces delays to change after writing a new value to the registers via the Avalon bus is dependent on the user's configuration. For example, it takes approximately 50 VCO clock cycles for the output delay to change value. Perform an RTL simulation to show an accurate timing which correlates to the hardware operation.

4.2.5.3.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers

The following tables show the register bits to construct the control register addresses for each feature.

Table 61. Address Register for Pin Output Delay Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[31:28]	Reserved	4'h0	RW	4'h0	RO
[27:24]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	Depending on the Interface ID parameter in the Parameter Editor.	RO
[23:21]	Specify the Avalon controller calibration bus base address.	3'h4	RW	3'h4	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RO
[12:8]	Specify the address for the physical location of a pin within a lane.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic or based on your pin assignment setting in the `.qsf` file.	RW	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic or based on your pin assignment setting in the `.qsf` file.	RO
[7:0]	Reserved	8'hD0	RW	8'hE8	RO

Table 62. Address Register for Pin Input Delay Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[31:28]	Reserved	4'h0	RW	N/A	RO
[27:24]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	N/A	RO
[23:21]	Specify the Avalon controller calibration bus base address.	3'h4	RW	N/A	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	N/A	RO
[12:9]	Reserved	4'hC	RW	N/A	RO
[8:7]	Select DQ pin sets to access.	2'h1: DQ 0 to DQ 5 2'h2: DQ 6 to DQ11	RW	N/A	RO
[6:4]	Select the specific DQ pin to access.	3'h0: DQ 0 and DQ 6 3'h1: DQ 1 and DQ 7 3'h2: DQ 2 and DQ 8 3'h3: DQ 3 and DQ 9 3'h4: DQ 4 and DQ 10 3'h5: DQ 5 and DQ 11	RW	N/A	RO
[3:0]	Reserved	4'h0	RW	N/A	RO

Table 63. Address Register for Strobe Input Delay Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[31:28]	Reserved	4'h0	RW	N/A	RO
[27:24]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	N/A	RO
[23:21]	Specify the Avalon controller calibration bus base address.	3'h4	RW	N/A	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	N/A	RO
[12:0]	Reserved	13'18E0	RW	N/A	RO

Table 64. Address Register for Strobe Enable Phase Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[31:28]	Reserved	4'h0	RW	4'h0	RO
[27:24]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	Depending on the Interface ID parameter in the Parameter Editor.	RO
[23:21]	Specify the Avalon controller calibration bus base address.	3'h4	RW	3'h4	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RO
[12:0]	Reserved	13h'18F0	RW	13'h1998	RO

Table 65. Address Register for Strobe Enable Delay Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[31:28]	Reserved	4'h0	RW	4'h0	RO
[27:24]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	Depending on the Interface ID parameter in the Parameter Editor.	RO
[23:21]	Specify the Avalon controller calibration bus base address.	3'h4	RW	3'h4	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RO
[12:0]	Reserved	13'h1808	RW	13'h19A8	RO

Table 66. Address Register for Read Valid Delay Feature
Bit	Description	Avalon^® MM Register		CSR Register
Bit	Description	Value	Access Type	Value	Access Type
[31:28]	Reserved	4'h0	RW	4'h0	RO
[27:24]	Specify the PHY Lite for Parallel Interfaces IP interface ID.	Depending on the Interface ID parameter in the Parameter Editor.	RW	Depending on the Interface ID parameter in the Parameter Editor.	RO
[23:21]	Specify the Avalon controller calibration bus base address.	3'h4	RW	3'h4	RO
[20:13]	Specify the lane address of an interface. This value is depending on the resource fitting process during compilation.	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RW	You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic.	RO
[12:0]	Reserved	13'h180C	RW	13'h19A4	RO

4.2.5.3.2. Control Registers Description

Table 67. Control Register Description
Feature	Bit	Description
Pin Output Delay	[31:13]	Reserved ¹²
Pin Output Delay	[12:0]	Phase value Strobe minimum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic. Strobe maximum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic. Incremental Delay: 1/128th VCO clock period The CSR value for DQS is set through the Output Strobe Phase parameter during IP instantiation. Note: The pin output delay switches from the CSR register value to the Avalon register value after the first Avalon write. It is only reset to the CSR register value on a reset of the interface.
Pin Input Delay	[31:13]	Reserved ¹²
	[12]	Enable bit to select access to Avalon register or CSR register. 0 = Delay value is 0. CSR register is not available for this feature. 1 = Select delay value from Avalon register
	[11:9]	Reserved ¹²
	[8:0]	Delay value Minimum Setting: 0 Maximum Setting: 511 VCO clock periods Incremental Delay: 1/256th VCO clock period
Strobe Input Delay	[31:13]	Reserved ¹²
	[12]	Enable bit to select access to Avalon register or CSR register. 0 = Delay value is 0. CSR register is not available for this feature. 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group.
	[11:10]	Reserved¹²
	[9:0]	Delay value Minimum Setting: 0 Maximum Setting: 1023 VCO clock periods Incremental Delay: 1/256th VCO clock period Modifying these values must be done on all lanes in a group.
Strobe Enable Phase	[31:16]	Reserved ¹²
	[15]	Enable bit to select access to Avalon register or CSR register. 0 = Select delay value from CSR register. The CSR value is set through the Capture Strobe Phase Shift parameter during IP instantiation. 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group.
	[14:13]	Reserved¹²
	[12:0]	Bit [12:0]: Phase value Minimum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic. Maximum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic. Incremental Delay: 1/128th VCO clock period Modifying these values must be done on all lanes in a group.
Strobe Enable Delay	[31:16]	Reserved¹²
	[15]	Enable bit to select access to Avalon register or CSR register. 0 = Select delay value from CSR register 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group.
	[14:6]	Reserved¹²
	[5:0]	Delay value Minimum Setting: 0 external clock cycles Maximum Setting: 63 external memory clock cycles Incremental Delay: 1 external memory clock cycle Modifying these values must be done on all lanes in a group.
Read Valid Delay	[31:16]	Reserved¹²
	[15]	Enable bit to select access to Avalon register or CSR register. 0 = Select delay value from CSR register 1 = Select delay value from Avalon register Modifying these values must be done on all lanes in a group.
	[14:7]	Reserved
	[6:0]	Delay value Minimum Setting: 0 external clock cycles Maximum Setting: 127 external memory clock cycles Incremental Delay: 1 external memory clock cycle Modifying these values must be done on all lanes in a group.

Important: For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.

¹² Reserved bit ranges must be zero

4.2.5.4. Calibration Guidelines

The PHY Lite for Parallel Interfaces IP allows you to dynamically reconfigure the features of the interface. However, performing calibration is an application specific process. This section provides some general guidelines for calibrating the Intel^® Arria^® 10, and Intel^® Cyclone^® 10 GX I/O architecture.

4.2.5.4.1. Strobe Enable Windowing

4.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings

When dynamically reconfiguring the interpolator phase settings, the values must be kept within the ranges below to ensure proper operation of the circuitry.

Table 68. Output and Strobe Enable Minimum and Maximum Phase Settings
VCO Multiplication Factor	Core Rate	Minimum Interpolator Phase			Maximum Interpolator Phase
		Output	Bidirectional	Bidirectional with OCT Enabled
1	Full	0x080	0x100	0x100	0xA80
	Half	0x080	0x100	0x100	0xBC0
	Quarter	0x080	0x100	0x100	0xA00
2	Full	0x080	0x100	0x180	0x1400
	Half	0x080	0x100	0x180	0x1400
	Quarter	0x080	0x100	0x180	0x1400
4	Full	0x080	0x100	0x280	0x1FFF
	Half	0x080	0x100	0x280	0x1FFF
	Quarter	0x080	0x100	0x280	0x1FFF
8	Full	0x080	0x100	0x480	0x1FFF
	Half	0x080	0x100	0x480	0x1FFF
	Quarter	0x080	0x100	0x480	0x1FFF

For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.

4.3. Getting Started

You can instantiate the PHY Lite for Parallel Interfaces IP from IP Catalog in Intel^® Quartus^® Prime software. Intel provides an integrated parameter editor that allows you to customize this IP to support a wide variety of applications.

This IP is located in Libraries > Basic Functions > I/O of the IP catalog.

4.3.1. Parameter Settings

Table 69. PHY Lite for Parallel Interfaces IP Parameter Settings
GUI Name	Values	Default Values	Description
Parameter
Number of groups	1 to 18	1	Number of data and strobe groups in the interface. The value is set to 1 by default.
General Tab- these parameters are set on a per interface basis
Clocks
Interface clock frequency	100 MHz - 1200 MHz	533.0 MHz	External memory clock frequency. Note: To achieve timing closure at 534 MHz and above, use dynamic reconfiguration to calibrate the interface. Compile your design with Intel^® Quartus^® Prime with accurate board skew information for final timing analysis.
Use recommended PLL reference clock frequency	On, Off	On	If you want to calculate the PLL reference clock frequency automatically for best performance, turn on this option. If you want to specify your own PLL reference clock frequency, turn off this option.
PLL reference clock frequency	Dependent on desired memory clock frequency	133.25 MHz	PLL reference clock frequency. You must feed a clock of this frequency to the PLL reference clock input of the memory interface. Note: There is no minimum range, but the maximum output frequency is 1600 MHz, limited by the clock network. The minimum range for the `ref_clk` signal is 10 MHz but the maximum is dependent on the speed grade.
VCO clock frequency	Calculated internally by PLL	1066.0 MHz	The frequency of this clock is calculated internally by the PLL based on the interface clock and the core clock rate.
Clock rate of user logic	Full, Half, Quarter	Quarter	Determines the clock frequency of user logic in relation to the memory clock frequency. For example, if the memory clock sent from the FPGA to the memory device is toggling at 800 MHz, a "Quarter rate" interface means that the user logic in the FPGA runs at 200 MHz.
Specify additional output clocks based on existing PLL	On, Off	Off	Exposes additional output clocks from the existing PLL. Important: PHY Lite for Parallel Interfaces in Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX devices do not support exposing additional output clocks when VCO frequency is below 600 MHz.
Output Clocks Note: These parameters are available only if the Specify additional output clocks based on existing PLL parameter is turned on
Number of additional clocks	0 to 4	0	Specifies the number of additional clocks to be exposed. Important: PHY Lite for Parallel Interfaces in Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX devices do not support exposing additional output clocks when VCO frequency is below 600 MHz.
outclk[4:0] (Reserved)	—	—	PLL output clocks with the flag (Reserved) in the QSYS GUI are reserved for PHY Lite for Parallel Interfaces IP internal functionality.
Desired Frequency	—	133.25 MHz	Specifies the output clock frequency of the corresponding output clock port, `outclk[]`, in MHz. The minimum and maximum values depend on the device used. The PLL only reads the numerals in the first six decimal places.
Actual Frequency	—	133.25 MHz	Allows you to select the actual output clock frequency from a list of achievable frequencies.
Phase shift units	ps or degrees	ps	Specifies the phase shift unit for the corresponding output clock port, `outclk[]`, in picoseconds (ps) or degrees.
Phase shift	—	469.0 ps	Specifies the requested value for the phase shift. The default value is 0 ps.
Actual phase shift	—	469.0 ps	Allows you to select the actual phase shift from a list of achievable phase shift values. The default value is the closest achievable phase shift to the desired phase shift.
Desired duty cycle	0.0–100.0	50.0 %	Specifies the requested value for the duty cycle.
Actual duty cycle	—	50.0 %	Allows you to select the actual duty cycle from a list of achievable duty cycle values. The default value is the closest achievable duty cycle to the desired duty cycle.
Dynamic Reconfiguration
Use dynamic reconfiguration	On, Off	Off	Exposes an Avalon memory-mapped interface, allowing you to control the configuration of the PHY Lite for Parallel Interfaces IP settings.
Interface ID	—	0	The ID used to identify this interface in the I/O column over the Avalon memory-mapped bus.
I/O Settings
I/O standard	SSTL-12 SSTL-125 SSTL-135 SSTL-15 SSTL-15 Class I SSTL-15 Class II SSTL-18 Class I SSTL-18 Class II 1.2-V-HSTL Class I 1.2-V-HSTL Class II 1.5-V-HSTL Class I 1.5-V-HSTL Class II 1.8-V-HSTL Class I 1.8-V-HSTL Class II 1.2-V POD 1.2-V 1.5-V 1.8-V None	SSTL-15 Class I	Specifies the I/O standard of the interface's strobe and data pins written to the .qip file of the IP instance. When you choose None, the I/O standard is unspecified in the generated IP.
Reference clock I/O configuration	Single-ended, LVDS with on-chip termination, LVDS without on-chip termination	Single-ended	Specify the reference clock I/O configuration.
General Settings
Fast simulation model	On, Off	Off	Turn on this option to reduce PHY Lite for Parallel Interfaces IP simulation time. Note: This option is preliminarily supported in Intel^® Quartus^® Prime v18.1.
Group <x> - these parameters are set on a per group basis
Group <x> Parameter Settings
Copy parameters from another group	On, Off	Off	Select this option when you want to copy the parameter settings from another group. Set Number of groups to more than 1 to enable this option.
Group	1 - 17	1	Choose the group index that you want as the parameter settings source. The changes made to the source is updated automatically to all the target groups. You can only choose the group index which the parameter settings are not copied from another group. Set Number of groups to more than 1 to enable this option.
Group <x> Pin Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Pin type	Input, Output, Bidirectional	Bidirectional	Direction of data pins. This value is set to Bidirectional by default.
Pin width	1 to 48	9	Number of pins in this data/strobe group. A data width up to 48 is achievable if no strobe is used in the group. The number of strobes is controlled by the Use output strobe, Strobe configuration and Use separate capture strobe parameters.
DDR/SDR	DDR, SDR	DDR	Double/single data rate.
Group <x> Input Path Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Read latency	1 to 63 external interface clock cycles	7	Expected read latency of the external device in memory clock cycles. For example, a design with an external clock frequency of 533 MHz in half-rate has a valid read latency range of 5 to 63 external interface clock cycles. Refer to the Read Latency topic for minimum read latency settings based on FPGA core clock rate.
Swap capture strobe polarity	On, Off	Off	Internally swap the negative and positive capture strobe input pins. This feature is only available for complementary strobe configurations.
Capture strobe phase shift	0, 45, 90, 135, 180	90	Internally phase shift the input strobe relative to input data.
Group <x> Output Path Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Write latency	0 to 3 (maximum value is dependent on the rate)	0	Additional delay added to the output data in memory clock cycles. Refer to the Write Latency topic for write latency settings based on FPGA core clock rate.
Use output strobe	On, Off	On	Use an output strobe.
Output strobe phase	0, 45, 90, 135, 180	90	Phase shift of the output strobe relative to the output data.
Group <x> General Data Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Data configuration	Single ended, Differential	Single ended	Selects the type of data. Single ended data type uses one pin. Differential data type uses 2 pins. Refer to the I/O Standards topic for a list of supported I/O standards.
Group <x> General Strobe Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Strobe configuration	Single ended, Differential, Complementary	Single ended	Select the type of strobe. A single ended strobe uses one pin, which reduces the maximum possible number of data pins in the group to 47. Differential/complementary strobe types use 2 pins, which reduces the maximum possible number of data pins in the group to 46. Note: The differential strobe configuration uses a differential input buffer, which produces a single clock for the capture DDIO and read FIFO. The complementary strobe configuration uses two single-ended input buffers and clocks the data into the capture DDIO and read FIFO using both clocks (as required by protocols such as QDRII). The output path functionality is the same. Refer to the I/O Standards topic for a list of supported I/O standards.
Use separate strobes	On, Off	Off	Separate the bidirectional strobe into input and output strobe pins. Use separate strobes is only available for a bidirectional data group with the output strobe enabled.
Group <x> OCT Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
OCT enable size	0 - 4 ( Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX devices)	1	Specifies the delay between the OCT enable signal assertion and the dqs_enable signal assertion. You must set a value that is large enough to ensure that the OCT is turn on before sampling input data. Note: For Intel^® Quartus^® Prime software version prior to 17.0, refer to related information for known issue.
Expose termination ports	On, Off	Off	Turn on to expose the series and parallel termination ports to connect separate OCT block. To enable this option, turn off Use Default OCT Values parameter and select a value for Input OCT Value or Output OCT Value parameters.
Use Default OCT Values	—		Use default OCT values based on the I/O standard parameter setting.
Input OCT Value	No termination, <n> ohm with calibration	No termination	Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to the I/O Standards topic for supported termination values. This option is available when the Use Default OCT Values option is disabled.
Output OCT Value	No termination, <n> ohm with calibration, <n> with no calibration	No termination	Specifies the group's data and strobe input termination values to be written to the .qip of the IP instance. The list of legal values is dependent on the I/O standard parameter setting. Refer to the I/O Standards topic for supported termination values. This option is available when the Use Default OCT Values option is disabled.
Group <x> Timing Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Generate Input Delay Constraints for this group	On, Off	On	Instructs SDC to generate set_input_delay constraints for this group.
Input Strobe Setup Delay Constraint	Constraint in ns	0.03 ns	Specifies the group's input setup delay constraint against the input strobe.
Input Strobe Hold Delay Constraint	Constraint in ns	0.03 ns	Specifies the group's input hold delay constraint against the input strobe.
Inter Symbol Interference of the Read Channel	Constraint in ns	0.09 ns	Specifies the Inter Symbol Interference value for `DQS` signal of read channel. Specify a positive value to decrease the setup and hold slack by half of the entered value.
Generate Output Delay Constraints for this group	On, Off	On	Instructs SDC to generate set_output_delay constraints for this group.
Output Strobe Setup Delay Constraint	Constraint in ns	0.03 ns	Specifies the group's output setup delay constraint against the input strobe.
Output Strobe Hold Delay Constraint	Constraint in ns	0.03 ns	Specifies the group's output hold delay constraint against the input strobe.
Inter Symbol Interference of the Write Channel	Constraint in ns	0.09 ns	Specifies the Inter Symbol Interference value for `DQS` signal of write channel. Specify a positive value to decrease the setup and hold slack by half of the entered value.
Group <x> Dynamic Reconfiguration Timing Settings Note: These parameters are disabled when Copy parameters from another group is enabled.
Dynamic Reconfiguration Read Deskew Algorithm	DQ Per-Bit Deskew, DQ Group Deskew, Custom Deskew	DQ Per-Bit Deskew	Specifies the Read Deskew algorithm for Timing Analyzer to use when performing I/O timing analysis: DQ Per-Bit Deskew: Each `DQ` pin is adjusted independently to minimize the skew within the DQ bits. `DQS` signal is adjusted to center-align to the de-skewed DQ bus. Each `DQ` bit may have different delay chain settings. DQ Group Deskew: `DQS` signal is adjusted center-align to the `DQ` bus without de-skewing individual DQ bits. All `DQ` bits within the same group has same delay chain settings. Custom Deskew: `DQS` is aligned based on the recoverable setup and hold slack you defined. You must select Use dynamic reconfiguration option to enable this parameter.
Setup Slack Recoverable of Custom Read Deskew Algorithm	Constraint in ns	0.0 ns	Specifies the amount of positive setup slack available based on your custom read deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Input or Bidirectional and Dynamic Reconfiguration Read Deskew Algorithm is set to Custom Deskew
Hold Slack Recoverable of Custom Read Deskew Algorithm	Constraint in ns	0.0 ns	Specifies the amount of positive hold slack available based on your custom read deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Input or Bidirectional and Dynamic Reconfiguration Read Deskew Algorithm is set to Custom Deskew
Dynamic Reconfiguration Write Deskew Algorithm	DQ Per-Bit Deskew, DQ Group Deskew, Custom Deskew	DQ Per-Bit Deskew	Specifies the Write Deskew algorithm for Timing Analyzer to use when performing I/O timing analysis: DQ Per-Bit Deskew: `DQS` signal is centered to each individual `DQ` bits. Each `DQ` bit may have different delay chain settings. DQ Group Deskew: `DQS` signal is centered to the `DQ` bus group. All `DQ` bits within the same group has same delay chain settings. Custom Deskew: `DQS` is aligned based on the recoverable setup and hold slack you defined. You must select Use dynamic reconfiguration option to enable this parameter.
Setup Slack Recoverable of Custom Write Deskew Algorithm	Constraint in ns	0.0 ns	Specifies the amount of positive setup slack available based on your custom write deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Output or Bidirectional and Dynamic Reconfiguration Write Deskew Algorithm is set to Custom Deskew
Hold Slack Recoverable of Custom Write Deskew Algorithm	Constraint in ns	0.0 ns	Specifies the amount of positive hold slack available based on your custom write deskew algorithm. This parameter is available with the conditions: Use dynamic reconfiguration is turn on Pin type is set to Output or Bidirectional and Dynamic Reconfiguration Write Deskew Algorithm is set to Custom Deskew

4.3.1.1. Read Latency

Table 70. Minimum Read Latency This table shows the minimum read latency value supported by PHY Lite for Parallel Interfaces based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate	VCO Multiplier Factor	Read Latency (External Memory Clock Cycle)
Full rate	1	4
	2	4
	4	3
	8	3
Half rate	1	5
	2	5
	4	4
	8	4
Quarter rate	1	7
	2	7
	4	7
	8	7

4.3.1.2. Write Latency

Table 71. Maximum Write LatencyThis shows the maximum write latency value supported by PHY Lite for Parallel Interfaces IP based on the core clock rate and VCO multiplier factor settings.
Core Clock Rate	VCO Multiplier Factor	Write Latency (External Memory Clock Cycle)
Full rate	1	0
	2	0
	4	0
	8	0
Half rate	1	1
	2	1
	4	1
	8	1
Quarter rate	1	3
	2	3
	4	3
	8	2

4.3.2. Signals

4.3.2.1. Clock and Reset Interface Signals

Table 72. Clock and Reset Interface Signals
Signal Name	Direction	Width	Description
`ref_clk`	Input	1	Reference clock for the PLL. The reference clock must be synchronous with `strobe_in` to ensure the `dqs_enable` signal is in-sync with `strobe_in`.
`reset_n`	Input	1	Resets the interface. This signal is asynchronous.
`interface_locked`	Output	1	Interface `locked` signal from PHY Lite for Parallel Interfaces IP to Intel FPGA core. This signal indicates that the PLL and PHY circuitry are locked. Data transfer should starts after the assertion of this signal.
`core_clk_out`	Output	1	Use this core clock in the core-to-periphery transfer of soft logic data and control signals. The `core_clk_out` frequency depends on the interface frequency and clock rate of user logic parameter.
`pll_extra_clock[0..3]`	Output	4	These are the additional output clock signals generated by PHY Lite for Parallel Interfaces IP when you enable Specify additional output clocks based on existing PLL parameter. Important: PHY Lite for Parallel Interfaces in Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX devices do not support exposing additional output clocks when VCO frequency is below 600 MHz.
`pll_locked`	Output	1	This is the locked signal for the additional output clocks generated by the IP.

4.3.2.2. Output Path Signals

Table 73. Output Path SignalsOutput path signals are signals that are available when you set the **Pin Type** parameter to either **Output** or **Bidirectional**.
Signal Name	Direction	Width	Description
`oe_from_core`	Input	Quarter-rate: 4 x `PIN_WIDTH` Half-rate: 2 x `PIN_WIDTH` Full-rate: 1 x `PIN_WIDTH`	Output enable signal from core logic. Synchronous to the `core_clk` output from the IP.
`data_from_core`	Input	Quarter rate-DDR: 8 x `PIN_WIDTH` Half-rate DDR: 4 x `PIN_WIDTH` Full-rate DDR: 2 x `PIN_WIDTH` Quarter-rate SDR: 4 x `PIN_WIDTH` Half-rate SDR: 2 x `PIN_WIDTH` Full-rate SDR: 1 x `PIN_WIDTH`	Data signal from core logic. Synchronous to the `core_clk` output from the IP.
`strobe_out_in`	Input	Quarter-rate: 8 Half-rate: 4 Full-rate: 2	Strobe signal from core logic. Synchronous to the `core_clk` output from the IP. Note: This path is always DDR.
`strobe_out_en`	Input	Quarter-rate: 4 Half-rate: 2 Full-rate: 1	Strobe output enable from core logic. Synchronous to the `core_clk` output from the IP.
`data_out/data_io`	Output/Bidirectional	1 to 48 if data configuration is Single Ended 1 to 24 if data configuration is Differential	Data output from PHY Lite for Parallel Interfaces IP. Synchronous to the `strobe_out` or `strobe_io` output from the IP. If the Pin Type parameter is set to Output, the `data_out` signals are used. If the Pin Type parameter is set to Bidirectional, the `data_io` signals are used.
`data_out_n/data_io_n`	Output/Bidirectional	1 to 24	Negative data output from PHY Lite for Parallel Interfaces IP is enabled when data configuration is set to Differential. Data is synchronous to the `strobe_out` or `strobe_io` output from the IP. If the Pin Type is set to Output, the `data_out_n` ports are used. If the pin type is set to Bidirectional, the `data_io_n` ports are used.
`strobe_out/strobe_io`	Output/Bidirectional	1	Positive output strobe from PHY Lite for Parallel Interfaces IP. If the Pin Type is set to Output, the `strobe_out` signal is used. If the Pin Type is set to Bidirectional the `strobe_io` signal is used. The Use Separate Strobes parameter forces the use of the `strobe_out` signal with a Bidirectional Pin Type.
`strobe_out_n/strobe_io_n`	Output/Bidirectional	1	Negative output strobe from PHY Lite for Parallel Interfaces IP. This is used if the Strobe Configuration is set to Differential or Complementary. If the Pin Type is set to Output, the `strobe_out_n` signal is used. If the Pin Type is set to Bidirectional, the `strobe_io_n` signal is used. The Use Separate Strobes parameter forces the use of the `strobe_out_n` signal with a Bidirectional Pin Type.

4.3.2.3. Input Path Signals

Table 74. Input Path SignalsInput path signals are signals that are available when you set the **Pin Type** parameter to **Input** or Bidirectional.
Signal Name	Direction	Width	Description
`data_to_core`	Output	Quarter-rate DDR: 8 x `PIN_WIDTH` Half-rate DDR: 4 x `PIN_WIDTH` Full-rate DDR: 2 x `PIN_WIDTH` Quarter-rate SDR: 4 x `PIN_WIDTH` Half-rate SDR: 2 x `PIN_WIDTH` Full-rate SDR: 1 x `PIN_WIDTH`	Output data to the core logic. Valid on `rdata_valid`. Synchronous to the `core_clk` output from the PHY Lite for Parallel Interfaces IP.
`rdata_en`	Input	Quarter-rate: 4 Half-rate: 2 Full-rate: 1	This signal represents the number of expected words to read from the external device. This signal is set to high after a read command is issued. Synchronous to the `core_clk` output from the PHY Lite for Parallel Interfaces IP. When using the IP as a receiver, assert this signal after `interface_locked` signal is asserted and `strobe_in` is stable.
`rdata_valid`	Output	Quarter-rate: 4 Half-rate: 2 Full-rate: 1	This signal determines which data are valid when reading from Read FIFO. Delayed by `READ_LATENCY` with margin and aligned to the core clock rate. For example, in quarter-rate, the delay is a multiple of 4 external clock cycles. Synchronous to the `core_clk` output from the PHY Lite for Parallel Interfaces IP.
`data_in/` `data_io`	Input/Bidirectional	1 to 48 if data configuration is Single Ended 1 to 24 if data configuration is Differential	Input and output data from/to external device. Synchronous to the `strobe_in` or `strobe_io` input. The first data_in must be associated with positive edge of `strobe_in`/`strobe_io`. If the pin type is set to Input, the `data_in` ports are used. If the pin type is set to bidirectional, the `data_io` ports are used.
`data_in_n/` `data_io_n`	Input/Bidirectional	1 to 24	Negative data input/output from external device enabled when data configuration is set to Differential. Data is synchronous to the `strobe_in` or `strobe_io` input. If the pin type is set to Input, the `data_in_n` ports are used. If the pin type is set to bidirectional, the `data_io_n` ports are used.
`strobe_in/strobe_io`	Input/Bidirectional	1	Input and output strobe from/to external device. If the pin type is set to Input, the `strobe_in` signal is used. If the pin type is set to Bidirectional, the `strobe_io` signal is used.
`strobe_in_n/strobe_io_n`	Input/Bidirectional	1	Negative strobe from/to external device. This is used if the Strobe Configuration parameter is set to Differential or Complementary. If the pin type is set to Input, the `strobe_in_n` signal is used. If the pin type is set to Bidirectional, the `strobe_io_n` signal is used.

4.3.2.4. Avalon Configuration Bus Interface Signals

The PHY Lite for Parallel Interfaces IP exposes the Avalon memory-mapped slave and Avalon memory-mapped master interfaces when you perform dynamic reconfiguration. Connect the Avalon memory-mapped slave to either a master in the core or the master interface of either an PHY Lite for Parallel Interfaces IP or the External Memory Interface IP to be placed in the same column. You can only connect the master interface to the slave interface of a PHY Lite for Parallel Interfaces IP or External Memory Interface IP to be placed in the same column.

Table 75. Avalon Memory-mapped Master Interface Signals
Signal Name	Direction	Width	Description
`avl_clk`	Input	1	Avalon interface clock.
`avl_reset_n`	Input	1	Reset input synchronous to `avl_clk`.
`avl_read`	Input	1	Read request from `io_aux`. This signal is synchronous to the `avl_clk` input.
`avl_write`	Input	1	Write request from `io_aux`. This signal is synchronous to the `avl_clk` input.
`avl_byteenable`	Input	4	Controls which bytes should be written on `avl_writedata`.
`avl_address`	Input	28 ( Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX devices)	Address from `io_aux`. This signal is synchronous to the `avl_clk` input.
`avl_readdata`	Output	32	Read data to `io_aux`. This signal is synchronous to the `avl_clk` input.
`avl_writedata`	Input	32	Write data from `io_aux`. This signal is synchronous to the `avl_clk` input.
`avl_readdata_valid`	Output	1	Indicates that read data has returned.
`avl_waitrequest`	Output	1	Stalls upstream logic when it is asserted.

Table 76. Avalon Memory-mapped Slave Interface Signals
Signal Name	Direction	Width	Description
`avl_out_clk`	Output	1	Connect this signal to the input Avalon interface of another PHY Lite for Parallel Interfaces IP or the External Memory Interfaces IP.
`avl_out_reset_n`	Output	1	Connect this signal to the input Avalon interface of another PHY Lite for Parallel Interfaces IP or the External Memory Interfaces FPGA IP.
`avl_out_read`	Output	1	Indicates read transaction.
`avl_out_write`	Output	1	Indicates write transaction.
`avl_out_byteenable`	Output	4	Controls which bytes should be written on `avl_out_writedata`.
`avl_out_writedata`	Output	32	The data packet associated with the write transaction.
`avl_out_address`	Output	28 ( Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX devices)	Avalon address (in byte granularity). Value is identical to `avl_address` but with zeroes padded on the LSBs.
`avl_out_readdata`	Input	32	The data packet associated with `avl_out_readdata_valid`.
`avl_out_readdata_valid`	Input	1	Indicates that read data has returned.
`avl_out_waitrequest`	Input	1	Stalls upstream logic when it is asserted.

4.3.2.5. Termination Signals

Table 77. Termination SignalsThe termination signals are signals that are available when you enable the **Expose termination ports** parameter.
Signal Name	Direction	Width	Description
`group_seriesterminationcontrol`	Input	16	Connect this signal to the series termination control signal of the OCT Intel^® FPGA IP to receive series termination code to calibrate R_s.
`group_parallelterminationcontrol`	Input	16	Connect this signal to the parallel termination control signal of the OCT Intel^® FPGA IP to receive parallel termination code to calibrate R_t.

4.4. I/O Standards

The PHY Lite for Parallel Interfaces IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.

Table 78. I/O Standards and Termination Values for Intel^® Arria^® 10 Devices
I/O Standard	Valid Input Terminations (Ω) ¹³	Valid Output Calibrated/Uncalibrated Terminations (Ω)¹³	RZQ (Ω) ¹⁴	Differential/Complementary I/O Support
SSTL-12 ¹⁵	60, 120	40, 60	240	Yes
SSTL-125 ¹⁵	60, 120	34, 40	240	Yes
SSTL-135 ¹⁵	60, 120	34, 40	240	Yes
SSTL-15 ¹⁵	60, 120	34, 40	240	Yes
SSTL-15 Class I ¹⁶	0, 50	0, 50	100	Yes
SSTL-15 Class II¹⁶	0, 50	0, 25	100	Yes
SSTL-18 Class I¹⁶	0, 50	0, 50	100	Yes
SSTL-18 Class II¹⁶	0, 50	0, 25	100	Yes
1.2-V HSTL Class I¹⁶	0, 50	0, 50	100	Yes
1.2-V HSTL Class II¹⁶	0, 50	0, 25	100	Yes
1.5-V HSTL Class I¹⁶	0, 50	0, 50	100	Yes
1.5-V HSTL Class II¹⁶	0, 50	0, 25	100	Yes
1.8-V HSTL Class I¹⁶	0, 50	0, 50	100	Yes
1.8-V HSTL Class II¹⁶	0, 50	0, 25	100	Yes
1.2-V POD	34, 40, 48, 60, 80, 120, 240	34, 40, 48, 60	240	Yes
1.2-V	—	—	—	No
1.5-V	—	—	—	No
1.8-V	—	—	—	No

Table 79. I/O Standards and Termination Values for Intel^® Cyclone^® 10 GX Devices
I/O Standard	Valid Input Terminations (Ω) ¹³	Valid Output Calibrated/Uncalibrated Terminations (Ω)¹³	RZQ (Ω) ¹⁴	Differential/Complementary I/O Support
SSTL-12 ¹⁷	60, 120	40, 60	240	Yes
SSTL-125 ¹⁷	60, 120	34, 40	240	Yes
SSTL-135 ¹⁷	60, 120	34, 40	240	Yes
SSTL-15 ¹⁷	60, 120	34, 40	240	Yes
SSTL-15 Class I ¹⁸	0, 50	0, 50	100	Yes
SSTL-15 Class II¹⁸	0, 50	0, 25	100	Yes
SSTL-18 Class I¹⁸	0, 50	0, 50	100	Yes
SSTL-18 Class II¹⁸	0, 50	0, 25	100	Yes
1.2-V HSTL Class I¹⁸	0, 50	0, 50	100	Yes
1.2-V HSTL Class II¹⁸	0, 50	0, 25	100	Yes
1.5-V HSTL Class I¹⁸	0, 50	0, 50	100	Yes
1.5-V HSTL Class II¹⁸	0, 50	0, 25	100	Yes
1.8-V HSTL Class I¹⁸	0, 50	0, 50	100	Yes
1.8-V HSTL Class II¹⁸	0, 50	0, 25	100	Yes
1.2-V POD	34, 40, 48, 60, 80, 120, 240	34, 40, 48, 60	240	Yes
1.2-V	—	—	—	No
1.5-V	—	—	—	No
1.8-V	—	—	—	No

¹³ 0 is equivalent to no termination.

¹⁴ RZQ pin is not required for uncalibrated output terminations.

¹⁵ Use this I/O standard if input termination is required with interface frequency more than 533 MHz.

¹⁶ Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.

¹⁷ Use this I/O standard if input termination is required with interface frequency more than 533 MHz.

¹⁸ Use this I/O standard if input termination is required with interface frequency equal or less than 533 MHz.

4.4.1. Input Buffer Reference Voltage (VREF)

The POD I/O standard allows configurable VREF. By default, the externally provided VREF is used and using an internal VREF requires the following .qsf assignments:

set_instance_assignment -name VREF_MODE <mode> -to <pin_name>

Note: The VREF settings are at the lane level, so all pins using a lane must have the same VREF settings (including GPIOs).

Table 80. VREF_MODE Description
VREF Mode	Description
EXTERNAL	Use the external VREF. This is the default.
CALIBRATED	Use internal VREF generated using VREF codes from the Avalon memory-mapped reconfiguration bus.
VCCIO_45	Use internal VREF generated using static VREF code. VREF is 45% of VCCIO
VCCIO_50	Use internal VREF generated using static VREF code. VREF is 50% of VCCIO
VCCIO_55	Use internal VREF generated using static VREF code. VREF is 55% of VCCIO
VCCIO_65	Use internal VREF generated using static VREF code. VREF is 65% of VCCIO
VCCIO_70	Use internal VREF generated using static VREF code. VREF is 70% of VCCIO
VCCIO_75	Use internal VREF generated using static VREF code. VREF is 75% of VCCIO

Figure 62. VREF

4.4.1.1. Calibrated VREF Settings

Table 81. Calibrated VREF SettingsThis table lists the calibrated VREF settings that you can set over the Avalon memory-mapped calibration bus. This table is applicable to all Intel FPGA devices.
avl_writedata[5:0]	% of VCCIO
000000	60.00%
000001	60.64%
000010	61.28%
000011	61.92%
000100	62.56%
000101	63.20%
000110	63.84%
000111	64.48%
001000	65.12%
001001	65.76%
001010	66.40%
001011	67.04%
001100	67.68%
001101	68.32%
001110	68.96%
001111	69.60%
010000	70.24%
010001	70.88%
010010	71.52%
010011	72.16%
010100	72.80%
010101	73.44%
010110	74.08%
010111	74.72%
011000	75.36%
011001	76.00%
011010	76.64%
011011	77.28%
011100	77.92%
011101	78.56%
011110	79.20%
011111	79.84%
100000	80.48%
100001	81.12%
100010	81.76%
100011	82.40%
100100	83.04%
100101	83.68%
100110	84.32%
100111	84.96%
101000	85.60%
101001	86.24%
101010	86.88%
101011	87.52%
101100	88.16%
101101	88.80%
101110	89.44%
101111	90.08%
110000	90.72%
110001	91.36%
110010	92.00%
110011 -> 111111	Reserved

4.4.2. On-Chip Termination (OCT)

PHY Lite for Parallel Interfaces IP provides valid OCT settings for each group (refer to the I/O Standards topic for supported termination values). These settings are written to the .qip of the instance during generation. If you select an I/O standard that supports OCT in the General tab, you can use the OCT blocks provided in the Intel^® Arria^® 10 and Intel^® Cyclone^® 10 GX devices.

You can instantiate the OCT block in one of two ways:

Using RZQ_GROUP assignment in the assignment editor, or
Manual insertion of OCT block

4.4.2.1. RZQ_GROUP Assignment

The RZQ_GROUP assignment creates the OCT Intel FPGA IP without modifying the RTL. The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the Fitter creates the pin name along with the OCT Intel FPGA IP and its corresponding connections. This allows you to create a group of pins to be calibrated by an existing or non-existing OCT and the Fitter ensures the legality of the design. You must associate the terminated pins of the PHY Lite for Parallel Interfaces IP instance with an RZQ pin at the system level manually.

Use the following steps to set RZQ pin locations for the PHY Lite for Parallel Interfaces IP:

In the Group <x> OCT Settings tab, disable Use Default OCT Values and Expose termination ports.

Figure 63. Group <x> OCT Settings Parameter Settings
Generate the IP or instantiate the IP into your project.
You can view the available RZQ pins location in the Pin Planner. Go to Pin Planner > Tasks > OCT Pins and double click the RZQ. The available RZQ pins are display in the pin grid diagram.
You can modify the qsf in your project to change the default RZQ location using the following command:
```
set_location_assignment <rzq_capable_pin_location> –to <user_defined_rzq_pin_name>
```

Use the following command to associate the terminated pins of the IP with the RZQ pin:

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <altera_phylite_strobe_pin>

set_instance_assignment -name RZQ_GROUP <rzq_pin_name> -to <altera_phylite_data_pin[*]>

where * represents all the data pins within the same group.

This is an example of a qsf file with modified RZQ pin location assignments:

set_location_assignment PIN_AH3 -to octrzq
set_instance_assignment -name IO_STANDARD "1.5 V" -to octrzq
set_instance_assignment -name RZQ_GROUP OCTRZQ -to group_0_io_interface_conduit_end_io_strobe_io
set_instance_assignment -name RZQ_GROUP OCTRZQ -to group_0_io_interface_conduit_end_io_data_io[*]

Compile the project.
To verify that the Intel^® Quartus^® Prime has successfully created and assigned the RZQ pin to the correct location, go to Pin Planner > Node Name and look for <user_defined_rzq_pin_name> with the assigned pin location in the list.

4.4.2.2. Manual Insertion of OCT Block

You may also instantiate the OCT Intel FPGA IP separately in your project and connect the termination ports to the PHY Lite for Parallel Interfaces.

Expose the PHY Lite for Parallel Interfaces termination ports by disable Use Default OCT Values.
Select the available OCT values in the Input OCT Value parameter. This displays the Expose termination ports parameter.
Note: For supported input and output OCT values, refer to the I/O Standards topic.
Select Expose termination ports to expose the termination ports in the IP.
Connect the termination ports to a OCT Intel FPGA IP either in power-up or user mode.

Figure 64. RTL View of PHY Lite for Parallel Interfaces IP Interfacing with OCT Intel FPGA IP in User Mode

4.5. Design Guidelines

4.5.1. Guidelines: Group Pin Placement

Follow these guidelines to place the PHY Lite for Parallel Interfaces IP group pins.

All groups in a PHY Lite for Parallel Interfaces IP must be placed across a contiguous set of lanes. The number of lanes depends on the number of pins used by the group.
Two groups, from either the same or different PHY Lite for Parallel Interfaces IP, cannot share an I/O lane.
For PHY Lite for Parallel Interfaces IP instance that spans more than one I/O bank, all groups in the interface must be placed across a contiguous set of banks within an I/O column. The number of I/O banks required depends on the memory interface width.
Pins that are not used in an I/O bank are available as general purpose I/O (GPIO) pins.
To constrain groups from separate PHY Lite for Parallel Interfaces IP instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies, and the same voltage settings. The number of I/O banks must be at least as many as the number of PHY Lite for Parallel Interfaces IP interfaces.
A reference clock network can only span across maximum of 6 I/O banks.
You cannot share the OCT termination block across the I/O column. You can associate the terminated pins of the PHY Lite for Parallel Interfaces IP instance with an RZQ pin through RZQ_GROUP assignment.

Table 82. Group Pin Placement PHY Lite for Parallel Interfaces IP does not support `DQS` for X4.
Number of Pins in Group	Valid DQS Group in a Bank	Valid Index in a Bank
1-12	DQS for X8/X9	{0-11}/{12-23}/{24-35}/{36-47}
13-24	DQS for X16/X18	{0-23}/{24-47}
25-48	DQS for X32/X36	{0-47}

4.5.2. Reference Clock

You are recommended to source the reference clock to the PHY Lite for Parallel Interfaces IP from a dedicated clock pin. Use the clock pin in one of the I/O banks used by the PHY Lite for Parallel Interfaces IP. You must use contiguous I/O banks to implement multiple interfaces (consisting of a combination of External Memory Interface and PHY Lite for Parallel Interfaces IP). If you use the same reference clock for these interfaces, place the reference clock in any of the contiguous I/O banks.

4.5.3. Reset

You can source the reset to the PHY Lite for Parallel Interfaces IP from an external pin or from the core. If you source the reset from an external pin, you must configure the I/O standard of the reset signal in the .qsf file with the following command:

set_location_asignment <PIN_NUMBER> -to <signal_name>

4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank

4.5.5. Dynamic Reconfiguration

If you are using the dynamic reconfiguration feature, all interfaces of the External Memory Interfaces and PHY Lite for Parallel Interfaces IP cores in the same I/O column must share the reset signal. Multiple IP cores requiring Avalon core access require daisy chain connectivity.

4.5.6. Timing

The