External Memory Interfaces
Intel® Cyclone® 10 GX devices provide an efficient architecture that allows up to 72 bit wide of DDR3 memory interfaces at up to 1,866 Mbps. This is to support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are designed to provide high-performance support for existing and emerging external memory standards.
Compared to previous generation of Cyclone® FPGAs, the new architecture, and solution provide the following advantages:
- Pre-closed timing in the controller and from the controller to the PHY
- Easier pin placement
For maximum performance and flexibility, the architecture offers hard memory controller and hard PHY for key interfaces.
- The solution offers completely hardened external memory interfaces for several protocols
- The devices feature columns of I/Os that are mixed within the core logic fabric instead of I/O banks on the device periphery
- A single hard Nios® II processor block calibrates all the memory interfaces in an I/O column
- The I/O columns are composed of groups of I/O modules called I/O banks
- Each I/O bank contains a dedicated integer PLL (IO_PLL), hard memory controller, and delay-locked loop
- The PHY clock tree is shorter compared to previous generation Cyclone® devices and only spans one I/O bank