UDPIP-10/25G: 10G/25G UDP/IP Hardware Protocol Stack
このオファーについて
The core is a UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables media streaming with speeds up to 25Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programmability of all the required network parameters (local, destination, and gateway IP addresses; UDP ports; and MAC address). The core implements the ARP Protocol, which is critical for multiple access networks, and the Echo-Request and Reply Messages of the ICMP are widely used to test network connectivity. It can use a static IP address or automatically request and acquire an IP address from a DHCP server. Finally, the core supports 801.1Q tagging and is suitable for operation in a Virtual LAN. The core is easy to integrate into systems with or without a host processor. Packet data can be read/written to the core via dedicated streaming-capable interfaces, or via registers mapped on an SoC bus.
技術仕様
- カテゴリー:
- ソフトウェアと IP コア: FPGA 知的財産コア: インターフェイス・プロトコル: イーサネット
- エンドカスタマーのタイプ:
-
中小規模のビジネス
その他
エンタープライズ
リソース
インテルのテクノロジーを含む

Intel Agilex® 5 FPGA および SoC FPGA

インテル® Arria® 10 FPGA & SoC FPGA

インテル® Stratix® 10 FPGA & SoC FPGA

インテル® Agilex™ 9 FPGA & SoC FPGA

インテル® Agilex™ 7 FPGA & SoC FPGA
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Udpip-10/25g: 10g/25g Udp/ip Hardware Protocol Stack
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